IGT bits for small-bar

index 593b01ba5..441b377b7 100644
@@ -169,7 +169,9 @@ struct drm_xe_query_mem_usage {
 		__u32 max_page_size;
 		__u64 total_size;
 		__u64 used;
-		__u64 reserved[8];
+		__u64 cpu_visible_size;
+		__u64 cpu_visible_used;
+		__u64 reserved[6];
 	} regions[];
 };
 

@@ -270,6 +272,7 @@ struct drm_xe_gem_create {
 	 */
 #define XE_GEM_CREATE_FLAG_DEFER_BACKING	(0x1 << 24)
 #define XE_GEM_CREATE_FLAG_SCANOUT		(0x1 << 25)
+#define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(0x1 << 26)
 	__u32 flags;
 
 	/**

index 47be8f301..81a9ec664 100644
@@ -140,6 +140,17 @@ static uint64_t gt_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
 	return 0;
 }
 
+static uint64_t gt_visible_vram_size(const struct drm_xe_query_mem_usage *mem_usage,
+				     const struct drm_xe_query_gts *gts, int gt)
+{
+	int region_idx = ffs(native_region_for_gt(gts, gt)) - 1;
+
+	if (XE_IS_CLASS_VRAM(&mem_usage->regions[region_idx]))
+		return mem_usage->regions[region_idx].cpu_visible_size;
+
+	return 0;
+}
+
 static bool __mem_has_vram(struct drm_xe_query_mem_usage *mem_usage)
 {
 	for (int i = 0; i < mem_usage->num_regions; i++)

@@ -246,9 +257,14 @@ struct xe_device *xe_device_get(int fd)
 	xe_dev->hw_engines = xe_query_engines_new(fd, &xe_dev->number_hw_engines);
 	xe_dev->mem_usage = xe_query_mem_usage_new(fd);
 	xe_dev->vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->vram_size));
-	for (int gt = 0; gt < xe_dev->number_gt; gt++)
+	xe_dev->visible_vram_size = calloc(xe_dev->number_gt, sizeof(*xe_dev->visible_vram_size));
+	for (int gt = 0; gt < xe_dev->number_gt; gt++) {
 		xe_dev->vram_size[gt] = gt_vram_size(xe_dev->mem_usage,
 						     xe_dev->gts, gt);
+		xe_dev->visible_vram_size[gt] =
+			gt_visible_vram_size(xe_dev->mem_usage,
+					     xe_dev->gts, gt);
+	}
 	xe_dev->default_alignment = __mem_default_alignment(xe_dev->mem_usage);
 	xe_dev->has_vram = __mem_has_vram(xe_dev->mem_usage);
 

@@ -383,6 +399,33 @@ uint64_t vram_memory(int fd, int gt)
 	return xe_has_vram(fd) ? native_region_for_gt(xe_dev->gts, gt) : 0;
 }
 
+static uint64_t __xe_visible_vram_size(int fd, int gt)
+{
+	struct xe_device *xe_dev;
+
+	xe_dev = find_in_cache(fd);
+	igt_assert(xe_dev);
+
+	return xe_dev->visible_vram_size[gt];
+}
+
+/**
+ * visible_vram_memory:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id, with
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM also set, to ensure that CPU access is
+ * possible.
+ */
+uint64_t visible_vram_memory(int fd, int gt)
+{
+	if (__xe_visible_vram_size(fd, gt))
+		return vram_memory(fd, gt) | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
+	else
+		return vram_memory(fd, gt); /* older kernel */
+}
+
 /**
  * vram_if_possible:
  * @fd: xe device fd

@@ -396,6 +439,28 @@ uint64_t vram_if_possible(int fd, int gt)
 	return vram_memory(fd, gt) ?: system_memory(fd);
 }
 
+/**
+ * visible_vram_if_possible:
+ * @fd: xe device fd
+ * @gt: gt id
+ *
+ * Returns vram memory bitmask for xe device @fd and @gt id or system memory if
+ * there's no vram memory available for @gt. Also attaches the
+ * XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM to ensure that CPU access is possible
+ * when using vram.
+ */
+uint64_t visible_vram_if_possible(int fd, int gt)
+{
+	uint64_t regions = all_memory_regions(fd);
+	uint64_t system_memory = regions & 0x1;
+	uint64_t vram = regions & (0x2 << gt);
+
+	if (__xe_visible_vram_size(fd, gt))
+		return vram ? vram | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM : system_memory;
+	else
+		return vram ? vram : system_memory; /* older kernel */
+}
+
 /**
  * xe_hw_engines:
  * @fd: xe device fd

@@ -512,6 +577,24 @@ uint64_t xe_vram_size(int fd, int gt)
 	return xe_dev->vram_size[gt];
 }
 
+/**
+ * xe_visible_vram_size:
+ * @fd: xe device fd
+ * @gt: gt
+ *
+ * Returns size of visible vram of xe device @fd.
+ */
+uint64_t xe_visible_vram_size(int fd, int gt)
+{
+	uint64_t visible_size;
+
+	visible_size = __xe_visible_vram_size(fd, gt);
+	if (!visible_size) /* older kernel */
+		visible_size = xe_vram_size(fd, gt);
+
+	return visible_size;
+}
+
 /**
  * xe_get_default_alignment:
  * @fd: xe device fd

@@ -528,6 +611,7 @@ xe_dev_FN(xe_get_default_alignment, default_alignment, uint32_t);
  */
 xe_dev_FN(xe_va_bits, va_bits, uint32_t);
 
+
 /**
  * xe_dev_id:
  * @fd: xe device fd

index 943ca558a..e2e5dcd00 100644
@@ -47,6 +47,9 @@ struct xe_device {
 	/** @vram_size: array of vram sizes for all gts */
 	uint64_t *vram_size;
 
+	/** @visible_vram_size: array of visible vram sizes for all gts */
+	uint64_t *visible_vram_size;
+
 	/** @default_alignment: safe alignment regardless region location */
 	uint32_t default_alignment;
 

@@ -80,7 +83,9 @@ unsigned int xe_number_gt(int fd);
 uint64_t all_memory_regions(int fd);
 uint64_t system_memory(int fd);
 uint64_t vram_memory(int fd, int gt);
+uint64_t visible_vram_memory(int fd, int gt);
 uint64_t vram_if_possible(int fd, int gt);
+uint64_t visible_vram_if_possible(int fd, int gt);
 struct drm_xe_engine_class_instance *xe_hw_engines(int fd);
 struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx);
 struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region);

@@ -89,6 +94,7 @@ uint32_t xe_min_page_size(int fd, uint64_t region);
 unsigned int xe_number_hw_engines(int fd);
 bool xe_has_vram(int fd);
 uint64_t xe_vram_size(int fd, int gt);
+uint64_t xe_visible_vram_size(int fd, int gt);
 uint32_t xe_get_default_alignment(int fd);
 uint32_t xe_va_bits(int fd);
 uint16_t xe_dev_id(int fd);

index a5c0cbbf6..519018eb3 100644
@@ -794,7 +794,7 @@ static void draw_rect_render(int fd, struct cmd_data *cmd_data,
 	else
 		tmp.handle = xe_bo_create_flags(fd, 0,
 						ALIGN(tmp.size, xe_get_default_alignment(fd)),
-						vram_if_possible(fd, 0));
+						visible_vram_if_possible(fd, 0));
 
 	tmp.stride = rect->w * pixel_size;
 	tmp.bpp = buf->bpp;

index 9be312a28..e5e52946e 100644
@@ -1192,7 +1192,7 @@ static int create_bo_for_fb(struct igt_fb *fb, bool prefer_sysmem)
 			igt_assert(err == 0 || err == -EOPNOTSUPP);
 		} else if (is_xe_device(fd)) {
 			fb->gem_handle = xe_bo_create_flags(fd, 0, fb->size,
-							vram_if_possible(fd, 0));
+							visible_vram_if_possible(fd, 0));
 		} else if (is_vc4_device(fd)) {
 			fb->gem_handle = igt_vc4_create_bo(fd, fb->size);
 

index 3cd680072..047843006 100644
@@ -943,7 +943,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
 
 		ibb->alignment = xe_get_default_alignment(fd);
 		size = ALIGN(size, ibb->alignment);
-		ibb->handle = xe_bo_create_flags(fd, 0, size, vram_if_possible(fd, 0));
+		ibb->handle = xe_bo_create_flags(fd, 0, size, visible_vram_if_possible(fd, 0));
 
 		/* Limit to 48-bit due to MI_* address limitation */
 		ibb->gtt_size = 1ull << min_t(uint32_t, xe_va_bits(fd), 48);

@@ -1399,7 +1399,7 @@ void intel_bb_reset(struct intel_bb *ibb, bool purge_objects_cache)
 		ibb->handle = gem_create(ibb->fd, ibb->size);
 	else
 		ibb->handle = xe_bo_create_flags(ibb->fd, 0, ibb->size,
-						 vram_if_possible(ibb->fd, 0));
+						 visible_vram_if_possible(ibb->fd, 0));
 
 	/* Reacquire offset for RELOC and SIMPLE */
 	if (ibb->allocator_type == INTEL_ALLOCATOR_SIMPLE ||

index 856d0ba22..3266905c9 100644
@@ -100,7 +100,8 @@ void xe_cork_init(int fd, struct drm_xe_engine_class_instance *hwe,
 
 	vm = xe_vm_create(fd, 0, 0);
 
-	bo = xe_bo_create(fd, hwe->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, hwe->gt_id));
 	spin = xe_bo_map(fd, bo, 0x1000);
 
 	xe_vm_bind_sync(fd, vm, bo, 0, addr, bo_size);

index 1d7ffc60f..05f2bc643 100644
@@ -123,7 +123,8 @@ test_export_dma_buf(struct drm_xe_engine_class_instance *hwe0,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd[0]),
 			xe_get_default_alignment(fd[0]));
 	for (i = 0; i < n_bo; ++i) {
-		bo[i] = xe_bo_create(fd[0], hwe0->gt_id, 0, bo_size);
+		bo[i] = xe_bo_create_flags(fd[0], 0, bo_size,
+					   visible_vram_if_possible(fd[0], hwe0->gt_id));
 		dma_buf_fd[i] = prime_handle_to_fd(fd[0], bo[i]);
 		import_bo[i] = prime_fd_to_handle(fd[1], dma_buf_fd[i]);
 

index 7fef4efc5..5f99a11cd 100644
@@ -98,15 +98,17 @@ test_evict(int fd, struct drm_xe_engine_class_instance *eci,
                                 i < n_execs / 8 ? 0 : vm;
 
 			if (flags & MULTI_VM) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, 0,
-							    bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, 0,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else if (flags & THREADED) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id, vm,
-							    bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, vm,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else {
 				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
 								  bo_size,
-								  vram_memory(fd, eci->gt_id) |
+								  visible_vram_memory(fd, eci->gt_id) |
 								  system_memory(fd));
 			}
 		} else {

@@ -281,16 +283,17 @@ test_evict_cm(int fd, struct drm_xe_engine_class_instance *eci,
                                 i < n_execs / 8 ? 0 : vm;
 
 			if (flags & MULTI_VM) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
-							    0, bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, 0,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else if (flags & THREADED) {
-				__bo = bo[i] = xe_bo_create(fd, eci->gt_id,
-							    vm, bo_size);
+				__bo = bo[i] = xe_bo_create_flags(fd, vm,
+								  bo_size,
+								  visible_vram_memory(fd, eci->gt_id));
 			} else {
 				__bo = bo[i] = xe_bo_create_flags(fd, _vm,
 								  bo_size,
-								  vram_memory(fd, eci->gt_id) |
-								  system_memory(fd));
+								  visible_vram_memory(fd, eci->gt_id));
 			}
 		} else {
 			__bo = bo[i % (n_execs / 2)];

@@ -453,9 +456,15 @@ threads(int fd, struct drm_xe_engine_class_instance *eci,
 		pthread_join(threads_data[i].thread, NULL);
 }
 
+#define SZ_256M	0x10000000
+#define SZ_1G	0x40000000
+
 static uint64_t calc_bo_size(uint64_t vram_size, int mul, int div)
 {
-	return (ALIGN(vram_size, 0x40000000)  * mul) / div;
+	if (vram_size >= SZ_1G)
+		return (ALIGN(vram_size, SZ_1G)  * mul) / div;
+	else
+		return (ALIGN(vram_size, SZ_256M)  * mul) / div; /* small-bar */
 }
 
 /**

@@ -670,7 +679,7 @@ igt_main
 		fd = drm_open_driver(DRIVER_XE);
 		xe_device_get(fd);
 		igt_require(xe_has_vram(fd));
-		vram_size = xe_vram_size(fd, 0);
+		vram_size = xe_visible_vram_size(fd, 0);
 		igt_assert(vram_size);
 
 		xe_for_each_hw_engine(fd, hwe)

index 2018c8104..f0b25b782 100644
@@ -70,7 +70,7 @@ static void test_all_active(int fd, int gt, int class)
 	bo_size = sizeof(*data) * num_placements;
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, gt, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < num_placements; i++) {

@@ -229,7 +229,7 @@ test_exec(int fd, int gt, int class, int n_engines, int n_execs,
 		}
 		memset(data, 0, bo_size);
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 

@@ -454,7 +454,7 @@ test_cm(int fd, int gt, int class, int n_engines, int n_execs,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

index 059e6ae89..64c0a5b5e 100644
@@ -130,15 +130,14 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 		}
 		memset(data, 0, bo_size);
 	} else {
-		if (flags & DEFER_ALLOC) {
-			bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
-						bo_size,
-						vram_if_possible(fd, eci->gt_id) |
-						XE_GEM_CREATE_FLAG_DEFER_BACKING);
-		} else {
-			bo = xe_bo_create(fd, eci->gt_id, n_vm == 1 ? vm[0] : 0,
-					  bo_size);
-		}
+		uint32_t bo_flags;
+
+		bo_flags = visible_vram_if_possible(fd, eci->gt_id);
+		if (flags & DEFER_ALLOC)
+			bo_flags |= XE_GEM_CREATE_FLAG_DEFER_BACKING;
+
+		bo = xe_bo_create_flags(fd, n_vm == 1 ? vm[0] : 0,
+					bo_size, bo_flags);
 		if (!(flags & DEFER_BIND))
 			data = xe_bo_map(fd, bo, bo_size);
 	}

index 685193990..4506046f6 100644
@@ -152,8 +152,8 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, flags & VM_FOR_BO ? vm : 0,
-				  bo_size);
+		bo = xe_bo_create_flags(fd, flags & VM_FOR_BO ? vm : 0,
+					bo_size, visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

index a3ab17270..742e955f8 100644
@@ -157,9 +157,11 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci,
 	} else {
 		if (flags & PREFETCH)
 			bo = xe_bo_create_flags(fd, 0, bo_size,
-						all_memory_regions(fd));
+						all_memory_regions(fd) |
+						visible_vram_if_possible(fd, 0));
 		else
-			bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+			bo = xe_bo_create_flags(fd, 0, bo_size,
+						visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

@@ -390,8 +392,10 @@ test_atomic(int fd, struct drm_xe_engine_class_instance *eci,
 	addr_wait = addr + bo_size;
 
 	bo = xe_bo_create_flags(fd, vm, bo_size,
-				all_memory_regions(fd));
-	bo_wait = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+				all_memory_regions(fd) |
+				visible_vram_if_possible(fd, 0));
+	bo_wait = xe_bo_create_flags(fd, vm, bo_size,
+				     visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 	wait = xe_bo_map(fd, bo_wait, bo_size);
 	ptr = &data[0].data;

index 0d72a3f20..c002b7882 100644
@@ -51,7 +51,8 @@ static void test_spin(int fd, struct drm_xe_engine_class_instance *eci)
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	spin = xe_bo_map(fd, bo, bo_size);
 
 	engine = xe_engine_create(fd, vm, eci, 0);

@@ -197,7 +198,7 @@ test_balancer(int fd, int gt, int class, int n_engines, int n_execs,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, gt, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, gt));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {

@@ -398,7 +399,8 @@ test_legacy_mode(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {

@@ -577,7 +579,8 @@ test_compute_mode(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 	memset(data, 0, bo_size);
 

@@ -710,7 +713,7 @@ static void submit_jobs(struct gt_thread_data *t)
 	uint32_t bo;
 	uint32_t *data;
 
-	bo = xe_bo_create(fd, 0, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
 	data = xe_bo_map(fd, bo, bo_size);
 	data[0] = MI_BATCH_BUFFER_END;
 

index 2e7779777..033c5859c 100644
@@ -107,7 +107,8 @@ test_balancer(int fd, int gt, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, gt, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, gt));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

@@ -310,7 +311,8 @@ test_compute_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, 0, bo_size);
+		bo = xe_bo_create_flags(fd, 0, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

@@ -522,7 +524,8 @@ test_legacy_mode(int fd, uint32_t vm, uint64_t addr, uint64_t userptr,
 			igt_assert(data);
 		}
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		data = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(data, 0, bo_size);

index 5c71ae147..e2d917d64 100644
@@ -64,7 +64,8 @@ static void exec_basic(int fd, struct drm_xe_engine_class_instance *eci,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {

index 420c7f86c..7bfe72e51 100644
@@ -124,10 +124,10 @@ igt_main
 		test_mmap(fd, system_memory(fd));
 
 	igt_subtest("vram")
-		test_mmap(fd, vram_memory(fd, 0));
+		test_mmap(fd, visible_vram_memory(fd, 0));
 
 	igt_subtest("vram-system")
-		test_mmap(fd, vram_memory(fd, 0) | system_memory(fd));
+		test_mmap(fd, visible_vram_memory(fd, 0) | system_memory(fd));
 
 	igt_subtest("bad-flags")
 		test_bad_flags(fd);

index 355626e32..e4df09240 100644
@@ -255,7 +255,8 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
 	if (check_rpm && runtime_usage_available(device.pci_xe))
 		rpm_usage = igt_pm_get_runtime_usage(device.pci_xe);
 
-	bo = xe_bo_create(device.fd_xe, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(device.fd_xe, vm, bo_size,
+				visible_vram_if_possible(device.fd_xe, eci->gt_id));
 	data = xe_bo_map(device.fd_xe, bo, bo_size);
 
 	for (i = 0; i < n_engines; i++) {

index c2b292c15..2d5ae08ea 100644
@@ -109,7 +109,7 @@ static void test_with_fd_dup(void)
 	fd2 = drm_open_driver(DRIVER_XE);
 	xe_device_get(fd2);
 
-	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd1 = prime_handle_to_fd(fd1, handle);
 	gem_close(fd1, handle);

@@ -148,8 +148,8 @@ static void test_with_two_bos(void)
 	fd2 = drm_open_driver(DRIVER_XE);
 	xe_device_get(fd2);
 
-	handle1 = xe_bo_create(fd1, 0, 0, BO_SIZE);
-	handle2 = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle1 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
+	handle2 = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd = prime_handle_to_fd(fd1, handle1);
 	handle_import = prime_fd_to_handle(fd2, dma_buf_fd);

@@ -227,7 +227,7 @@ static void test_with_one_bo(void)
 	fd2 = drm_open_driver(DRIVER_XE);
 	xe_device_get(fd2);
 
-	handle = xe_bo_create(fd1, 0, 0, BO_SIZE);
+	handle = xe_bo_create_flags(fd1, 0, BO_SIZE, visible_vram_if_possible(fd1, 0));
 
 	dma_buf_fd = prime_handle_to_fd(fd1, handle);
 	handle_import1 = prime_fd_to_handle(fd2, dma_buf_fd);

index 861822b48..2af07c379 100644
@@ -52,7 +52,8 @@ write_dwords(int fd, uint32_t vm, int n_dwords, uint64_t *addrs)
 	batch_size = (n_dwords * 4 + 1) * sizeof(uint32_t);
 	batch_size = ALIGN(batch_size + xe_cs_prefetch_size(fd),
 			   xe_get_default_alignment(fd));
-	batch_bo = xe_bo_create(fd, 0, vm, batch_size);
+	batch_bo = xe_bo_create_flags(fd, vm, batch_size,
+				      visible_vram_if_possible(fd, 0));
 	batch_map = xe_bo_map(fd, batch_bo, batch_size);
 
 	for (i = 0; i < n_dwords; i++) {

@@ -117,7 +118,7 @@ __test_bind_one_bo(int fd, uint32_t vm, int n_addrs, uint64_t *addrs)
 		vms = malloc(sizeof(*vms) * n_addrs);
 		igt_assert(vms);
 	}
-	bo = xe_bo_create(fd, 0, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size, visible_vram_if_possible(fd, 0));
 	map = xe_bo_map(fd, bo, bo_size);
 	memset(map, 0, bo_size);
 

@@ -562,7 +563,8 @@ shared_pte_page(int fd, struct drm_xe_engine_class_instance *eci, int n_bo,
 			xe_get_default_alignment(fd));
 
 	for (i = 0; i < n_bo; ++i) {
-		bo[i] = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo[i] = xe_bo_create_flags(fd, vm, bo_size,
+					   visible_vram_if_possible(fd, eci->gt_id));
 		data[i] = xe_bo_map(fd, bo[i], bo_size);
 	}
 

@@ -731,7 +733,8 @@ test_bind_engines_independent(int fd, struct drm_xe_engine_class_instance *eci)
 	bo_size = sizeof(*data) * N_ENGINES;
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	for (i = 0; i < N_ENGINES; i++) {

@@ -892,7 +895,8 @@ test_bind_array(int fd, struct drm_xe_engine_class_instance *eci, int n_execs,
 	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd),
 			xe_get_default_alignment(fd));
 
-	bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+	bo = xe_bo_create_flags(fd, vm, bo_size,
+				visible_vram_if_possible(fd, eci->gt_id));
 	data = xe_bo_map(fd, bo, bo_size);
 
 	if (flags & BIND_ARRAY_BIND_ENGINE_FLAG)

@@ -1088,7 +1092,11 @@ test_large_binds(int fd, struct drm_xe_engine_class_instance *eci,
 		map = aligned_alloc(xe_get_default_alignment(fd), bo_size);
 		igt_assert(map);
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		igt_skip_on(xe_visible_vram_size(fd, 0) && bo_size >
+			    xe_visible_vram_size(fd, 0));
+
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		map = xe_bo_map(fd, bo, bo_size);
 	}
 

@@ -1367,7 +1375,8 @@ test_munmap_style_unbind(int fd, struct drm_xe_engine_class_instance *eci,
 			    MAP_ANONYMOUS, -1, 0);
 		igt_assert(map != MAP_FAILED);
 	} else {
-		bo = xe_bo_create(fd, eci->gt_id, vm, bo_size);
+		bo = xe_bo_create_flags(fd, vm, bo_size,
+					visible_vram_if_possible(fd, eci->gt_id));
 		map = xe_bo_map(fd, bo, bo_size);
 	}
 	memset(map, 0, bo_size);

index 40bd19ae7..6c74a96a0 100644
@@ -230,6 +230,23 @@ test_query_mem_usage(int fd)
 		igt_info("min_page_size=0x%x, max_page_size=0x%x\n",
 		       mem_usage->regions[i].min_page_size,
 		       mem_usage->regions[i].max_page_size);
+
+		igt_info("visible size=%lluMiB\n",
+			 mem_usage->regions[i].cpu_visible_size >> 20);
+		igt_info("visible used=%lluMiB\n",
+			 mem_usage->regions[i].cpu_visible_used >> 20);
+
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_size,
+				   mem_usage->regions[i].total_size);
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].cpu_visible_size);
+		igt_assert_lte_u64(mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].used);
+		igt_assert_lte_u64(mem_usage->regions[i].used,
+				   mem_usage->regions[i].total_size);
+		igt_assert_lte_u64(mem_usage->regions[i].used -
+				   mem_usage->regions[i].cpu_visible_used,
+				   mem_usage->regions[i].total_size);
 	}
 	dump_hex_debug(mem_usage, query.size);
 	free(mem_usage);

index 66a8393fe..6c14f03d1 100644
@@ -232,17 +232,31 @@ void xe_vm_destroy(int fd, uint32_t vm)
 	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_VM_DESTROY, &destroy), 0);
 }
 
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+			      uint32_t *handle)
+{
+	struct drm_xe_gem_create create = {
+		.vm_id = vm,
+		.size = size,
+		.flags = flags,
+	};
+	int err;
+
+	err = igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create);
+	if (err)
+		return err;
+
+	*handle = create.handle;
+	return 0;
+}
+
 uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags)
 {
-	struct drm_xe_gem_create create = {
-		.vm_id = vm,
-		.size = size,
-		.flags = flags,
-	};
+	uint32_t handle;
 
-	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_GEM_CREATE, &create), 0);
+	igt_assert_eq(__xe_bo_create_flags(fd, vm, size, flags, &handle), 0);
 
-	return create.handle;
+	return handle;
 }
 
 uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size)

index 049cd183d..85389eff5 100644
@@ -64,6 +64,8 @@ void xe_vm_unbind_all_async(int fd, uint32_t vm, uint32_t engine,
 			    uint32_t bo, struct drm_xe_sync *sync,
 			    uint32_t num_syncs);
 void xe_vm_destroy(int fd, uint32_t vm);
+uint32_t __xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags,
+			      uint32_t *handle);
 uint32_t xe_bo_create_flags(int fd, uint32_t vm, uint64_t size, uint32_t flags);
 uint32_t xe_bo_create(int fd, int gt, uint32_t vm, uint64_t size);
 uint32_t xe_engine_create(int fd, uint32_t vm,

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