dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
Subsystems (2)
cover dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
From: Conor Dooley <[email protected]>
Do the various bits needed to drop the additionalProperties: true that we currently have in riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.
Conor Dooley (6):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: allow clocks property
dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
dt-bindings: riscv: cpus: permit operating-points-v2
dt-bindings: riscv: cpus: document cpu-supply
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
.../devicetree/bindings/riscv/cpus.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
Signature · 1 line
2.39.2
PATCH 1/6 dt-bindings: riscv: cpus: add a ref the common cpu schema
From: Conor Dooley <[email protected]>
To permit validation of RISC-V cpu nodes, "additionalProperties: true" needs to be swapped for "unevaluatedProperties: false". To facilitate this in a way that passes dt_binding_check, a reference to the cpu schema is required.
Disallow the generic cache-op-block-size property that that drags in, since the RISC-V CBO extensions do not require a common size, and have individual properties.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +6 -0
@@ -23,6 +23,9 @@ description: | two cores, each of which has two hyperthreads, could be described as having four harts. +allOf: + - $ref: /schemas/cpu.yaml# + properties: compatible: oneOf:
@@ -98,6 +101,9 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + # RISC-V has multiple properties for cache op block sizes as the sizes + # differ between individual CBO extensions + cache-op-block-size: false # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
Signature · 1 line
2.39.2
PATCH 2/6 dt-bindings: riscv: cpus: allow clocks property
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
Having disallowed additionalProperties, dtbs_check complains about unevaluated clocks properties. Permit a single clock, as that's all any current dts uses.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +3 -0
@@ -58,6 +58,9 @@ properties: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart. + clocks: + maxItems: 1 + mmu-type: description: Identifies the MMU address translation mode used on this
Signature · 7 lines
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PATCH 3/6 dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
With "additionalProperties: true" removed from cpus.yaml, dtbs_check complains that #cooling-cells is a disallowed property. Add a ref to the binding in which it is defined to satisfy the checks.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -0
@@ -25,6 +25,7 @@ description: | allOf: - $ref: /schemas/cpu.yaml# + - $ref: /schemas/thermal/thermal-cooling-devices.yaml# properties: compatible:
Signature · 1 line
2.39.2
PATCH 4/6 dt-bindings: riscv: cpus: permit operating-points-v2
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
To allow setting "unevaluatedProperties: false" for cpus.yaml, permit the operating points property for RISC-V cpu nodes.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -0
@@ -108,6 +108,7 @@ properties: # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions cache-op-block-size: false + operating-points-v2: true # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false
Signature · 1 line
2.39.2
PATCH 5/6 dt-bindings: riscv: cpus: document cpu-supply
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
To facilitate switching to "unevaluatedProperties: false", document the cpu-supply property that is already in use in several Allwinner devicetrees.
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/riscv/cpus.yaml +4 -0
@@ -62,6 +62,10 @@ properties: clocks: maxItems: 1 + cpu-supply: + description: + Regulator supplying the CPU's power rail. + mmu-type: description: Identifies the MMU address translation mode used on this
Signature · 1 line
2.39.2
PATCH 6/6 dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
To permit validation of cpu nodes, swap "additionalProperties: true" out for "unevaluatedProperties: false".
--- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +1 -1
@@ -152,7 +152,7 @@ required: - riscv,isa - interrupt-controller -additionalProperties: true +unevaluatedProperties: false examples: - |
Signature · 7 lines
2.39.2 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Rob Herring
maintainerQuoted 5 lines · Conor Dooley
From: Conor Dooley <[email protected]>
Do the various bits needed to drop the additionalProperties: true that we currently have in
riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.
Arm needs pretty much all the same properties. I started on adding them to cpu.yaml a while back. Let me finish that up.
Quoted 9 lines
CC Rob Herring <[email protected]>CC Krzysztof Kozlowski <[email protected]>CC Paul Walmsley <[email protected]>CC Palmer Dabbelt <[email protected]>
Quoted 3 lines
Conor Dooley (6):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: allow clocks property
I just have 'clocks: true', so if you want to keep this setting it to 1 clock that's fine. But I imagine that it's just a matter of time until someone wants more clocks.
Quoted 11 lines
dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
dt-bindings: riscv: cpus: permit operating-points-v2
dt-bindings: riscv: cpus: document cpu-supply
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false.../devicetree/bindings/riscv/cpus.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)Signature · 1 line
2.39.2
Quoted 9 lines · Rob Herring
Quoted 5 lines · Conor Dooley
From: Conor Dooley <[email protected]>
Do the various bits needed to drop the additionalProperties: true that we currently have in
riscv/cpu.yaml, to permit actually enforcing what people put in cpus nodes.Arm needs pretty much all the same properties. I started on adding them to
cpu.yamla while back. Let me finish that up.
Cool, I see you've already updated dt-schema. I'll go update mine & cull whatever is no longer needed here.
Quoted 8 lines
Quoted 8 lines
CC Rob Herring <[email protected]>CC Krzysztof Kozlowski <[email protected]>CC Paul Walmsley <[email protected]>CC Palmer Dabbelt <[email protected]>
Quoted 7 lines
Quoted 3 lines
Conor Dooley (6):
dt-bindings: riscv: cpus: add a ref the common cpu schema
dt-bindings: riscv: cpus: allow clocks propertyI just have 'clocks: true', so if you want to keep this setting it to 1 clock that's fine. But I imagine that it's just a matter of time until someone wants more clocks.
Yeah, I said something to that affect in the commit message. I don't doubt that it'll show up at some point, was just enabling the minimum that I know of SoCs requiring at the moment. "clocks: true" WFM.
Cheers,
Conor.
Quoted 11 lines
Quoted 11 lines
dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
dt-bindings: riscv: cpus: permit operating-points-v2
dt-bindings: riscv: cpus: document cpu-supply
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false.../devicetree/bindings/riscv/cpus.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)Signature · 1 line
2.39.2