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FAILED: patch "[PATCH] drm/amd/display: Set minimum requirement for using PSR-SU on" failed to apply to 6.1-stable tree

PATCH [email protected] 1 participant 1 message Jul 21, 2023

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core
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The patch below does not apply to the 6.1-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y
git checkout FETCH_HEAD
git cherry-pick -x cd2e31a9ab93d13c412a36c6e26811e0f830985b
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023072121-hypnotism-wheat-48ff@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^..

Possible dependencies:

cd2e31a9ab93 ("drm/amd/display: Set minimum requirement for using PSR-SU on Phoenix") c35b6ea8f2ec ("drm/amd/display: Set minimum requirement for using PSR-SU on Rembrandt") 268182606f26 ("drm/amd/display: Update correct DCN314 register header")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From cd2e31a9ab93d13c412a36c6e26811e0f830985b Mon Sep 17 00:00:00 2001
From: Mario Limonciello <[email protected]>
Date: Fri, 23 Jun 2023 10:05:21 -0500
Subject: [PATCH] drm/amd/display: Set minimum requirement for using PSR-SU on
Phoenix

The same parade TCON issue can potentially happen on Phoenix, and the same PSR resilience changes have been ported into the DMUB firmware.

Don't allow running PSR-SU unless on the newer firmware.

Cc [email protected]
Cc Sean Wang <[email protected]>
Cc Marc Rossi <[email protected]>
Cc Hamza Mahfooz <[email protected]>
Cc Tsung-hua (Ryan) Lin <[email protected]>
Signed-off-by Mario Limonciello <[email protected]>
Reviewed-by Leo Li <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c +5 -0
index 48a06dbd9be7..f161aeb7e7c4 100644
@@ -60,3 +60,8 @@ const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs = {
 	{ DMUB_DCN31_FIELDS() },
 #undef DMUB_SF
 };
+
+bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)
+{
+	return dmub->fw_version >= DMUB_FW_VERSION(8, 0, 16);
+}
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h +2 -0
index 674267a2940e..f213bd82c911 100644
@@ -30,4 +30,6 @@
 
 extern const struct dmub_srv_dcn31_regs dmub_srv_dcn314_regs;
 
+bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);
+
 #endif /* _DMUB_DCN314_H_ */
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +1 -0
index 7a31e3e27bab..bdaf43892f47 100644
@@ -228,6 +228,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 	case DMUB_ASIC_DCN316:
 		if (asic == DMUB_ASIC_DCN314) {
 			dmub->regs_dcn31 = &dmub_srv_dcn314_regs;
+			funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported;
 		} else if (asic == DMUB_ASIC_DCN315) {
 			dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
 		} else if (asic == DMUB_ASIC_DCN316) {