Add USB PHY and USB dts node for JH7110
Subsystems (3)
cover Add USB PHY and USB dts node for JH7110
Add USB and USB/PCIe PHY dts node for StarFive JH7110. The PHY driver is in linux-phy-next tree.
Minda Chen (2):
riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
riscv: dts: starfive: Add USB dts node for JH7110
.../jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+)
base-commit: f2b539af5718bb63eb9fd913d9d4474bd1e55d07
Signature · 1 line
2.25.1
PATCH 1/2 riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.
--- arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
arch/riscv/boot/dts/starfive/jh7110.dtsi +21 -0
@@ -446,6 +446,27 @@ i2c2: i2c@10050000 { status = "disabled"; }; + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;
Signature · 1 line
2.25.1
PATCH 2/2 riscv: dts: starfive: Add USB dts node for JH7110
In reply to Minda ChenAdd USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board.
--- .../jh7110-starfive-visionfive-2.dtsi | 5 +++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 32 +++++++++++++++++++ 2 files changed, 37 insertions(+)
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +5 -0
@@ -273,6 +273,11 @@ &uart0 { status = "okay"; }; +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + &U74_1 { cpu-supply = <&vdd_cpu>; };
arch/riscv/boot/dts/starfive/jh7110.dtsi +32 -0
@@ -446,6 +446,38 @@ i2c2: i2c@10050000 { status = "disabled"; }; + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + usbphy0: phy@10200000 { compatible = "starfive,jh7110-usb-phy"; reg = <0x0 0x10200000 0x0 0x10000>;
Signature · 1 line
2.25.1
From: Conor Dooley <[email protected]>
Quoted 8 lines · Minda Chen
Add USB and USB/PCIe PHY dts node for StarFive JH7110. The PHY driver is in linux-phy-next tree.
Minda Chen (2):
riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
riscv: dts: starfive: Add USB dts node for JH7110[...]
Applied to riscv-dt-for-next, thanks!
[1/2] riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
https://git.kernel.org/conor/c/c2a10081c033 [2/2] riscv: dts: starfive: Add USB dts node for JH7110 https://git.kernel.org/conor/c/e126aa3abc4e
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv