drm/msm/adreno: Move away from legacy revision matching
Subsystems (6)
v2 cover drm/msm/adreno: Move away from legacy revision matching
From: Rob Clark <[email protected]>
Downstream seems to be moving to using the chip_id as simply an opaque identifier, and if we want to avoid headaches with userspace mesa supporting both kgsl and upstream, we should move away from the assumption that certain bits in the chip_id have a specific meaning.
v2 adds a patch to move adreno_info to adreno_platform_config rather than needing to look it up in multiple places.
Rob Clark (13):
drm/msm/adreno: Remove GPU name
drm/msm/adreno: Remove redundant gmem size param drm/msm/adreno: Remove redundant revn param drm/msm/adreno: Use quirk identify hw_apriv drm/msm/adreno: Use quirk to identify cached-coherent support drm/msm/adreno: Allow SoC specific gpu device table entries drm/msm/adreno: Move speedbin mapping to device table drm/msm/adreno: Bring the a630 family together drm/msm/adreno: Add adreno family
drm/msm/adreno: Add helper for formating chip-id drm/msm/adreno: Move adreno info to config
dt-bindings: drm/msm/gpu: Extend bindings for chip-id drm/msm/adreno: Switch to chip-id for identifying GPU
.../devicetree/bindings/display/msm/gpu.yaml | 6 + drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 189 ++--------- drivers/gpu/drm/msm/adreno/adreno_device.c | 294 ++++++++++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 53 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 154 ++++++--- 10 files changed, 365 insertions(+), 357 deletions(-)
Signature · 1 line
2.41.0
PATCH v2 1/13 drm/msm/adreno: Remove GPU name
From: Rob Clark <[email protected]>
No real need to have marketing names in the kernel.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
Reviewed-by Dmitry Baryshkov <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 25 ---------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 3 files changed, 5 insertions(+), 34 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +0 -25
@@ -24,7 +24,6 @@ static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), .revn = 200, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw",
@@ -35,7 +34,6 @@ static const struct adreno_info gpulist[] = { }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), .revn = 201, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw",
@@ -46,7 +44,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), .revn = 220, - .name = "A220", .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", [ADRENO_FW_PFP] = "leia_pfp_470.fw",
@@ -57,7 +54,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), .revn = 305, - .name = "A305", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -68,7 +64,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 6, 0), .revn = 307, /* because a305c is revn==306 */ - .name = "A306", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -79,7 +74,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .revn = 320, - .name = "A320", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw",
@@ -90,7 +84,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), .revn = 330, - .name = "A330", .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", [ADRENO_FW_PFP] = "a330_pfp.fw",
@@ -101,7 +94,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), .revn = 405, - .name = "A405", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -112,7 +104,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), .revn = 420, - .name = "A420", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -123,7 +114,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), .revn = 430, - .name = "A430", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw",
@@ -134,7 +124,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), .revn = 506, - .name = "A506", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -152,7 +141,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), .revn = 508, - .name = "A508", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -169,7 +157,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), .revn = 509, - .name = "A509", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -187,7 +174,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, - .name = "A510", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -202,7 +188,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), .revn = 512, - .name = "A512", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -219,7 +204,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, - .name = "A530", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -238,7 +222,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), .revn = 540, - .name = "A540", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw",
@@ -256,7 +239,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), .revn = 610, - .name = "A610", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", },
@@ -268,7 +250,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, - .name = "A618", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin",
@@ -279,7 +260,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, - .name = "A619", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a619_gmu.bin",
@@ -292,7 +272,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, - .name = "A630", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin",
@@ -305,7 +284,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), .revn = 640, - .name = "A640", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin",
@@ -318,7 +296,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, - .name = "A650", .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", [ADRENO_FW_GMU] = "a650_gmu.bin",
@@ -332,7 +309,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, - .name = "A660", .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin",
@@ -357,7 +333,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, - .name = "A680", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin",
drivers/gpu/drm/msm/adreno/adreno_gpu.c +5 -8
@@ -1105,14 +1105,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin =0xffff ; adreno_gpu->speedbin = (uint16_t ) (0xffff & speedbin); - gpu_name = adreno_gpu->info->name; -if (!gpu_name) { - gpu_name =devm_kasprintf (dev,GFP_KERNEL ,"%d.%d.%d.%d" , - rev->core, rev->major, rev->minor, - rev->patchid); -if (!gpu_name) -return -ENOMEM ; - } + gpu_name =devm_kasprintf (dev,GFP_KERNEL ,"%d.%d.%d.%d" , + rev->core, rev->major, rev->minor, + rev->patchid); +if (!gpu_name) +return -ENOMEM ; adreno_gpu_config.ioname ="kgsl_3d0_reg_memory" ;
drivers/gpu/drm/msm/adreno/adreno_gpu.h +0 -1
@@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[];struct adreno_info {struct adreno_rev rev;uint32_t revn; -const char *name;const char *fw[ADRENO_FW_MAX ];uint32_t gmem;u64 quirks;
Signature · 1 line
2.41.0
PATCH v2 2/13 drm/msm/adreno: Remove redundant gmem size param
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Even in the ocmem case, the allocated ocmem buffer size should match the requested size.
v2: Move stray hunk to previous patch, make OCMEM size mismatch an error
condition.
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 5 files changed, 8 insertions(+), 8 deletions(-)
drivers/gpu/drm/msm/adreno/a2xx_gpu.c +1 -1
@@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);for (i =3 ; i <=5 ; i++) -if ((SZ_16K << i) == adreno_gpu->gmem) +if ((SZ_16K << i) == adreno_gpu->info->gmem)break ;gpu_write (gpu,REG_A2XX_RB_EDRAM_INFO , i);
drivers/gpu/drm/msm/adreno/a5xx_gpu.c +1 -1
@@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MIN_LO ,0x00100000 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MIN_HI ,0x00000000 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MAX_LO , -0x00100000 + adreno_gpu->gmem -1 ); +0x00100000 + adreno_gpu->info->gmem -1 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MAX_HI ,0x00000000 ); if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +1 -1
@@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu)gpu_write64 (gpu,REG_A6XX_UCHE_GMEM_RANGE_MIN ,0x00100000 );gpu_write64 (gpu,REG_A6XX_UCHE_GMEM_RANGE_MAX , -0x00100000 + adreno_gpu->gmem -1 ); +0x00100000 + adreno_gpu->info->gmem -1 ); }gpu_write (gpu,REG_A6XX_UCHE_FILTER_CNTL ,0x804 );
drivers/gpu/drm/msm/adreno/adreno_gpu.c +5 -4
@@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = adreno_gpu->info->revn;return 0 ;case MSM_PARAM_GMEM_SIZE : - *value = adreno_gpu->gmem; + *value = adreno_gpu->info->gmem;return 0 ;case MSM_PARAM_GMEM_BASE : *value = !adreno_is_a650_family (adreno_gpu) ?0x100000 :0 ;
@@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,return PTR_ERR (ocmem); } - ocmem_hdl =ocmem_allocate (ocmem,OCMEM_GRAPHICS , adreno_gpu->gmem); + ocmem_hdl =ocmem_allocate (ocmem,OCMEM_GRAPHICS , adreno_gpu->info->gmem);if (IS_ERR (ocmem_hdl))return PTR_ERR (ocmem_hdl); adreno_ocmem->ocmem = ocmem; adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->hdl = ocmem_hdl; - adreno_gpu->gmem = ocmem_hdl->len; + +if (WARN_ON (ocmem_hdl->len != adreno_gpu->info->gmem)) +return -ENOMEM ;return 0 ; }
@@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info =adreno_info (config->rev); - adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev;
drivers/gpu/drm/msm/adreno/adreno_gpu.h +0 -1
@@ -77,7 +77,6 @@ struct adreno_gpu {struct msm_gpu base;struct adreno_rev rev;const struct adreno_info *info; -uint32_t gmem;/* actual gmem size */ uint32_t revn;/* numeric revision name */ uint16_t speedbin;const struct adreno_gpu_funcs *funcs;
Signature · 1 line
2.41.0
Re: [PATCH v2 02/13] drm/msm/adreno: Remove redundant gmem size param
Quoted 10 lines · Rob Clark
From: Rob Clark <[email protected]>
Even in the ocmem case, the allocated ocmem buffer size should match the requested size.
v2: Move stray hunk to previous patch, make OCMEM size mismatch an error
condition.Signed-off-by Rob Clark <[email protected]>
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 102 lines
--- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 5 files changed, 8 insertions(+), 8 deletions(-)drivers/gpu/drm/msm/adreno/a2xx_gpu.c +1
-1@@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT);for (i =3 ; i <=5 ; i++) -if ((SZ_16K << i) == adreno_gpu->gmem) +if ((SZ_16K << i) == adreno_gpu->info->gmem)break ;gpu_write (gpu,REG_A2XX_RB_EDRAM_INFO , i);drivers/gpu/drm/msm/adreno/a5xx_gpu.c +1
-1@@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MIN_LO ,0x00100000 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MIN_HI ,0x00000000 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MAX_LO , -0x00100000 + adreno_gpu->gmem -1 ); +0x00100000 + adreno_gpu->info->gmem -1 );gpu_write (gpu,REG_A5XX_UCHE_GMEM_RANGE_MAX_HI ,0x00000000 ); if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) ||drivers/gpu/drm/msm/adreno/a6xx_gpu.c +1
-1@@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu)gpu_write64 (gpu,REG_A6XX_UCHE_GMEM_RANGE_MIN ,0x00100000 );gpu_write64 (gpu,REG_A6XX_UCHE_GMEM_RANGE_MAX , -0x00100000 + adreno_gpu->gmem -1 ); +0x00100000 + adreno_gpu->info->gmem -1 ); }gpu_write (gpu,REG_A6XX_UCHE_FILTER_CNTL ,0x804 );drivers/gpu/drm/msm/adreno/adreno_gpu.c +5
-4@@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = adreno_gpu->info->revn;return 0 ;case MSM_PARAM_GMEM_SIZE : - *value = adreno_gpu->gmem; + *value = adreno_gpu->info->gmem;return 0 ;case MSM_PARAM_GMEM_BASE : *value = !adreno_is_a650_family (adreno_gpu) ?0x100000 :0 ;@@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,return PTR_ERR (ocmem); } - ocmem_hdl =ocmem_allocate (ocmem,OCMEM_GRAPHICS , adreno_gpu->gmem); + ocmem_hdl =ocmem_allocate (ocmem,OCMEM_GRAPHICS , adreno_gpu->info->gmem);if (IS_ERR (ocmem_hdl))return PTR_ERR (ocmem_hdl); adreno_ocmem->ocmem = ocmem; adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->hdl = ocmem_hdl; - adreno_gpu->gmem = ocmem_hdl->len; + +if (WARN_ON (ocmem_hdl->len != adreno_gpu->info->gmem)) +return -ENOMEM ;return 0 ; }@@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info =adreno_info (config->rev); - adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev;drivers/gpu/drm/msm/adreno/adreno_gpu.h +0
-2@@ -77,7 +77,6 @@ struct adreno_gpu {struct msm_gpu base;struct adreno_rev rev;const struct adreno_info *info; -uint32_t gmem;/* actual gmem size */ uint32_t revn;/* numeric revision name */ uint16_t speedbin;const struct adreno_gpu_funcs *funcs; --2.41.0
Signature · 2 lines
With best wishes Dmitry
PATCH v2 3/13 drm/msm/adreno: Remove redundant revn param
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
This just duplicates what is in adreno_info, and can cause confusion if used before it is set.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
Reviewed-by Dmitry Baryshkov <[email protected]>
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 -- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++------------- 3 files changed, 9 insertions(+), 16 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +0 -2
@@ -2484,8 +2484,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)return ERR_PTR (-EINVAL );/* Assign these early so that we can use the is_aXYZ helpers */ -/* Numeric revision IDs (e.g. 630) */ - adreno_gpu->revn = info->revn;/* New-style ADRENO_REV()-only */ adreno_gpu->rev = info->rev;/* Quirk data */
drivers/gpu/drm/msm/adreno/adreno_gpu.c +0 -1
@@ -1099,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info =adreno_info (config->rev); - adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev;if (adreno_read_speedbin (dev, &speedbin) || !speedbin)
drivers/gpu/drm/msm/adreno/adreno_gpu.h +9 -13
@@ -77,7 +77,6 @@ struct adreno_gpu {struct msm_gpu base;struct adreno_rev rev;const struct adreno_info *info; -uint32_t revn;/* numeric revision name */ uint16_t speedbin;const struct adreno_gpu_funcs *funcs;
@@ -147,10 +146,9 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);static inline bool adreno_is_revn (const struct adreno_gpu *gpu,uint32_t revn) { -/* revn can be zero, but if not is set at same time as info */ -WARN_ON_ONCE (!gpu->info); - -return gpu->revn == revn; +if (WARN_ON_ONCE (!gpu->info)) +return false; +return gpu->info->revn == revn; }static inline bool adreno_has_gmu_wrapper (const struct adreno_gpu *gpu)
@@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu)static inline bool adreno_is_a2xx (const struct adreno_gpu *gpu) { -/* revn can be zero, but if not is set at same time as info */ -WARN_ON_ONCE (!gpu->info); - -return (gpu->revn <300 ); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return (gpu->info->revn <300 ); }static inline bool adreno_is_a20x (const struct adreno_gpu *gpu) { -/* revn can be zero, but if not is set at same time as info */ -WARN_ON_ONCE (!gpu->info); - -return (gpu->revn <210 ); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return (gpu->info->revn <210 ); }static inline bool adreno_is_a225 (const struct adreno_gpu *gpu)
Signature · 1 line
2.41.0
PATCH v2 4/13 drm/msm/adreno: Use quirk identify hw_apriv
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Rather than just open coding a list of gpu-id matches.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
Reviewed-by Dmitry Baryshkov <[email protected]>
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +1 -2
@@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)/* Quirk data */ adreno_gpu->info = info; -if (adreno_is_a650 (adreno_gpu) ||adreno_is_a660_family (adreno_gpu)) - adreno_gpu->base.hw_apriv = true; + adreno_gpu->base.hw_apriv = !!(info->quirks &ADRENO_QUIRK_HAS_HW_APRIV );a6xx_llc_slices_init (pdev, a6xx_gpu);
drivers/gpu/drm/msm/adreno/adreno_device.c +4 -0
@@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg,
@@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg,
@@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G,
@@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg,
drivers/gpu/drm/msm/adreno/adreno_gpu.h +1 -0
@@ -32,6 +32,7 @@ enum {#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) +#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)struct adreno_rev {uint8_t core;
Signature · 1 line
2.41.0
PATCH v2 5/13 drm/msm/adreno: Use quirk to identify cached-coherent support
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +16 -7
@@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID),
@@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg,
@@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg,
@@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg,
@@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg,
@@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg,
@@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G,
@@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg,
@@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks =ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg,
@@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)if (ret)return ret; -if (config.rev.core >=6 ) -if (!adreno_has_gmu_wrapper (to_adreno_gpu (gpu))) - priv->has_cached_coherent = true; + priv->has_cached_coherent = + !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ) && + !adreno_has_gmu_wrapper (to_adreno_gpu (gpu));return 0 ; }
drivers/gpu/drm/msm/adreno/adreno_gpu.h +1 -0
@@ -33,6 +33,7 @@ enum {#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)struct adreno_rev {uint8_t core;
Signature · 1 line
2.41.0
Re: [PATCH v2 05/13] drm/msm/adreno: Use quirk to identify cached-coherent support
Quoted 7 lines · Rob Clark
From: Rob Clark <[email protected]>
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value.
Quoted 6 lines
Signed-off-by Rob Clark <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>--- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-)
Reviewed-by Dmitry Baryshkov <[email protected]>
Signature · 2 lines
With best wishes Dmitry
PATCH v2 6/13 drm/msm/adreno: Allow SoC specific gpu device table entries
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings.
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +30 -4
@@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619,
@@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)/* identify gpu: */ for (i =0 ; i <ARRAY_SIZE (gpulist); i++) {const struct adreno_info *info = &gpulist[i]; +if (info->machine && !of_machine_is_compatible (info->machine)) +continue ;if (adreno_cmp_rev (info->rev, rev))return info; }
@@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core ==2 ; + priv->has_cached_coherent = + !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ); gpu = info->init (drm);if (IS_ERR (gpu)) {
@@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)if (ret)return ret; - priv->has_cached_coherent = - !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ) && - !adreno_has_gmu_wrapper (to_adreno_gpu (gpu)); -return 0 ; }
drivers/gpu/drm/msm/adreno/adreno_gpu.h +1 -0
@@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hextern const struct adreno_reglist a660_hwcg[], a690_hwcg[];struct adreno_info { +const char *machine;struct adreno_rev rev;uint32_t revn;const char *fw[ADRENO_FW_MAX ];
Signature · 1 line
2.41.0
Re: [PATCH v2 06/13] drm/msm/adreno: Allow SoC specific gpu device table entries
Quoted 18 lines · Rob Clark
From: Rob Clark <[email protected]>
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings.
Signed-off-by Rob Clark <[email protected]>--- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-)drivers/gpu/drm/msm/adreno/adreno_device.c +0
-0
drivers/gpu/drm/msm/adreno/adreno_device.c static const struct adreno_info gpulist[] = { · line 267
Quoted 10 lines
drivers/gpu/drm/msm/adreno/adreno_device.c +7
-0@@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin",
If those are GMU-less platforms, do we need the ADRENO_FW_GMU firmware?
Other than that:
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 66 lines
drivers/gpu/drm/msm/adreno/adreno_device.c +23
-4+ }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619,@@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)/* identify gpu: */ for (i =0 ; i <ARRAY_SIZE (gpulist); i++) {const struct adreno_info *info = &gpulist[i]; +if (info->machine && !of_machine_is_compatible (info->machine)) +continue ;if (adreno_cmp_rev (info->rev, rev))return info; }@@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core ==2 ; + priv->has_cached_coherent = + !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ); gpu = info->init (drm);if (IS_ERR (gpu)) {@@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)if (ret)return ret; - priv->has_cached_coherent = - !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ) && - !adreno_has_gmu_wrapper (to_adreno_gpu (gpu)); -return 0 ; }drivers/gpu/drm/msm/adreno/adreno_gpu.h +1
-1@@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hextern const struct adreno_reglist a660_hwcg[], a690_hwcg[];struct adreno_info { +const char *machine;struct adreno_rev rev;uint32_t revn;const char *fw[ADRENO_FW_MAX ]; --2.41.0
Signature · 2 lines
With best wishes Dmitry
Re: [PATCH v2 06/13] drm/msm/adreno: Allow SoC specific gpu device table entries
Quoted 24 lines · Dmitry Baryshkov
Quoted 22 lines · Rob Clark
From: Rob Clark <[email protected]>
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings.
Signed-off-by Rob Clark <[email protected]>--- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-)drivers/gpu/drm/msm/adreno/adreno_device.c +1
-0@@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, {
Quoted 8 lines
drivers/gpu/drm/msm/adreno/adreno_device.c static const struct adreno_info gpulist[] = { · line 267
Quoted 6 lines
drivers/gpu/drm/msm/adreno/adreno_device.c +6
-0+ .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin",If those are GMU-less platforms, do we need the
ADRENO_FW_GMUfirmware?
ahh, good point, fixed that locally
Quoted 3 lines
Other than that:
Reviewed-by Dmitry Baryshkov <[email protected]>
thanks
BR,
-R
Quoted 71 lines
Quoted 64 lines
drivers/gpu/drm/msm/adreno/adreno_device.c +23
-4+ }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619,@@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev)/* identify gpu: */ for (i =0 ; i <ARRAY_SIZE (gpulist); i++) {const struct adreno_info *info = &gpulist[i]; +if (info->machine && !of_machine_is_compatible (info->machine)) +continue ;if (adreno_cmp_rev (info->rev, rev))return info; }@@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core ==2 ; + priv->has_cached_coherent = + !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ); gpu = info->init (drm);if (IS_ERR (gpu)) {@@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)if (ret)return ret; - priv->has_cached_coherent = - !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT ) && - !adreno_has_gmu_wrapper (to_adreno_gpu (gpu)); -return 0 ; }drivers/gpu/drm/msm/adreno/adreno_gpu.h +1
-1@@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hextern const struct adreno_reglist a660_hwcg[], a690_hwcg[];struct adreno_info { +const char *machine;struct adreno_rev rev;uint32_t revn;const char *fw[ADRENO_FW_MAX ]; --Quoted 2 lines
2.41.0
--
With best wishes
Dmitry
PATCH v2 7/13 drm/msm/adreno: Move speedbin mapping to device table
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
This simplifies the code.
v2: Use a table of structs instead of flat uint32_t[]
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++++ 3 files changed, 97 insertions(+), 155 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +16 -155
@@ -2204,159 +2204,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)return progress; } -static u32 a610_get_speed_bin (u32 fuse) +static u32 fuse_to_supp_hw (const struct adreno_info *info,u32 fuse) { -/* -* There are (at least) three SoCs implementing A610: SM6125 (trinket), -* SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, -* as only a single SKU exists and we don't support khaje upstream yet. -* Hence, this matching table is only valid for bengal and can be easily -* expanded if need be. -*/ - -if (fuse ==0 ) -return 0 ; -else if (fuse ==206 ) -return 1 ; -else if (fuse ==200 ) -return 2 ; -else if (fuse ==157 ) -return 3 ; -else if (fuse ==127 ) -return 4 ; - -return UINT_MAX ; -} - -static u32 a618_get_speed_bin (u32 fuse) -{ -if (fuse ==0 ) -return 0 ; -else if (fuse ==169 ) -return 1 ; -else if (fuse ==174 ) -return 2 ; - -return UINT_MAX ; -} - -static u32 a619_holi_get_speed_bin (u32 fuse) -{ -/* -* There are (at least) two SoCs implementing A619_holi: SM4350 (holi) -* and SM6375 (blair). Limit the fuse matching to the corresponding -* SoC to prevent bogus frequency setting (as improbable as it may be, -* given unexpected fuse values are.. unexpected! But still possible.) -*/ - -if (fuse ==0 ) -return 0 ; - -if (of_machine_is_compatible ("qcom,sm4350" )) { -if (fuse ==138 ) -return 1 ; -else if (fuse ==92 ) -return 2 ; - }else if (of_machine_is_compatible ("qcom,sm6375" )) { -if (fuse ==190 ) -return 1 ; -else if (fuse ==177 ) -return 2 ; - }else -pr_warn ("Unknown SoC implementing A619_holi!\n" ); - -return UINT_MAX ; -} - -static u32 a619_get_speed_bin (u32 fuse) -{ -if (fuse ==0 ) -return 0 ; -else if (fuse ==120 ) -return 4 ; -else if (fuse ==138 ) -return 3 ; -else if (fuse ==169 ) -return 2 ; -else if (fuse ==180 ) -return 1 ; - -return UINT_MAX ; -} - -static u32 a640_get_speed_bin (u32 fuse) -{ -if (fuse ==0 ) -return 0 ; -else if (fuse ==1 ) -return 1 ; - -return UINT_MAX ; -} - -static u32 a650_get_speed_bin (u32 fuse) -{ -if (fuse ==0 ) -return 0 ; -else if (fuse ==1 ) -return 1 ; -/* Yep, 2 and 3 are swapped! :/ */ -else if (fuse ==2 ) -return 3 ; -else if (fuse ==3 ) -return 2 ; - -return UINT_MAX ; -} +if (!info->speedbins) +return UINT_MAX ; -static u32 adreno_7c3_get_speed_bin (u32 fuse) -{ -if (fuse ==0 ) -return 0 ; -else if (fuse ==117 ) -return 0 ; -else if (fuse ==190 ) -return 1 ; +for (int i =0 ; info->speedbins[i].fuse !=SHRT_MAX ; i++) +if (info->speedbins[i].fuse == fuse) +return BIT (info->speedbins[i].speedbin);return UINT_MAX ; } -static u32 fuse_to_supp_hw (struct device *dev,struct adreno_gpu *adreno_gpu,u32 fuse) -{ -u32 val =UINT_MAX ; - -if (adreno_is_a610 (adreno_gpu)) - val =a610_get_speed_bin (fuse); - -if (adreno_is_a618 (adreno_gpu)) - val =a618_get_speed_bin (fuse); - -else if (adreno_is_a619_holi (adreno_gpu)) - val =a619_holi_get_speed_bin (fuse); - -else if (adreno_is_a619 (adreno_gpu)) - val =a619_get_speed_bin (fuse); - -else if (adreno_is_7c3 (adreno_gpu)) - val =adreno_7c3_get_speed_bin (fuse); - -else if (adreno_is_a640 (adreno_gpu)) - val =a640_get_speed_bin (fuse); - -else if (adreno_is_a650 (adreno_gpu)) - val =a650_get_speed_bin (fuse); - -if (val ==UINT_MAX ) { -DRM_DEV_ERROR (dev, -"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n" , - fuse); -return UINT_MAX ; - } - -return (1 << val); -} - -static int a6xx_set_supported_hw (struct device *dev,struct adreno_gpu *adreno_gpu) +static int a6xx_set_supported_hw (struct device *dev,const struct adreno_info *info) {u32 supp_hw;u32 speedbin;
@@ -2375,7 +2235,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_greturn ret; } - supp_hw =fuse_to_supp_hw (dev, adreno_gpu, speedbin); + supp_hw =fuse_to_supp_hw (info, speedbin); + +if (supp_hw ==UINT_MAX ) { +DRM_DEV_ERROR (dev, +"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n" , + speedbin); +return UINT_MAX ; + } ret =devm_pm_opp_set_supported_hw (dev, &supp_hw,1 );if (ret)
@@ -2483,17 +2350,11 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)if (!info)return ERR_PTR (-EINVAL ); -/* Assign these early so that we can use the is_aXYZ helpers */ -/* New-style ADRENO_REV()-only */ - adreno_gpu->rev = info->rev; -/* Quirk data */ - adreno_gpu->info = info; - adreno_gpu->base.hw_apriv = !!(info->quirks &ADRENO_QUIRK_HAS_HW_APRIV );a6xx_llc_slices_init (pdev, a6xx_gpu); - ret =a6xx_set_supported_hw (&pdev->dev, adreno_gpu); + ret =a6xx_set_supported_hw (&pdev->dev, info);if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));return ERR_PTR (ret);
drivers/gpu/drm/msm/adreno/adreno_device.c +51 -0
99 lines not on this page · raw message
drivers/gpu/drm/msm/adreno/adreno_gpu.h +30 -0
@@ -60,6 +60,11 @@ struct adreno_reglist {extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; +struct adreno_speedbin { +uint16_t fuse; +uint16_t speedbin; +}; +struct adreno_info {const char *machine;struct adreno_rev rev;
@@ -72,8 +77,33 @@ struct adreno_info {u32 inactive_period;const struct adreno_reglist *hwcg;u64 address_space_size; +/** +* @speedbins: Optional table of fuse to speedbin mappings +* +* Consists of pairs of fuse, index mappings, terminated with +* {SHRT_MAX, 0} sentinal. +*/ +struct adreno_speedbin *speedbins; }; +/* +* Helper to build a speedbin table, ie. the table: +* fuse | speedbin +* -----+--------- +* 0 | 0 +* 169 | 1 +* 174 | 2 +* +* would be declared as: +* +* .speedbins = ADRENO_SPEEDBINS( +* { 0, 0 }, +* { 169, 1 }, +* { 174, 2 }, +* ), +*/ +#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } +const struct adreno_info *adreno_info (struct adreno_rev rev);struct adreno_gpu {
Signature · 1 line
2.41.0
Re: [PATCH v2 07/13] drm/msm/adreno: Move speedbin mapping to device table
Quoted 5 lines · Rob Clark
From: Rob Clark <[email protected]>
This simplifies the code.
Quoted 8 lines
v2: Use a table of structs instead of flat uint32_t[]
Signed-off-by Rob Clark <[email protected]>--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++++ 3 files changed, 97 insertions(+), 155 deletions(-)
Reviewed-by Dmitry Baryshkov <[email protected]>
Signature · 2 lines
With best wishes Dmitry
PATCH v2 8/13 drm/msm/adreno: Bring the a630 family together
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
All of these are derivatives of a630.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>
--- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +1 -1
@@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) SZ_256K - SZ_16K, 0x44000, "dcache");if (ret) goto err_memory; - }else if (adreno_is_a630 (adreno_gpu) ||adreno_is_a615_family (adreno_gpu)) { + }else if (adreno_is_a630_family (adreno_gpu)) {/* HFI v1, has sptprac */ gmu->legacy = true;
drivers/gpu/drm/msm/adreno/adreno_gpu.h +4 -3
@@ -340,10 +340,11 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)/* The order of args is important here to handle ANY_ID correctly */ return adreno_cmp_rev (ADRENO_REV (6 ,9 ,0 ,ANY_ID ), gpu->rev); }; -/* check for a615, a616, a618, a619 or any derivatives */ -static inline int adreno_is_a615_family (const struct adreno_gpu *gpu) +/* check for a615, a616, a618, a619 or any a630 derivatives */ +static inline int adreno_is_a630_family (const struct adreno_gpu *gpu) { -return adreno_is_revn (gpu,615 ) || +return adreno_is_revn (gpu,630 ) || +adreno_is_revn (gpu,615 ) ||adreno_is_revn (gpu,616 ) ||adreno_is_revn (gpu,618 ) ||adreno_is_revn (gpu,619 );
Signature · 1 line
2.41.0
PATCH v2 9/13 drm/msm/adreno: Add adreno family
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id.
v2: Fix is_a2xx() typo
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +30 -1
@@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);static const struct adreno_info gpulist[] = { { .rev =ADRENO_REV (2 ,0 ,0 ,0 ), + .family =ADRENO_2XX_GEN1 , .revn =200 , .fw = { [ADRENO_FW_PM4 ] ="yamato_pm4.fw" ,
@@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), + .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw",
@@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw",
@@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .family = ADRENO_3XX, .revn = 305, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 6, 0), + .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .family = ADRENO_3XX, .revn = 320, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw",
@@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .family = ADRENO_3XX, .revn = 330, .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw",
@@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .family = ADRENO_4XX, .revn = 405, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 420, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 430, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw",
@@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .family = ADRENO_5XX, .revn = 506, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a506_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .family = ADRENO_5XX, .revn = 508, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a508_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .family = ADRENO_5XX, .revn = 509, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 510, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .family = ADRENO_5XX, .revn = 512, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), + .family = ADRENO_5XX, .revn = 530, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a530_zap.mdt", }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 540, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw",
@@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a540_zap.mdt", }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw",
@@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw",
@@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = { .address_space_size = SZ_16G, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin",
@@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw",
@@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a640_hwcg, }, { .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a690_gmu.bin",
@@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)DBG ("Found GPU: %u.%u.%u.%u" , config.rev.core, config.rev.major, config.rev.minor, config.rev.patchid); - priv->is_a2xx = config.rev.core ==2 ; + priv->is_a2xx = info->family <ADRENO_3XX ; priv->has_cached_coherent = !!(info->quirks &ADRENO_QUIRK_HAS_CACHED_COHERENT );
drivers/gpu/drm/msm/adreno/adreno_gpu.c +6 -5
@@ -1080,8 +1080,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,u32 speedbin;int ret; + adreno_gpu->funcs = funcs; + adreno_gpu->info =adreno_info (config->rev); + adreno_gpu->rev = *rev; +/* Only handle the core clock when GMU is not in use (or is absent). */ -if (adreno_has_gmu_wrapper (adreno_gpu) || config->rev.core <6 ) { +if (adreno_has_gmu_wrapper (adreno_gpu) || + adreno_gpu->info->family <ADRENO_6XX_GEN1 ) {/* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON()
@@ -1097,10 +1102,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,devm_pm_opp_set_clkname (dev,"core" ); } - adreno_gpu->funcs = funcs; - adreno_gpu->info =adreno_info (config->rev); - adreno_gpu->rev = *rev; -if (adreno_read_speedbin (dev, &speedbin) || !speedbin) speedbin =0xffff ; adreno_gpu->speedbin = (uint16_t ) (0xffff & speedbin);
drivers/gpu/drm/msm/adreno/adreno_gpu.h +34 -12
89 lines not on this page · raw message
Signature · 1 line
2.41.0
Re: [PATCH v2 09/13] drm/msm/adreno: Add adreno family
Quoted 5 lines · Rob Clark
From: Rob Clark <[email protected]>
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the
Nit: inferring
Quoted 10 lines
numerical chip-id.
v2: Fix
is_a2xx()typoSigned-off-by Rob Clark <[email protected]>--- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-)
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 1 line
[skipped]
Quoted 11 lines
drivers/gpu/drm/msm/adreno/adreno_gpu.h +3
-0@@ -29,6 +29,25 @@ enum { ADRENO_FW_MAX, }; +/** +* @enum adreno_family: identify generation and possibly sub-generation +*
drivers/gpu/drm/msm/adreno/adreno_gpu.h enum { · line 44
Quoted 10 lines
drivers/gpu/drm/msm/adreno/adreno_gpu.h +10
-0+* In some cases there are distinct sub-generations within a major revision +* so it helps to be able to group the GPU devices by generation and if +* necessary sub-generation. +*/ +enum adreno_family { +ADRENO_2XX_GEN1 ,/* a20x */ +ADRENO_2XX_GEN2 ,/* a22x */ +ADRENO_3XX , +ADRENO_4XX , +ADRENO_5XX ,
reserves himself a right to glance at splitting 3xx and 5xx later on.
Quoted 79 lines
drivers/gpu/drm/msm/adreno/adreno_gpu.h +21
-13+ADRENO_6XX_GEN1 ,/* a630 family */ +ADRENO_6XX_GEN2 ,/* a640 family */ +ADRENO_6XX_GEN3 ,/* a650 family */ + ADRENO_6XX_GEN4, /* a660 family */ +}; +#define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)#define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)#define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)@@ -68,6 +87,7 @@ struct adreno_speedbin {struct adreno_info {const char *machine;struct adreno_rev rev; +enum adreno_family family;uint32_t revn;const char *fw[ADRENO_FW_MAX ];uint32_t gmem;@@ -193,14 +213,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) {if (WARN_ON_ONCE (!gpu->info))return false; -return (gpu->info->revn <300 ); +return gpu->info->family <=ADRENO_2XX_GEN2 ; }static inline bool adreno_is_a20x (const struct adreno_gpu *gpu) {if (WARN_ON_ONCE (!gpu->info))return false; -return (gpu->info->revn <210 ); +return gpu->info->family ==ADRENO_2XX_GEN1 ; }static inline bool adreno_is_a225 (const struct adreno_gpu *gpu)@@ -343,29 +363,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)/* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family (const struct adreno_gpu *gpu) { -return adreno_is_revn (gpu,630 ) || -adreno_is_revn (gpu,615 ) || -adreno_is_revn (gpu,616 ) || -adreno_is_revn (gpu,618 ) || -adreno_is_revn (gpu,619 ); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return gpu->info->family ==ADRENO_6XX_GEN1 ; }static inline int adreno_is_a660_family (const struct adreno_gpu *gpu) { -return adreno_is_a660 (gpu) ||adreno_is_a690 (gpu) ||adreno_is_7c3 (gpu); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return gpu->info->family ==ADRENO_6XX_GEN4 ; }/* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family (const struct adreno_gpu *gpu) { -return adreno_is_revn (gpu,650 ) || -adreno_is_revn (gpu,620 ) || -adreno_is_a660_family (gpu); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return gpu->info->family >=ADRENO_6XX_GEN3 ; }static inline int adreno_is_a640_family (const struct adreno_gpu *gpu) { -return adreno_is_a640 (gpu) ||adreno_is_a680 (gpu); +if (WARN_ON_ONCE (!gpu->info)) +return false; +return gpu->info->family ==ADRENO_6XX_GEN2 ; }u64 adreno_private_address_space_size (struct msm_gpu *gpu); --2.41.0
Signature · 2 lines
With best wishes Dmitry
PATCH v2 10/13 drm/msm/adreno: Add helper for formating chip-id
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better.
Signed-off-by Rob Clark <[email protected]>
Reviewed-by Dmitry Baryshkov <[email protected]>
--- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++----------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 3 files changed, 17 insertions(+), 16 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_device.c +3 -5
@@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) info =adreno_info (config.rev);if (!info) { -dev_warn (drm->dev,"Unknown GPU revision: %u.%u.%u.%u\n" , - config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); +dev_warn (drm->dev,"Unknown GPU revision: %" ADRENO_CHIPID_FMT "\n" , +ADRENO_CHIPID_ARGS (config.rev));return -ENXIO ; } -DBG ("Found GPU: %u.%u.%u.%u" , config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); +DBG ("Found GPU: %" ADRENO_CHIPID_FMT ,ADRENO_CHIPID_ARGS (config.rev)); priv->is_a2xx = info->family <ADRENO_3XX ; priv->has_cached_coherent =
drivers/gpu/drm/msm/adreno/adreno_gpu.c +8 -11
@@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,if (IS_ERR_OR_NULL (state))return ; -drm_printf (p,"revision: %d (%d.%d.%d.%d)\n" , - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); +drm_printf (p,"revision: %u (%" ADRENO_CHIPID_FMT ")\n" , + adreno_gpu->info->revn, +ADRENO_CHIPID_ARGS (adreno_gpu->rev));/* * If this is state collected due to iova fault, so fault related info *
@@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu)struct adreno_gpu *adreno_gpu =to_adreno_gpu (gpu);int i; -printk ("revision: %d (%d.%d.%d.%d)\n" , - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); +printk ("revision: %u (%" ADRENO_CHIPID_FMT ")\n" , + adreno_gpu->info->revn, +ADRENO_CHIPID_ARGS (adreno_gpu->rev));for (i =0 ; i < gpu->nr_rings; i++) {struct msm_ringbuffer *ring = gpu->rb[i];
@@ -1106,9 +1104,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin =0xffff ; adreno_gpu->speedbin = (uint16_t ) (0xffff & speedbin); - gpu_name =devm_kasprintf (dev,GFP_KERNEL ,"%d.%d.%d.%d" , - rev->core, rev->major, rev->minor, - rev->patchid); + gpu_name =devm_kasprintf (dev,GFP_KERNEL ,"%" ADRENO_CHIPID_FMT , +ADRENO_CHIPID_ARGS (config->rev));if (!gpu_name)return -ENOMEM ;
drivers/gpu/drm/msm/adreno/adreno_gpu.h +6 -0
@@ -66,6 +66,12 @@ struct adreno_rev {#define ADRENO_REV (core, major, minor, patchid) \ ((struct adreno_rev){ core, major, minor, patchid }) +/* Helper for formating the chip_id in the way that userspace tools like +* crashdec expect. +*/ +#define ADRENO_CHIPID_FMT "u.%u.%u.%u" +#define ADRENO_CHIPID_ARGS (_r) (_r).core, (_r).major, (_r).minor, (_r).patchid +struct adreno_gpu_funcs {struct msm_gpu_funcs base;int (*get_timestamp)(struct msm_gpu *gpu,uint64_t *value);
Signature · 1 line
2.41.0
PATCH v2 11/13 drm/msm/adreno: Move adreno info to config
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Let's just stash it in adreno_platform_config rather than looking it up in N different places.
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++------------ drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- 4 files changed, 8 insertions(+), 17 deletions(-)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c +3 -12
@@ -2316,7 +2316,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)struct msm_drm_private *priv = dev->dev_private;struct platform_device *pdev = priv->gpu_pdev;struct adreno_platform_config *config = pdev->dev.platform_data; -const struct adreno_info *info;struct device_node *node;struct a6xx_gpu *a6xx_gpu;struct adreno_gpu *adreno_gpu;
@@ -2341,20 +2340,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper =of_device_is_compatible (node,"qcom,adreno-gmu-wrapper" ); -/* -* We need to know the platform type before calling into adreno_gpu_init -* so that the hw_apriv flag can be correctly set. Snoop into the info -* and grab the revision number -*/ - info =adreno_info (config->rev); -if (!info) -return ERR_PTR (-EINVAL ); - - adreno_gpu->base.hw_apriv = !!(info->quirks &ADRENO_QUIRK_HAS_HW_APRIV ); + adreno_gpu->base.hw_apriv = + !!(config->info->quirks &ADRENO_QUIRK_HAS_HW_APRIV );a6xx_llc_slices_init (pdev, a6xx_gpu); - ret =a6xx_set_supported_hw (&pdev->dev, info); + ret =a6xx_set_supported_hw (&pdev->dev, config->info);if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));return ERR_PTR (ret);
drivers/gpu/drm/msm/adreno/adreno_device.c +3 -2
@@ -508,7 +508,7 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)_rev_match (rev1.patchid, rev2.patchid); } -const struct adreno_info *adreno_info (struct adreno_rev rev) +static const struct adreno_info *adreno_info (struct adreno_rev rev) {int i;
@@ -659,13 +659,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->gpu_pdev =to_platform_device (dev); info =adreno_info (config.rev); -if (!info) {dev_warn (drm->dev,"Unknown GPU revision: %" ADRENO_CHIPID_FMT "\n" ,ADRENO_CHIPID_ARGS (config.rev));return -ENXIO ; } + config.info = info; +DBG ("Found GPU: %" ADRENO_CHIPID_FMT ,ADRENO_CHIPID_ARGS (config.rev)); priv->is_a2xx = info->family <ADRENO_3XX ;
drivers/gpu/drm/msm/adreno/adreno_gpu.c +1 -1
@@ -1079,7 +1079,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,int ret; adreno_gpu->funcs = funcs; - adreno_gpu->info =adreno_info (config->rev); + adreno_gpu->info = config->info; adreno_gpu->rev = *rev;/* Only handle the core clock when GMU is not in use (or is absent). */
drivers/gpu/drm/msm/adreno/adreno_gpu.h +1 -2
@@ -130,8 +130,6 @@ struct adreno_info {*/ #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } -const struct adreno_info *adreno_info (struct adreno_rev rev); -struct adreno_gpu {struct msm_gpu base;struct adreno_rev rev;
@@ -185,6 +183,7 @@ struct adreno_ocmem {/* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config {struct adreno_rev rev; +const struct adreno_info *info; };#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
Signature · 1 line
2.41.0
Re: [PATCH v2 11/13] drm/msm/adreno: Move adreno info to config
Quoted 5 lines · Rob Clark
From: Rob Clark <[email protected]>
Let's just stash it in
adreno_platform_configrather than looking it up in N different places.
This leaves me with the feeling that we are abusing the dev->platform_data, but we were doing it anyway even before the patch. So:
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 111 lines
Signed-off-by Rob Clark <[email protected]>--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++------------ drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- 4 files changed, 8 insertions(+), 17 deletions(-)drivers/gpu/drm/msm/adreno/a6xx_gpu.c +3
-12@@ -2316,7 +2316,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)struct msm_drm_private *priv = dev->dev_private;struct platform_device *pdev = priv->gpu_pdev;struct adreno_platform_config *config = pdev->dev.platform_data; -const struct adreno_info *info;struct device_node *node;struct a6xx_gpu *a6xx_gpu;struct adreno_gpu *adreno_gpu;@@ -2341,20 +2340,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper =of_device_is_compatible (node,"qcom,adreno-gmu-wrapper" ); -/* -* We need to know the platform type before calling into adreno_gpu_init -* so that the hw_apriv flag can be correctly set. Snoop into the info -* and grab the revision number -*/ - info =adreno_info (config->rev); -if (!info) -return ERR_PTR (-EINVAL ); - - adreno_gpu->base.hw_apriv = !!(info->quirks &ADRENO_QUIRK_HAS_HW_APRIV ); + adreno_gpu->base.hw_apriv = + !!(config->info->quirks &ADRENO_QUIRK_HAS_HW_APRIV );a6xx_llc_slices_init (pdev, a6xx_gpu); - ret =a6xx_set_supported_hw (&pdev->dev, info); + ret =a6xx_set_supported_hw (&pdev->dev, config->info);if (ret) {a6xx_destroy (&(a6xx_gpu->base.base));return ERR_PTR (ret);drivers/gpu/drm/msm/adreno/adreno_device.c +3
-2@@ -508,7 +508,7 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2)_rev_match (rev1.patchid, rev2.patchid); } -const struct adreno_info *adreno_info (struct adreno_rev rev) +static const struct adreno_info *adreno_info (struct adreno_rev rev) {int i;@@ -659,13 +659,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->gpu_pdev =to_platform_device (dev); info =adreno_info (config.rev); -if (!info) {dev_warn (drm->dev,"Unknown GPU revision: %" ADRENO_CHIPID_FMT "\n" ,ADRENO_CHIPID_ARGS (config.rev));return -ENXIO ; } + config.info = info; +DBG ("Found GPU: %" ADRENO_CHIPID_FMT ,ADRENO_CHIPID_ARGS (config.rev)); priv->is_a2xx = info->family <ADRENO_3XX ;drivers/gpu/drm/msm/adreno/adreno_gpu.c +1
-1@@ -1079,7 +1079,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,int ret; adreno_gpu->funcs = funcs; - adreno_gpu->info =adreno_info (config->rev); + adreno_gpu->info = config->info; adreno_gpu->rev = *rev;/* Only handle the core clock when GMU is not in use (or is absent). */ drivers/gpu/drm/msm/adreno/adreno_gpu.h +1
-3@@ -130,8 +130,6 @@ struct adreno_info {*/ #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } -const struct adreno_info *adreno_info (struct adreno_rev rev); -struct adreno_gpu {struct msm_gpu base;struct adreno_rev rev;@@ -185,6 +183,7 @@ struct adreno_ocmem {/* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config {struct adreno_rev rev; +const struct adreno_info *info; };#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) --2.41.0
Signature · 2 lines
With best wishes Dmitry
PATCH v2 12/13 dt-bindings: drm/msm/gpu: Extend bindings for chip-id
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Upcoming GPUs use an opaque chip-id for identifying the GPU.
Signed-off-by Rob Clark <[email protected]>
--- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/display/msm/gpu.yaml +6 -0
@@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + - const: qcom,adreno - description: | The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level.
Signature · 1 line
2.41.0
Re: [PATCH v2 12/13] dt-bindings: drm/msm/gpu: Extend bindings for chip-id
Quoted 3 lines · Rob Clark
From: Rob Clark <[email protected]>
Upcoming GPUs use an opaque chip-id for identifying the GPU.
Examples?
Anyway, I think we should insist here of using something human-readable, even if Qualcomm/Adreno internally use some weird numbers.
Quoted 11 lines
Signed-off-by Rob Clark <[email protected]>--- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+)Documentation/devicetree/bindings/display/msm/gpu.yaml +0
-0
Documentation/devicetree/bindings/display/msm/gpu.yaml maintainers: · line 20
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/gpu.yaml +5
-0@@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
{8} should work?
Best regards,
Krzysztof
Re: [PATCH v2 12/13] dt-bindings: drm/msm/gpu: Extend bindings for chip-id
Quoted 7 lines · Krzysztof Kozlowski
Quoted 3 lines · Rob Clark
From: Rob Clark <[email protected]>
Upcoming GPUs use an opaque chip-id for identifying the GPU.
Examples?
We'll know when we bring up the hw. But the main point is that we shouldn't expect, for example, the high 8 bits to tell us the generation, any more than we could if it was a pci id.
We may not end up needing to use this new binding much, I _think_ we should be able to read it from the fw in most cases, at least for android devices. I'm unsure at this point about windows/chromebooks.
Quoted 2 lines
Anyway, I think we should insist here of using something human-readable, even if Qualcomm/Adreno internally use some weird numbers.
I mean qcom,sc8280cx-adreno is human readable but not really very informative. Encoding the chip-id is just a way to avoid the qcom,chipid field in the bindings, which qcom used downstream. The new pattern accomplishes the same thing as the existing one, but without trying to imply some meaning that becomes increasingly non-existent as qc moves to decouple the id from marketing names.
Quoted 6 lines
Quoted 6 lines
Signed-off-by Rob Clark <[email protected]>--- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
Quoted 16 lines
Documentation/devicetree/bindings/display/msm/gpu.yaml maintainers: · line 20
Quoted 13 lines
Documentation/devicetree/bindings/display/msm/gpu.yaml +5
-0@@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'{8} should work?
so '^qcom,adreno-[0-9a-f]{8}$'
BR,
-R
Quoted 5 lines
Best regards,
Krzysztof
PATCH v2 13/13 drm/msm/adreno: Switch to chip-id for identifying GPU
In reply to Rob ClarkFrom: Rob Clark <[email protected]>
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table.
Signed-off-by Rob Clark <[email protected]>
--- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++- drivers/gpu/drm/msm/adreno/adreno_device.c | 137 +++++++++++---------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 49 ++++---- 7 files changed, 115 insertions(+), 105 deletions(-)
drivers/gpu/drm/msm/adreno/a4xx_gpu.c +1 -1
@@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)gpu_write (gpu,REG_A4XX_RBBM_CLOCK_DELAY_HLSQ ,0x00220000 );/* Early A430's have a timing issue with SP/TP power collapse; disabling HW clock gating prevents it. */ -if (adreno_is_a430 (adreno_gpu) && adreno_gpu->rev.patchid <2 ) +if (adreno_is_a430 (adreno_gpu) &&adreno_patchid (adreno_gpu) <2 )gpu_write (gpu,REG_A4XX_RBBM_CLOCK_CTL ,0 );else gpu_write (gpu,REG_A4XX_RBBM_CLOCK_CTL ,0xAAAAAAAA );
drivers/gpu/drm/msm/adreno/a5xx_gpu.c +1 -1
@@ -1770,7 +1770,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) nr_rings =4 ; -if (adreno_cmp_rev (ADRENO_REV (5 ,1 ,0 ,ANY_ID ), config->rev)) +if (config->info->revn ==510 ) nr_rings =1 ; ret =adreno_gpu_init (dev, pdev, adreno_gpu, &funcs, nr_rings);
drivers/gpu/drm/msm/adreno/a5xx_power.c +1 -1
@@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu)/* The battery current limiter isn't enabled for A540 */ config =AGC_LM_CONFIG_BCL_DISABLED ; - config |= adreno_gpu->rev.patchid <<AGC_LM_CONFIG_GPU_VERSION_SHIFT ; + config |=adreno_patchid (adreno_gpu) <<AGC_LM_CONFIG_GPU_VERSION_SHIFT ;/* For now disable GPMU side throttling */ config |=AGC_LM_CONFIG_THROTTLE_DISABLE ;
drivers/gpu/drm/msm/adreno/a6xx_gmu.c +10 -4
@@ -790,10 +790,16 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)gmu_write (gmu,REG_A6XX_GMU_AHB_FENCE_RANGE_0 , (1 <<31 ) | (0xa <<18 ) | (0xa0 )); - chipid = adreno_gpu->rev.core <<24 ; - chipid |= adreno_gpu->rev.major <<16 ; - chipid |= adreno_gpu->rev.minor <<12 ; - chipid |= adreno_gpu->rev.patchid <<8 ; +/* +* Note that the GMU has a slightly different layout for +* chip_id, for whatever reason, so a bit of massaging +* is needed. The upper 16b are the same, but minor and +* patchid are packed in four bits each with the lower +* 8b unused: +*/ + chipid = adreno_gpu->chip_id &0xffff0000 ; + chipid |= (adreno_gpu->chip_id <<4 ) &0xf000 ;/* minor */ + chipid |= (adreno_gpu->chip_id <<8 ) &0x0f00 ;/* patchid */ gmu_write (gmu,REG_A6XX_GMU_HFI_SFR_ADDR , chipid);
drivers/gpu/drm/msm/adreno/adreno_device.c +70 -67
371 lines not on this page · raw message
drivers/gpu/drm/msm/adreno/adreno_gpu.c +5 -9
@@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = !adreno_is_a650_family (adreno_gpu) ?0x100000 :0 ;return 0 ;case MSM_PARAM_CHIP_ID : - *value = (uint64_t )adreno_gpu->rev.patchid | - ((uint64_t )adreno_gpu->rev.minor <<8 ) | - ((uint64_t )adreno_gpu->rev.major <<16 ) | - ((uint64_t )adreno_gpu->rev.core <<24 ); + *value = adreno_gpu->chip_id;if (!adreno_gpu->info->revn) *value |= ((uint64_t ) adreno_gpu->speedbin) <<32 ;return 0 ;
@@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,drm_printf (p,"revision: %u (%" ADRENO_CHIPID_FMT ")\n" , adreno_gpu->info->revn, -ADRENO_CHIPID_ARGS (adreno_gpu->rev)); +ADRENO_CHIPID_ARGS (adreno_gpu->chip_id));/* * If this is state collected due to iova fault, so fault related info *
@@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu)printk ("revision: %u (%" ADRENO_CHIPID_FMT ")\n" , adreno_gpu->info->revn, -ADRENO_CHIPID_ARGS (adreno_gpu->rev)); +ADRENO_CHIPID_ARGS (adreno_gpu->chip_id));for (i =0 ; i < gpu->nr_rings; i++) {struct msm_ringbuffer *ring = gpu->rb[i];
@@ -1073,14 +1070,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,struct adreno_platform_config *config = dev->platform_data;struct msm_gpu_config adreno_gpu_config = {0 };struct msm_gpu *gpu = &adreno_gpu->base; -struct adreno_rev *rev = &config->rev;const char *gpu_name;u32 speedbin;int ret; adreno_gpu->funcs = funcs; adreno_gpu->info = config->info; - adreno_gpu->rev = *rev; + adreno_gpu->chip_id = config->chip_id;/* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) ||
@@ -1105,7 +1101,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->speedbin = (uint16_t ) (0xffff & speedbin); gpu_name =devm_kasprintf (dev,GFP_KERNEL ,"%" ADRENO_CHIPID_FMT , -ADRENO_CHIPID_ARGS (config->rev)); +ADRENO_CHIPID_ARGS (config->chip_id));if (!gpu_name)return -ENOMEM ;
drivers/gpu/drm/msm/adreno/adreno_gpu.h +27 -22
108 lines not on this page · raw message
Signature · 1 line
2.41.0
Re: [PATCH v2 13/13] drm/msm/adreno: Switch to chip-id for identifying GPU
Quoted 9 lines · Rob Clark
From: Rob Clark <[email protected]>
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table.
Signed-off-by Rob Clark <[email protected]>
Quoted 9 lines
--- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++- drivers/gpu/drm/msm/adreno/adreno_device.c | 137 +++++++++++---------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 49 ++++---- 7 files changed, 115 insertions(+), 105 deletions(-)
Reviewed-by Dmitry Baryshkov <[email protected]>
Signature · 2 lines
With best wishes Dmitry