FAILED: patch "[PATCH] drm/i915/gt: Poll aux invalidation register bit on" failed to apply to 5.10-stable tree

The patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.10.y
git checkout FETCH_HEAD
git cherry-pick -x 0fde2f23516a00fd90dfb980b66b4665fcbfa659
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023080729-dandy-target-2826@gregkh' --subject-prefix 'PATCH 5.10.y' HEAD^..

Possible dependencies:

0fde2f23516a ("drm/i915/gt: Poll aux invalidation register bit on invalidation") b2f59e902603 ("drm/i915: Add the gen12_needs_ccs_aux_inv helper") 29063c6a6a57 ("drm/i915/mtl: Add gsi_offset when emitting aux table invalidation") d8b932014c4a ("drm/i915: avoid concurrent writes to aux_inv") 6639fabb1685 ("drm/i915/xehp: Drop aux table invalidation on FlatCCS platforms") ff6b19d3a0f9 ("drm/i915/xehp: Add compute workarounds")
803efd297e31 ("drm/i915/xehp: compute engine pipe_control") 0d53879faada ("drm/i915/gt: Order GT registers by MMIO offset") bd3de31950ae ("drm/i915/gt: Use consistent offset notation in intel_gt_regs.h") 680a5cd10b9c ("drm/i915/gt: Cleanup spacing of intel_gt_regs.h") ab9e00a3509a ("drm/i915/gt: Use parameterized RING_MI_MODE") 93cc7aa0b037 ("drm/i915/gt: Move SFC lock bits to intel_engine_regs.h") 4895b90dd510 ("drm/i915/gt: Drop duplicate register definition for VDBOX_CGCTL3F18") 22ba60f617bd ("drm/i915: Move [more] GT registers to their own header file") 0d6419e9c855 ("drm/i915: Move GT registers to their own header file") e71a74122863 ("drm/i915: Parameterize MI_PREDICATE registers") 7d296f369d38 ("drm/i915: Parameterize R_PWR_CLK_STATE register definition") 2ef6d3bf4262 ("drm/i915/perf: Move OA regs to their own header") 063565aca373 ("Merge drm/drm-next into drm-intel-next")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 0fde2f23516a00fd90dfb980b66b4665fcbfa659 Mon Sep 17 00:00:00 2001
From: Jonathan Cavitt <[email protected]>
Date: Tue, 25 Jul 2023 02:19:49 +0200
Subject: [PATCH] drm/i915/gt: Poll aux invalidation register bit on
invalidation

For platforms that use Aux CCS, wait for aux invalidation to complete by checking the aux invalidation register bit is cleared.

index ec54d36eaef7..ec7a0ddf9e12 100644
@@ -184,7 +184,15 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 	*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
 	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
 	*cs++ = AUX_INV;
-	*cs++ = MI_NOOP;
+
+	*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
+		MI_SEMAPHORE_REGISTER_POLL |
+		MI_SEMAPHORE_POLL |
+		MI_SEMAPHORE_SAD_EQ_SDD;
+	*cs++ = 0;
+	*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
+	*cs++ = 0;
+	*cs++ = 0;
 
 	return cs;
 }

@@ -292,10 +300,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		else if (engine->class == COMPUTE_CLASS)
 			flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
+		count = 8;
 		if (gen12_needs_ccs_aux_inv(rq->engine))
-			count = 8 + 4;
-		else
-			count = 8;
+			count += 8;
 
 		cs = intel_ring_begin(rq, count);
 		if (IS_ERR(cs))

@@ -338,7 +345,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
 			aux_inv = rq->engine->mask &
 				~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
 			if (aux_inv)
-				cmd += 4;
+				cmd += 8;
 		}
 	}
 

index 5df7cce23197..2bd8d98d2110 100644
@@ -121,6 +121,7 @@
 #define   MI_SEMAPHORE_TARGET(engine)	((engine)<<15)
 #define MI_SEMAPHORE_WAIT	MI_INSTR(0x1c, 2) /* GEN8+ */
 #define MI_SEMAPHORE_WAIT_TOKEN	MI_INSTR(0x1c, 3) /* GEN12+ */
+#define   MI_SEMAPHORE_REGISTER_POLL	(1 << 16)
 #define   MI_SEMAPHORE_POLL		(1 << 15)
 #define   MI_SEMAPHORE_SAD_GT_SDD	(0 << 12)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1 << 12)