Linux 6.4.9
Greg Kroah-Hartman
maintainer-----------------
Note, PLEASE TEST this kernel if you are on the 6.4.y tree before using it in a real workload. This was a quick release due to the obvious security fixes in it, and as such, it has not had very much testing "in the wild". Please let us know of any problems seen. Also note that the user/kernel api for the new security mitigations might be changing over time, so do not get used to them being fixed in stone just yet.
-----------------
I'm announcing the release of the 6.4.9 kernel.
All users of the 6.4 kernel series must upgrade.
The updated 6.4.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linux-6.4.y
and can be browsed at the normal kernel.org git web browser:
https://git.kernel.org/?p=linux/kernel/git/stable/linux-stable.git;a=summary
thanks,
greg k-h
------------
Documentation/ABI/testing/sysfs-devices-system-cpu | 13 Documentation/admin-guide/hw-vuln/gather_data_sampling.rst | 109 +++ Documentation/admin-guide/hw-vuln/index.rst | 1 Documentation/admin-guide/hw-vuln/srso.rst | 133 ++++ Documentation/admin-guide/kernel-parameters.txt | 58 + Makefile | 2 arch/Kconfig | 3 arch/alpha/include/asm/bugs.h | 20 arch/arm/Kconfig | 1 arch/arm/include/asm/bugs.h | 4 arch/arm/kernel/bugs.c | 3 arch/ia64/Kconfig | 1 arch/ia64/include/asm/bugs.h | 20 arch/ia64/kernel/setup.c | 3 arch/loongarch/Kconfig | 1 arch/loongarch/include/asm/bugs.h | 15 arch/loongarch/kernel/setup.c | 4 arch/m68k/Kconfig | 1 arch/m68k/include/asm/bugs.h | 21 arch/m68k/kernel/setup_mm.c | 3 arch/mips/Kconfig | 1 arch/mips/include/asm/bugs.h | 17 arch/mips/kernel/setup.c | 13 arch/parisc/include/asm/bugs.h | 20 arch/powerpc/include/asm/bugs.h | 15 arch/sh/Kconfig | 1 arch/sh/include/asm/bugs.h | 74 -- arch/sh/include/asm/processor.h | 2 arch/sh/kernel/idle.c | 1 arch/sh/kernel/setup.c | 55 + arch/sparc/Kconfig | 1 arch/sparc/include/asm/bugs.h | 18 arch/sparc/kernel/setup_32.c | 7 arch/um/Kconfig | 1 arch/um/include/asm/bugs.h | 7 arch/um/kernel/um_arch.c | 3 arch/x86/Kconfig | 27 arch/x86/include/asm/bugs.h | 2 arch/x86/include/asm/cpufeatures.h | 13 arch/x86/include/asm/fpu/api.h | 2 arch/x86/include/asm/mem_encrypt.h | 9 arch/x86/include/asm/msr-index.h | 12 arch/x86/include/asm/nospec-branch.h | 23 arch/x86/include/asm/processor.h | 2 arch/x86/include/asm/sigframe.h | 2 arch/x86/kernel/cpu/amd.c | 19 arch/x86/kernel/cpu/bugs.c | 388 +++++++++++-- arch/x86/kernel/cpu/common.c | 123 +++- arch/x86/kernel/cpu/cpu.h | 2 arch/x86/kernel/fpu/init.c | 8 arch/x86/kernel/signal.c | 4 arch/x86/kernel/vmlinux.lds.S | 31 + arch/x86/kvm/cpuid.c | 3 arch/x86/kvm/svm/svm.c | 4 arch/x86/kvm/svm/vmenter.S | 3 arch/x86/kvm/x86.c | 7 arch/x86/lib/retpoline.S | 83 ++ arch/x86/xen/smp_pv.c | 1 arch/xtensa/include/asm/bugs.h | 18 drivers/base/cpu.c | 16 drivers/net/xen-netback/netback.c | 15 include/asm-generic/bugs.h | 11 include/linux/cpu.h | 8 init/main.c | 16 tools/arch/x86/include/asm/cpufeatures.h | 2 tools/objtool/arch/x86/decode.c | 5 66 files changed, 1109 insertions(+), 402 deletions(-)
Borislav Petkov (AMD) (8):
x86/bugs: Increase the x86 bugs vector size to two u32s x86/srso: Add a Speculative RAS Overflow mitigation x86/srso: Add IBPB_BRTYPE support
x86/srso: Add SRSO_NO support
x86/srso: Add IBPB
x86/srso: Add IBPB on VMEXIT
x86/srso: Add a forgotten NOENDBR annotation x86/srso: Tie SBPB bit setting to microcode patch detection
Daniel Sneddon (4):
x86/speculation: Add Gather Data Sampling mitigation x86/speculation: Add force option to GDS mitigation x86/speculation: Add Kconfig option for GDS
KVM: Add GDS_NO support to KVM
Dave Hansen (1):
Documentation/x86: Fix backwards on/off logic about YMM support
Greg Kroah-Hartman (2):
x86: fix backwards merge of GDS/SRSO bit
Linux 6.4.9
Josh Poimboeuf (1):
x86/srso: Fix return thunks in generated code
Juergen Gross (1):
x86/xen: Fix secondary processors' FPU initialization
Ross Lagerwall (1):
xen/netback: Fix buffer overrun triggered by unusual packet
Thomas Gleixner (18):
init: Provide arch_cpu_finalize_init()
x86/cpu: Switch to arch_cpu_finalize_init()
ARM: cpu: Switch to arch_cpu_finalize_init() ia64/cpu: Switch to arch_cpu_finalize_init() loongarch/cpu: Switch to arch_cpu_finalize_init() m68k/cpu: Switch to arch_cpu_finalize_init() mips/cpu: Switch to arch_cpu_finalize_init()
sh/cpu: Switch to arch_cpu_finalize_init()
sparc/cpu: Switch to arch_cpu_finalize_init()
um/cpu: Switch to arch_cpu_finalize_init()
init: Remove check_bugs() leftovers
init: Invoke arch_cpu_finalize_init() earlier
init, x86: Move mem_encrypt_init() into arch_cpu_finalize_init() x86/init: Initialize signal frame size late
x86/fpu: Remove cpuinfo argument from init functions x86/fpu: Mark init functions __init
x86/fpu: Move FPU initialization into arch_cpu_finalize_init() x86/mem_encrypt: Unbreak the AMD_MEM_ENCRYPT=n build
Greg Kroah-Hartman
maintainerDocumentation/ABI/testing/sysfs-devices-system-cpu +7 -6
@@ -513,17 +513,18 @@ Description: information about CPUs heterogeneity. cpu_capacity: capacity of cpuX. What: /sys/devices/system/cpu/vulnerabilities + /sys/devices/system/cpu/vulnerabilities/gather_data_sampling + /sys/devices/system/cpu/vulnerabilities/itlb_multihit + /sys/devices/system/cpu/vulnerabilities/l1tf + /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/meltdown + /sys/devices/system/cpu/vulnerabilities/mmio_stale_data + /sys/devices/system/cpu/vulnerabilities/retbleed + /sys/devices/system/cpu/vulnerabilities/spec_store_bypass /sys/devices/system/cpu/vulnerabilities/spectre_v1 /sys/devices/system/cpu/vulnerabilities/spectre_v2 - /sys/devices/system/cpu/vulnerabilities/spec_store_bypass - /sys/devices/system/cpu/vulnerabilities/l1tf - /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/tsx_async_abort - /sys/devices/system/cpu/vulnerabilities/itlb_multihit - /sys/devices/system/cpu/vulnerabilities/mmio_stale_data - /sys/devices/system/cpu/vulnerabilities/retbleed Date: January 2018 Contact: Linux kernel mailing list <[email protected]> Description: Information about CPU vulnerabilities
Documentation/admin-guide/hw-vuln/gather_data_sampling.rst new file +109 -0
109 lines not on this page · raw message
Documentation/admin-guide/hw-vuln/index.rst +1 -0
@@ -19,3 +19,4 @@ are configurable at compile, boot or run time. l1d_flush.rst processor_mmio_stale_data.rst cross-thread-rsb.rst + gather_data_sampling.rst
Documentation/admin-guide/hw-vuln/srso.rst new file +133 -0
133 lines not on this page · raw message
Documentation/admin-guide/kernel-parameters.txt +45 -13
81 lines not on this page · raw message
Makefile +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 6 PATCHLEVEL = 4 -SUBLEVEL = 8 +SUBLEVEL = 9 EXTRAVERSION = NAME = Hurr durr I'ma ninja sloth
arch/Kconfig +3 -0
@@ -285,6 +285,9 @@ config ARCH_HAS_DMA_SET_UNCACHED config ARCH_HAS_DMA_CLEAR_UNCACHED bool +config ARCH_HAS_CPU_FINALIZE_INIT + bool + # Select if arch init_task must go in the __init_task_data section config ARCH_TASK_STRUCT_ON_STACK bool
arch/alpha/include/asm/bugs.h deleted +0 -20
@@ -1,20 +0,0 @@ -/* -* include/asm-alpha/bugs.h -* -* Copyright (C) 1994 Linus Torvalds -*/ - -/* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Needs: -* void check_bugs(void); -*/ - -/* -* I don't know of any alpha bugs yet.. Nice chip -*/ - -static void check_bugs (void ) -{ -}
arch/arm/Kconfig +1 -0
@@ -5,6 +5,7 @@ config ARM select ARCH_32BIT_OFF_T select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
arch/arm/include/asm/bugs.h +0 -4
@@ -1,7 +1,5 @@/* SPDX-License-Identifier: GPL-2.0-only */ /* -* arch/arm/include/asm/bugs.h -* * Copyright (C) 1995-2003 Russell King */ #ifndef __ASM_BUGS_H
@@ -10,10 +8,8 @@extern void check_writebuffer_bugs (void );#ifdef CONFIG_MMU -extern void check_bugs (void );extern void check_other_bugs (void );#else -#define check_bugs () do { } while (0)#define check_other_bugs () do { } while (0)#endif
arch/arm/kernel/bugs.c +2 -1
@@ -1,5 +1,6 @@// SPDX-License-Identifier: GPL-2.0 #include <linux/init.h> +#include <linux/cpu.h> #include <asm/bugs.h> #include <asm/proc-fns.h>
@@ -11,7 +12,7 @@ void check_other_bugs(void)#endif } -void __init check_bugs (void ) +void __init arch_cpu_finalize_init (void ) {check_writebuffer_bugs ();check_other_bugs ();
arch/ia64/Kconfig +1 -0
@@ -9,6 +9,7 @@ menu "Processor type and features" config IA64 bool select ARCH_BINFMT_ELF_EXTRA_PHDRS + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_DMA_MARK_CLEAN select ARCH_HAS_STRNCPY_FROM_USER select ARCH_HAS_STRNLEN_USER
arch/ia64/include/asm/bugs.h deleted +0 -20
@@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Needs: -* void check_bugs(void); -* -* Based on <asm-alpha/bugs.h>. -* -* Modified 1998, 1999, 2003 -* David Mosberger-Tang <[email protected]>, Hewlett-Packard Co. -*/ -#ifndef _ASM_IA64_BUGS_H -#define _ASM_IA64_BUGS_H - -#include <asm/processor.h> - -extern void check_bugs (void ); - -#endif /* _ASM_IA64_BUGS_H */
arch/ia64/kernel/setup.c +1 -2
@@ -1067,8 +1067,7 @@ cpu_init (void) } } -void __init -check_bugs (void ) +void __init arch_cpu_finalize_init (void ) {ia64_patch_mckinley_e9 ((unsigned long ) __start___mckinley_e9_bundles, (unsigned long ) __end___mckinley_e9_bundles);
arch/loongarch/Kconfig +1 -0
@@ -10,6 +10,7 @@ config LOONGARCH select ARCH_ENABLE_MEMORY_HOTPLUG select ARCH_ENABLE_MEMORY_HOTREMOVE select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
arch/loongarch/include/asm/bugs.h deleted +0 -15
@@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Copyright (C) 2020-2022 Loongson Technology Corporation Limited -*/ -#ifndef _ASM_BUGS_H -#define _ASM_BUGS_H - -#include <asm/cpu.h> -#include <asm/cpu-info.h> - -extern void check_bugs (void ); - -#endif /* _ASM_BUGS_H */
arch/loongarch/kernel/setup.c +2 -2
@@ -12,6 +12,7 @@*/ #include <linux/init.h> #include <linux/acpi.h> +#include <linux/cpu.h> #include <linux/dmi.h> #include <linux/efi.h> #include <linux/export.h>
@@ -37,7 +38,6 @@#include <asm/addrspace.h> #include <asm/alternative.h> #include <asm/bootinfo.h> -#include <asm/bugs.h> #include <asm/cache.h> #include <asm/cpu.h> #include <asm/dma.h>
@@ -87,7 +87,7 @@ const char *get_system_type(void)return "generic-loongson-machine" ; } -void __init check_bugs (void ) +void __init arch_cpu_finalize_init (void ) {alternative_instructions (); }
arch/m68k/Kconfig +1 -0
@@ -4,6 +4,7 @@ config M68K default y select ARCH_32BIT_OFF_T select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DMA_PREP_COHERENT if HAS_DMA && MMU && !COLDFIRE select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA
arch/m68k/include/asm/bugs.h deleted +0 -21
@@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* -* include/asm-m68k/bugs.h -* -* Copyright (C) 1994 Linus Torvalds -*/ - -/* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Needs: -* void check_bugs(void); -*/ - -#ifdef CONFIG_MMU -extern void check_bugs (void );/* in arch/m68k/kernel/setup.c */ -#else -static void check_bugs (void ) -{ -} -#endif
arch/m68k/kernel/setup_mm.c +2 -1
@@ -10,6 +10,7 @@*/ #include <linux/kernel.h> +#include <linux/cpu.h> #include <linux/mm.h> #include <linux/sched.h> #include <linux/delay.h>
@@ -504,7 +505,7 @@ static int __init proc_hardware_init(void)module_init (proc_hardware_init);#endif -void check_bugs (void ) +void __init arch_cpu_finalize_init (void ) {#if defined(CONFIG_FPU ) && !defined(CONFIG_M68KFPU_EMU )if (m68k_fputype ==0 ) {
arch/mips/Kconfig +1 -0
@@ -4,6 +4,7 @@ config MIPS default y select ARCH_32BIT_OFF_T if !64BIT select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000 select ARCH_HAS_DEBUG_VIRTUAL if !64BIT select ARCH_HAS_FORTIFY_SOURCE
arch/mips/include/asm/bugs.h +0 -17
@@ -1,17 +1,11 @@/* SPDX-License-Identifier: GPL-2.0 */ /* -* This is included by init/main.c to check for architecture-dependent bugs. -* * Copyright (C) 2007 Maciej W. Rozycki -* -* Needs: -* void check_bugs(void); */ #ifndef _ASM_BUGS_H#define _ASM_BUGS_H#include <linux/bug.h> -#include <linux/delay.h> #include <linux/smp.h> #include <asm/cpu.h>
@@ -24,17 +18,6 @@ extern void check_bugs64_early(void);extern void check_bugs32 (void );extern void check_bugs64 (void ); -static inline void __init check_bugs (void ) -{ -unsigned int cpu =smp_processor_id (); - - cpu_data[cpu].udelay_val = loops_per_jiffy; -check_bugs32 (); - -if (IS_ENABLED (CONFIG_CPU_R4X00_BUGS64 )) -check_bugs64 (); -} -static inline int r4k_daddiu_bug (void ) {if (!IS_ENABLED (CONFIG_CPU_R4X00_BUGS64 ))
arch/mips/kernel/setup.c +13 -0
@@ -11,6 +11,8 @@* Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki */ #include <linux/init.h> +#include <linux/cpu.h> +#include <linux/delay.h> #include <linux/ioport.h> #include <linux/export.h> #include <linux/screen_info.h>
@@ -841,3 +843,14 @@ static int __init setnocoherentio(char *str) }early_param ("nocoherentio" , setnocoherentio);#endif + +void __init arch_cpu_finalize_init (void ) +{ +unsigned int cpu =smp_processor_id (); + + cpu_data[cpu].udelay_val = loops_per_jiffy; +check_bugs32 (); + +if (IS_ENABLED (CONFIG_CPU_R4X00_BUGS64 )) +check_bugs64 (); +}
arch/parisc/include/asm/bugs.h deleted +0 -20
@@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* -* include/asm-parisc/bugs.h -* -* Copyright (C) 1999 Mike Shaver -*/ - -/* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Needs: -* void check_bugs(void); -*/ - -#include <asm/processor.h> - -static inline void check_bugs (void ) -{ -// identify_cpu(&boot_cpu_data); -}
arch/powerpc/include/asm/bugs.h deleted +0 -15
@@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef _ASM_POWERPC_BUGS_H -#define _ASM_POWERPC_BUGS_H - -/* -*/ - -/* -* This file is included by 'init/main.c' to check for -* architecture-dependent bugs. -*/ - -static inline void check_bugs (void ) { } - -#endif /* _ASM_POWERPC_BUGS_H */
arch/sh/Kconfig +1 -0
@@ -6,6 +6,7 @@ config SUPERH select ARCH_ENABLE_MEMORY_HOTREMOVE if SPARSEMEM && MMU select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) select ARCH_HAS_BINFMT_FLAT if !MMU + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_GCOV_PROFILE_ALL
arch/sh/include/asm/bugs.h deleted +0 -74
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arch/sh/include/asm/processor.h +2 -0
@@ -166,6 +166,8 @@ extern unsigned int instruction_size(unsigned int insn);#define instruction_size (insn) (2)#endif +void select_idle_routine (void ); +#endif /* __ASSEMBLY__ */ #include <asm/processor_32.h>
arch/sh/kernel/idle.c +1 -0
@@ -15,6 +15,7 @@#include <linux/irqflags.h> #include <linux/smp.h> #include <linux/atomic.h> +#include <asm/processor.h> #include <asm/smp.h> #include <asm/bl_bit.h>
arch/sh/kernel/setup.c +55 -0
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arch/sparc/Kconfig +1 -0
@@ -52,6 +52,7 @@ config SPARC config SPARC32 def_bool !64BIT select ARCH_32BIT_OFF_T + select ARCH_HAS_CPU_FINALIZE_INIT if !SMP select ARCH_HAS_SYNC_DMA_FOR_CPU select CLZ_TAB select DMA_DIRECT_REMAP
arch/sparc/include/asm/bugs.h deleted +0 -18
@@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* include/asm/bugs.h: Sparc probes for various bugs. -* -* Copyright (C) 1996, 2007 David S. Miller ([email protected]) -*/ - -#ifdef CONFIG_SPARC32 -#include <asm/cpudata.h> -#endif - -extern unsigned long loops_per_jiffy; - -static void __init check_bugs (void ) -{ -#if defined(CONFIG_SPARC32 ) && !defined(CONFIG_SMP ) -cpu_data (0 ).udelay_val = loops_per_jiffy; -#endif -}
arch/sparc/kernel/setup_32.c +7 -0
@@ -412,3 +412,10 @@ static int __init topology_init(void) }subsys_initcall (topology_init); + +#if defined(CONFIG_SPARC32 ) && !defined(CONFIG_SMP ) +void __init arch_cpu_finalize_init (void ) +{ +cpu_data (0 ).udelay_val = loops_per_jiffy; +} +#endif
arch/um/Kconfig +1 -0
@@ -6,6 +6,7 @@ config UML bool default y select ARCH_EPHEMERAL_INODES + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_FORTIFY_SOURCE select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_HAS_KCOV
arch/um/include/asm/bugs.h deleted +0 -7
@@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __UM_BUGS_H -#define __UM_BUGS_H - -void check_bugs (void ); - -#endif
arch/um/kernel/um_arch.c +2 -1
@@ -3,6 +3,7 @@* Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com) */ +#include <linux/cpu.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/mm.h>
@@ -430,7 +431,7 @@ void __init setup_arch(char **cmdline_p) } } -void __init check_bugs (void ) +void __init arch_cpu_finalize_init (void ) {arch_check_bugs ();os_check_bugs ();
arch/x86/Kconfig +27 -0
@@ -71,6 +71,7 @@ config X86 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI select ARCH_HAS_CACHE_LINE_SIZE select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEBUG_VM_PGTABLE if !X86_PAE
@@ -2640,6 +2641,13 @@ config CPU_IBRS_ENTRY This mitigates both spectre_v2 and retbleed at great cost to performance. +config CPU_SRSO + bool "Mitigate speculative RAS overflow on AMD" + depends on CPU_SUP_AMD && X86_64 && RETHUNK + default y + help + Enable the SRSO mitigation needed on AMD Zen1-4 machines. + config SLS bool "Mitigate Straight-Line-Speculation" depends on CC_HAS_SLS && X86_64
@@ -2650,6 +2658,25 @@ config SLS against straight line speculation. The kernel image might be slightly larger. +config GDS_FORCE_MITIGATION + bool "Force GDS Mitigation" + depends on CPU_SUP_INTEL + default n + help + Gather Data Sampling (GDS) is a hardware vulnerability which allows + unprivileged speculative access to data which was previously stored in + vector registers. + + This option is equivalent to setting gather_data_sampling=force on the + command line. The microcode mitigation is used if present, otherwise + AVX is disabled as a mitigation. On affected systems that are missing + the microcode any userspace code that unconditionally uses AVX will + break with this option set. + + Setting this option on systems not vulnerable to GDS has no effect. + + If in doubt, say N. + endif config ARCH_HAS_ADD_PAGES
arch/x86/include/asm/bugs.h +0 -2
@@ -4,8 +4,6 @@#include <asm/processor.h> -extern void check_bugs (void ); -#if defined(CONFIG_CPU_SUP_INTEL ) && defined(CONFIG_X86_32 )int ppro_with_ram_bug (void );#else
arch/x86/include/asm/cpufeatures.h +12 -1
@@ -14,7 +14,7 @@* Defines x86 CPU feature bits */ #define NCAPINTS 21/* N 32-bit words worth of info */ -#define NBUGINTS 1/* N 32-bit bug flags */ +#define NBUGINTS 2/* N 32-bit bug flags */ /* * Note: If the comment begins with a quoted string, that string is used
@@ -309,6 +309,10 @@#define X86_FEATURE_SMBA (11*32+21)/* "" Slow Memory Bandwidth Allocation */ #define X86_FEATURE_BMEC (11*32+22)/* "" Bandwidth Monitoring Event Configuration */ +#define X86_FEATURE_SRSO (11*32+24)/* "" AMD BTB untrain RETs */ +#define X86_FEATURE_SRSO_ALIAS (11*32+25)/* "" AMD BTB untrain RETs through aliasing */ +#define X86_FEATURE_IBPB_ON_VMEXIT (11*32+26)/* "" Issue an IBPB only on VMEXIT */ +/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4)/* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5)/* AVX512 BFLOAT16 instructions */
@@ -442,6 +446,10 @@#define X86_FEATURE_AUTOIBRS (20*32+ 8)/* "" Automatic IBRS */ #define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9)/* "" SMM_CTL MSR is not present */ +#define X86_FEATURE_SBPB (20*32+27)/* "" Selective Branch Prediction Barrier */ +#define X86_FEATURE_IBPB_BRTYPE (20*32+28)/* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */ +#define X86_FEATURE_SRSO_NO (20*32+29)/* "" CPU is not affected by SRSO */ +/* * BUG word(s) */
@@ -483,5 +491,8 @@#define X86_BUG_RETBLEED X86_BUG(27)/* CPU is affected by RETBleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28)/* EIBRS is vulnerable to Post Barrier RSB Predictions */ #define X86_BUG_SMT_RSB X86_BUG(29)/* CPU is vulnerable to Cross-Thread Return Address Predictions */ +#define X86_BUG_GDS X86_BUG(30)/* CPU is affected by Gather Data Sampling */ +/* BUG word 2 */ +#define X86_BUG_SRSO X86_BUG(1*32 + 0)/* AMD SRSO bug */ #endif /* _ASM_X86_CPUFEATURES_H */
arch/x86/include/asm/fpu/api.h +1 -1
@@ -109,7 +109,7 @@ extern void fpu_reset_from_exception_fixup(void);/* Boot, hotplug and resume */ extern void fpu__init_cpu (void ); -extern void fpu__init_system (struct cpuinfo_x86 *c); +extern void fpu__init_system (void );extern void fpu__init_check_bugs (void );extern void fpu__resume_cpu (void );
arch/x86/include/asm/mem_encrypt.h +6 -3
@@ -17,6 +17,12 @@#include <asm/bootparam.h> +#ifdef CONFIG_X86_MEM_ENCRYPT +void __init mem_encrypt_init (void ); +#else +static inline void mem_encrypt_init (void ) { } +#endif +#ifdef CONFIG_AMD_MEM_ENCRYPT extern u64 sme_me_mask;
@@ -87,9 +93,6 @@ static inline void mem_encrypt_free_decrypted_mem(void) { }#endif /* CONFIG_AMD_MEM_ENCRYPT */ -/* Architecture __weak replacement functions */ -void __init mem_encrypt_init (void ); -void add_encrypt_protection_map (void );/*
arch/x86/include/asm/msr-index.h +12 -0
@@ -57,6 +57,7 @@#define MSR_IA32_PRED_CMD 0x00000049/* Prediction Command */ #define PRED_CMD_IBPB BIT(0)/* Indirect Branch Prediction Barrier */ +#define PRED_CMD_SBPB BIT(7)/* Selective Branch Prediction Barrier */ #define MSR_PPIN_CTL 0x0000004e#define MSR_PPIN 0x0000004f
@@ -155,6 +156,15 @@* Not susceptible to Post-Barrier * Return Stack Buffer Predictions. */ +#define ARCH_CAP_GDS_CTRL BIT(25)/* +* CPU is vulnerable to Gather +* Data Sampling (GDS) and +* has controls for mitigation. +*/ +#define ARCH_CAP_GDS_NO BIT(26)/* +* CPU is not vulnerable to Gather +* Data Sampling (GDS). +*/ #define ARCH_CAP_XAPIC_DISABLE BIT(21)/* * IA32_XAPIC_DISABLE_STATUS MSR
@@ -178,6 +188,8 @@#define RNGDS_MITG_DIS BIT(0)/* SRBDS support */ #define RTM_ALLOW BIT(1)/* TSX development mode */ #define FB_CLEAR_DIS BIT(3)/* CPU Fill buffer clear disable */ +#define GDS_MITG_DIS BIT(4)/* Disable GDS mitigation */ +#define GDS_MITG_LOCKED BIT(5)/* GDS mitigation locked */ #define MSR_IA32_SYSENTER_CS 0x00000174#define MSR_IA32_SYSENTER_ESP 0x00000175
arch/x86/include/asm/nospec-branch.h +18 -5
@@ -211,7 +211,8 @@* eventually turn into it's own annotation. */ .macro VALIDATE_UNRET_END -#if defined(CONFIG_NOINSTR_VALIDATION ) && defined(CONFIG_CPU_UNRET_ENTRY ) +#if defined(CONFIG_NOINSTR_VALIDATION ) && \ + (defined(CONFIG_CPU_UNRET_ENTRY ) || defined(CONFIG_CPU_SRSO ))ANNOTATE_RETPOLINE_SAFE nop#endif
@@ -285,13 +286,18 @@*/ .macro UNTRAIN_RET#if defined(CONFIG_CPU_UNRET_ENTRY ) || defined(CONFIG_CPU_IBPB_ENTRY ) || \ - defined(CONFIG_CALL_DEPTH_TRACKING ) + defined(CONFIG_CALL_DEPTH_TRACKING ) || defined(CONFIG_CPU_SRSO )VALIDATE_UNRET_END ALTERNATIVE_3 "", \CALL_ZEN_UNTRAIN_RET ,X86_FEATURE_UNRET , \"call entry_ibpb" ,X86_FEATURE_ENTRY_IBPB , \ __stringify(RESET_CALL_DEPTH), X86_FEATURE_CALL_DEPTH#endif + +#ifdef CONFIG_CPU_SRSO +ALTERNATIVE_2 "" ,"call srso_untrain_ret" ,X86_FEATURE_SRSO , \ +"call srso_untrain_ret_alias" ,X86_FEATURE_SRSO_ALIAS +#endif .endm .macro UNTRAIN_RET_FROM_CALL
@@ -303,6 +309,11 @@"call entry_ibpb" ,X86_FEATURE_ENTRY_IBPB , \ __stringify(RESET_CALL_DEPTH_FROM_CALL), X86_FEATURE_CALL_DEPTH#endif + +#ifdef CONFIG_CPU_SRSO +ALTERNATIVE_2 "" ,"call srso_untrain_ret" ,X86_FEATURE_SRSO , \ +"call srso_untrain_ret_alias" ,X86_FEATURE_SRSO_ALIAS +#endif .endm
@@ -328,6 +339,8 @@ extern retpoline_thunk_t __x86_indirect_jump_thunk_array[];extern void __x86_return_thunk (void );extern void zen_untrain_ret (void ); +extern void srso_untrain_ret (void ); +extern void srso_untrain_ret_alias (void );extern void entry_ibpb (void );#ifdef CONFIG_CALL_THUNKS
@@ -475,11 +488,11 @@ void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature) : "memory"); } +extern u64 x86_pred_cmd; +static inline void indirect_branch_prediction_barrier (void ) { -u64 val =PRED_CMD_IBPB ; - -alternative_msr_write (MSR_IA32_PRED_CMD , val,X86_FEATURE_USE_IBPB ); +alternative_msr_write (MSR_IA32_PRED_CMD , x86_pred_cmd,X86_FEATURE_USE_IBPB ); }/* The Intel SPEC CTRL MSR base value cache */
arch/x86/include/asm/processor.h +2 -0
@@ -683,9 +683,11 @@ extern u16 get_llc_id(unsigned int cpu);#ifdef CONFIG_CPU_SUP_AMD extern u32 amd_get_nodes_per_socket (void );extern u32 amd_get_highest_perf (void ); +extern bool cpu_has_ibpb_brtype_microcode (void );#else static inline u32 amd_get_nodes_per_socket (void ) {return 0 ; }static inline u32 amd_get_highest_perf (void ) {return 0 ; } +static inline bool cpu_has_ibpb_brtype_microcode (void ) {return false; }#endif extern unsigned long arch_align_stack (unsigned long sp);
arch/x86/include/asm/sigframe.h +0 -2
@@ -85,6 +85,4 @@ struct rt_sigframe_x32 {#endif /* CONFIG_X86_64 */ -void __init init_sigframe_size (void ); -#endif /* _ASM_X86_SIGFRAME_H */
arch/x86/kernel/cpu/amd.c +19 -0
@@ -1279,6 +1279,25 @@ u32 amd_get_highest_perf(void) }EXPORT_SYMBOL_GPL (amd_get_highest_perf); +bool cpu_has_ibpb_brtype_microcode (void ) +{ +switch (boot_cpu_data.x86) { +/* Zen1/2 IBPB flushes branch type predictions too. */ +case 0x17 : +return boot_cpu_has (X86_FEATURE_AMD_IBPB ); +case 0x19 : +/* Poke the MSR bit on Zen3/4 to check its presence. */ +if (!wrmsrl_safe (MSR_IA32_PRED_CMD ,PRED_CMD_SBPB )) { +setup_force_cpu_cap (X86_FEATURE_SBPB ); +return true; + }else { +return false; + } +default : +return false; + } +} +static void zenbleed_check_cpu (void *unused) {struct cpuinfo_x86 *c = &cpu_data (smp_processor_id ());
arch/x86/kernel/cpu/bugs.c +338 -50
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arch/x86/kernel/cpu/common.c +106 -17
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arch/x86/kernel/cpu/cpu.h +2 -0
@@ -79,9 +79,11 @@ extern void detect_ht(struct cpuinfo_x86 *c);extern void check_null_seg_clears_base (struct cpuinfo_x86 *c);unsigned int aperfmperf_get_khz (int cpu); +void cpu_select_mitigations (void );extern void x86_spec_ctrl_setup_ap (void );extern void update_srbds_msr (void ); +extern void update_gds_msr (void );extern enum spectre_v2_mitigation spectre_v2_enabled;
arch/x86/kernel/fpu/init.c +4 -4
@@ -53,7 +53,7 @@ void fpu__init_cpu(void)fpu__init_cpu_xstate (); } -static bool fpu__probe_without_cpuid (void ) +static bool __init fpu__probe_without_cpuid (void ) {unsigned long cr0;u16 fsw, fcw;
@@ -71,7 +71,7 @@ static bool fpu__probe_without_cpuid(void)return fsw ==0 && (fcw &0x103f ) ==0x003f ; } -static void fpu__init_system_early_generic (struct cpuinfo_x86 *c) +static void __init fpu__init_system_early_generic (void ) {if (!boot_cpu_has (X86_FEATURE_CPUID ) && !test_bit (X86_FEATURE_FPU , (unsigned long *)cpu_caps_cleared)) {
@@ -211,10 +211,10 @@ static void __init fpu__init_system_xstate_size_legacy(void)* Called on the boot CPU once per system bootup, to set up the initial * FPU state that is later cloned into all processes: */ -void __init fpu__init_system (struct cpuinfo_x86 *c) +void __init fpu__init_system (void ) {fpstate_reset (¤t->thread.fpu); -fpu__init_system_early_generic (c); +fpu__init_system_early_generic ();/* * The FPU has to be operational for some of the
arch/x86/kernel/signal.c +3 -1
@@ -182,7 +182,7 @@ get_sigframe(struct ksignal *ksig, struct pt_regs *regs, size_t frame_size,static unsigned long __ro_after_init max_frame_size;static unsigned int __ro_after_init fpu_default_state_size; -void __init init_sigframe_size (void ) +static int __init init_sigframe_size (void ) { fpu_default_state_size =fpu__get_fpstate_size ();
@@ -194,7 +194,9 @@ void __init init_sigframe_size(void) max_frame_size =round_up (max_frame_size,FRAME_ALIGNMENT );pr_info ("max sigframe size: %lu\n" , max_frame_size); +return 0 ; } +early_initcall (init_sigframe_size);unsigned long get_sigframe_size (void ) {
arch/x86/kernel/vmlinux.lds.S +30 -1
@@ -134,13 +134,27 @@ SECTIONS SOFTIRQENTRY_TEXT #ifdef CONFIG_RETPOLINE __indirect_thunk_start = .; - *(.text.__x86.*) + *(.text.__x86.indirect_thunk) + *(.text.__x86.return_thunk) __indirect_thunk_end = .; #endif STATIC_CALL_TEXT ALIGN_ENTRY_TEXT_BEGIN +#ifdef CONFIG_CPU_SRSO + *(.text.__x86.rethunk_untrain) +#endif + ENTRY_TEXT + +#ifdef CONFIG_CPU_SRSO + /* + * See the comment above srso_untrain_ret_alias()'s + * definition. + */ + . = srso_untrain_ret_alias | (1 << 2) | (1 << 8) | (1 << 14) | (1 << 20); + *(.text.__x86.rethunk_safe) +#endif ALIGN_ENTRY_TEXT_END *(.gnu.warning)
@@ -508,4 +522,19 @@ INIT_PER_CPU(irq_stack_backing_store); "fixed_percpu_data is not at start of per-cpu area"); #endif + #ifdef CONFIG_RETHUNK +. = ASSERT((__ret & 0x3f) == 0, "__ret not cacheline-aligned"); +. = ASSERT((srso_safe_ret & 0x3f) == 0, "srso_safe_ret not cacheline-aligned"); +#endif + +#ifdef CONFIG_CPU_SRSO +/* + * GNU ld cannot do XOR so do: (A | B) - (A & B) in order to compute the XOR + * of the two function addresses: + */ +. = ASSERT(((srso_untrain_ret_alias | srso_safe_ret_alias) - + (srso_untrain_ret_alias & srso_safe_ret_alias)) == ((1 << 2) | (1 << 8) | (1 << 14) | (1 << 20)), + "SRSO function pair won't alias"); +#endif + #endif /* CONFIG_X86_64 */
arch/x86/kvm/cpuid.c +3 -0
@@ -734,6 +734,9 @@ void kvm_set_cpu_caps(void)F (NULL_SEL_CLR_BASE ) |F (AUTOIBRS ) |0 /* PrefetchCtlMsr */ ); +if (cpu_feature_enabled (X86_FEATURE_SRSO_NO )) +kvm_cpu_cap_set (X86_FEATURE_SRSO_NO ); +/* * Synthesize "LFENCE is serializing" into the AMD-defined entry in * KVM's supported CPUID if the feature is reported as supported by the
arch/x86/kvm/svm/svm.c +3 -1
@@ -1511,7 +1511,9 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)if (sd->current_vmcb != svm->vmcb) { sd->current_vmcb = svm->vmcb; -indirect_branch_prediction_barrier (); + +if (!cpu_feature_enabled (X86_FEATURE_IBPB_ON_VMEXIT )) +indirect_branch_prediction_barrier (); }if (kvm_vcpu_apicv_active (vcpu))avic_vcpu_load (vcpu, cpu);
arch/x86/kvm/svm/vmenter.S +3 -0
@@ -224,6 +224,9 @@ SYM_FUNC_START(__svm_vcpu_run) */ UNTRAIN_RET + /* SRSO */ + ALTERNATIVE "", "call entry_ibpb", X86_FEATURE_IBPB_ON_VMEXIT + /* * Clear all general purpose registers except RSP and RAX to prevent * speculative use of the guest's values, even those that are reloaded
arch/x86/kvm/x86.c +6 -1
@@ -314,6 +314,8 @@ u64 __read_mostly host_xcr0;static struct kmem_cache *x86_emulator_cache; +extern bool gds_ucode_mitigated (void ); +/* * When called, it means the previous get/set msr reached an invalid msr. * Return true if we want to ignore/silent this failed msr access.
@@ -1617,7 +1619,7 @@ static bool kvm_is_immutable_feature_msr(u32 msr) ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \ ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \ ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \ - ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO) + ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO)static u64 kvm_get_arch_capabilities (void ) {
@@ -1674,6 +1676,9 @@ static u64 kvm_get_arch_capabilities(void)*/ } +if (!boot_cpu_has_bug (X86_BUG_GDS ) ||gds_ucode_mitigated ()) + data |=ARCH_CAP_GDS_NO ; +return data; }
arch/x86/lib/retpoline.S +79 -4
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arch/x86/xen/smp_pv.c +1 -0
@@ -63,6 +63,7 @@ static void cpu_bringup(void)cr4_init ();cpu_init (); +fpu__init_cpu ();touch_softlockup_watchdog ();/* PVH runs in ring 0 and allows us to do native syscalls. Yay! */
arch/xtensa/include/asm/bugs.h deleted +0 -18
@@ -1,18 +0,0 @@ -/* -* include/asm-xtensa/bugs.h -* -* This is included by init/main.c to check for architecture-dependent bugs. -* -* Xtensa processors don't have any bugs. :) -* -* This file is subject to the terms and conditions of the GNU General -* Public License. See the file "COPYING" in the main directory of -* this archive for more details. -*/ - -#ifndef _XTENSA_BUGS_H -#define _XTENSA_BUGS_H - -static void check_bugs (void ) { } - -#endif /* _XTENSA_BUGS_H */
drivers/base/cpu.c +16 -0
@@ -577,6 +577,18 @@ ssize_t __weak cpu_show_retbleed(struct device *dev,return sysfs_emit (buf,"Not affected\n" ); } +ssize_t __weak cpu_show_gds (struct device *dev, +struct device_attribute *attr,char *buf) +{ +return sysfs_emit (buf,"Not affected\n" ); +} + +ssize_t __weak cpu_show_spec_rstack_overflow (struct device *dev, +struct device_attribute *attr,char *buf) +{ +return sysfs_emit (buf,"Not affected\n" ); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
@@ -588,6 +600,8 @@ static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL); static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL); static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL); static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, NULL); +static DEVICE_ATTR(gather_data_sampling, 0444, cpu_show_gds, NULL); +static DEVICE_ATTR(spec_rstack_overflow, 0444, cpu_show_spec_rstack_overflow, NULL);static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr,
@@ -601,6 +615,8 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_srbds.attr, &dev_attr_mmio_stale_data.attr, &dev_attr_retbleed.attr, + &dev_attr_gather_data_sampling.attr, + &dev_attr_spec_rstack_overflow.attr, NULL };
drivers/net/xen-netback/netback.c +10 -5
@@ -396,7 +396,7 @@ static void xenvif_get_requests(struct xenvif_queue *queue,struct gnttab_map_grant_ref *gop = queue->tx_map_ops + *map_ops;struct xen_netif_tx_request *txp = first; - nr_slots = shinfo->nr_frags +1 ; + nr_slots = shinfo->nr_frags + frag_overflow +1 ;copy_count (skb) =0 ;XENVIF_TX_CB (skb)->split_mask =0 ;
@@ -462,8 +462,8 @@ static void xenvif_get_requests(struct xenvif_queue *queue, } } -for (shinfo->nr_frags =0 ; shinfo->nr_frags < nr_slots; - shinfo->nr_frags++, gop++) { +for (shinfo->nr_frags =0 ; nr_slots >0 && shinfo->nr_frags <MAX_SKB_FRAGS ; + shinfo->nr_frags++, gop++, nr_slots--) { index =pending_index (queue->pending_cons++); pending_idx = queue->pending_ring[index]; xenvif_tx_create_map_op(queue, pending_idx, txp,
@@ -476,12 +476,12 @@ static void xenvif_get_requests(struct xenvif_queue *queue, txp++; } -if (frag_overflow) { +if (nr_slots >0 ) { shinfo =skb_shinfo (nskb); frags = shinfo->frags; -for (shinfo->nr_frags =0 ; shinfo->nr_frags < frag_overflow; +for (shinfo->nr_frags =0 ; shinfo->nr_frags < nr_slots; shinfo->nr_frags++, txp++, gop++) { index =pending_index (queue->pending_cons++); pending_idx = queue->pending_ring[index];
@@ -492,6 +492,11 @@ static void xenvif_get_requests(struct xenvif_queue *queue, }skb_shinfo (skb)->frag_list = nskb; + }else if (nskb) { +/* A frag_list skb was allocated but it is no longer needed +* because enough slots were converted to copy ops above. +*/ +kfree_skb (nskb); } (*copy_ops) = cop - queue->tx_copy_ops;
include/asm-generic/bugs.h deleted +0 -11
@@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_GENERIC_BUGS_H -#define __ASM_GENERIC_BUGS_H -/* -* This file is included by 'init/main.c' to check for -* architecture-dependent bugs. -*/ - -static inline void check_bugs (void ) { } - -#endif /* __ASM_GENERIC_BUGS_H */
include/linux/cpu.h +8 -0
@@ -70,6 +70,8 @@ extern ssize_t cpu_show_mmio_stale_data(struct device *dev, char *buf);extern ssize_t cpu_show_retbleed (struct device *dev,struct device_attribute *attr,char *buf); +extern ssize_t cpu_show_spec_rstack_overflow (struct device *dev, +struct device_attribute *attr,char *buf); extern __printf(4, 5) struct device *cpu_device_create(struct device *parent, void *drvdata,
@@ -184,6 +186,12 @@ void arch_cpu_idle_enter(void);void arch_cpu_idle_exit (void );void __noreturn arch_cpu_idle_dead (void ); +#ifdef CONFIG_ARCH_HAS_CPU_FINALIZE_INIT +void arch_cpu_finalize_init (void ); +#else +static inline void arch_cpu_finalize_init (void ) { } +#endif +int cpu_report_state (int cpu);int cpu_check_up_prepare (int cpu);void cpu_set_state_online (int cpu);
init/main.c +1 -15
@@ -95,7 +95,6 @@#include <linux/cache.h> #include <linux/rodata_test.h> #include <linux/jump_label.h> -#include <linux/mem_encrypt.h> #include <linux/kcsan.h> #include <linux/init_syscalls.h> #include <linux/stackdepot.h>
@@ -103,7 +102,6 @@#include <net/net_namespace.h> #include <asm/io.h> -#include <asm/bugs.h> #include <asm/setup.h> #include <asm/sections.h> #include <asm/cacheflush.h>
@@ -787,8 +785,6 @@ void __init __weak thread_stack_cache_init(void) }#endif -void __init __weak mem_encrypt_init (void ) { } -void __init __weak poking_init (void ) { }void __init __weak pgtable_cache_init (void ) { }
@@ -1043,15 +1039,7 @@ void start_kernel(void)sched_clock_init ();calibrate_delay (); -/* -* This needs to be called before any devices perform DMA -* operations that might use the SWIOTLB bounce buffers. It will -* mark the bounce buffers as decrypted so that their usage will -* not cause "plain-text" data to be decrypted when accessed. It -* must be called after late_time_init() so that Hyper-V x86/x64 -* hypercalls work when the SWIOTLB bounce buffers are decrypted. -*/ -mem_encrypt_init (); +arch_cpu_finalize_init ();pid_idr_init ();anon_vma_init ();
@@ -1079,8 +1067,6 @@ void start_kernel(void)taskstats_init_early ();delayacct_init (); -check_bugs (); -acpi_subsystem_init ();arch_post_acpi_subsys_init ();kcsan_init ();
tools/arch/x86/include/asm/cpufeatures.h +1 -1
@@ -14,7 +14,7 @@* Defines x86 CPU feature bits */ #define NCAPINTS 21/* N 32-bit words worth of info */ -#define NBUGINTS 1/* N 32-bit bug flags */ +#define NBUGINTS 2/* N 32-bit bug flags */ /* * Note: If the comment begins with a quoted string, that string is used
tools/objtool/arch/x86/decode.c +4 -1
@@ -824,5 +824,8 @@ bool arch_is_retpoline(struct symbol *sym)bool arch_is_rethunk (struct symbol *sym) { -return !strcmp (sym->name,"__x86_return_thunk" ); +return !strcmp (sym->name,"__x86_return_thunk" ) || + !strcmp (sym->name,"srso_untrain_ret" ) || + !strcmp (sym->name,"srso_safe_ret" ) || + !strcmp (sym->name,"__ret" ); }