Linux 5.4.256
Greg Kroah-Hartman
maintainerI'm announcing the release of the 5.4.256 kernel.
All users of the 5.4 kernel series must upgrade.
The updated 5.4.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linux-5.4.y
and can be browsed at the normal kernel.org git web browser:
https://git.kernel.org/?p=linux/kernel/git/stable/linux-stable.git;a=summary
thanks,
greg k-h
------------
Makefile | 2 +- arch/mips/alchemy/common/dbdma.c | 27 ++++++++++++--------------- arch/powerpc/platforms/powermac/smp.c | 8 ++++---- 3 files changed, 17 insertions(+), 20 deletions(-)
Greg Kroah-Hartman (2):
Revert "MIPS: Alchemy: fix dbdma2"
Linux 5.4.256
Ilie Halip (1):
powerpc/pmac/smp: Avoid unused-variable warnings
YueHaibing (1):
powerpc/pmac/smp: Drop unnecessary volatile qualifier
Greg Kroah-Hartman
maintainerMakefile +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 4 -SUBLEVEL = 255 +SUBLEVEL = 256 EXTRAVERSION = NAME = Kleptomaniac Octopus
arch/mips/alchemy/common/dbdma.c +12 -15
@@ -30,7 +30,6 @@* */ -#include <linux/dma-map-ops.h> /* for dma_default_coherent */ #include <linux/init.h> #include <linux/kernel.h> #include <linux/slab.h>
@@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_cmd0 &= ~DSCR_CMD0_IE ;/* -* There is an erratum on certain Au1200/Au1550 revisions that could -* result in "stale" data being DMA'ed. It has to do with the snoop -* logic on the cache eviction buffer. dma_default_coherent is set -* to false on these parts. +* There is an errata on the Au1200/Au1550 parts that could result +* in "stale" data being DMA'ed. It has to do with the snoop logic on +* the cache eviction buffer. DMA_NONCOHERENT is on by default for +* these parts. If it is fixed in the future, these dma_cache_inv will +* just be nothing more than empty macros. See io.h. */ -if (!dma_default_coherent) -dma_cache_wback_inv (KSEG0ADDR (buf), nbytes); +dma_cache_wback_inv ((unsigned long )buf, nbytes); dp->dscr_cmd0 |=DSCR_CMD0_V ;/* Let it rip */ wmb ();/* drain writebuffer */ dma_cache_wback_inv ((unsigned long )dp,sizeof (*dp)); ctp->chan_ptr->ddma_dbell =0 ; -wmb ();/* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr =phys_to_virt (DSCR_GET_NXTPTR (dp->dscr_nxtptr));
@@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);#endif /* -* There is an erratum on certain Au1200/Au1550 revisions that could -* result in "stale" data being DMA'ed. It has to do with the snoop -* logic on the cache eviction buffer. dma_default_coherent is set -* to false on these parts. +* There is an errata on the Au1200/Au1550 parts that could result in +* "stale" data being DMA'ed. It has to do with the snoop logic on the +* cache eviction buffer. DMA_NONCOHERENT is on by default for these +* parts. If it is fixed in the future, these dma_cache_inv will just +* be nothing more than empty macros. See io.h. */ -if (!dma_default_coherent) -dma_cache_inv (KSEG0ADDR (buf), nbytes); +dma_cache_inv ((unsigned long )buf, nbytes); dp->dscr_cmd0 |=DSCR_CMD0_V ;/* Let it rip */ wmb ();/* drain writebuffer */ dma_cache_wback_inv ((unsigned long )dp,sizeof (*dp)); ctp->chan_ptr->ddma_dbell =0 ; -wmb ();/* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr =phys_to_virt (DSCR_GET_NXTPTR (dp->dscr_nxtptr));
arch/powerpc/platforms/powermac/smp.c +4 -4
@@ -660,13 +660,13 @@ static void smp_core99_gpio_tb_freeze(int freeze)#endif /* !CONFIG_PPC64 */ -/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ -volatile static long int core99_l2_cache; -volatile static long int core99_l3_cache; -static void core99_init_caches (int cpu) {#ifndef CONFIG_PPC64 +/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ +static long int core99_l2_cache; +static long int core99_l3_cache; +if (!cpu_has_feature (CPU_FTR_L2CR ))return ;