raw/ntb: add support for 5th and 6th Gen Intel Xeon
PATCH 1/1 raw/ntb: add support for 5th and 6th Gen Intel Xeon
Add support for 5th and 6th Gen Intel Xeon Scalable processors. Note that NTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors share the same device id, and compliant to PCIe 4.0 spec. And the NTB devices within 6th Gen Intel Xeon compliant to PCIe 5.0.
--- doc/guides/rawdevs/ntb.rst | 8 +- drivers/raw/ntb/ntb.c | 10 +- drivers/raw/ntb/ntb.h | 6 +- drivers/raw/ntb/ntb_hw_intel.c | 190 +++++++++++++++------------------ drivers/raw/ntb/ntb_hw_intel.h | 96 ++++++++++------- usertools/dpdk-devbind.py | 8 +- 6 files changed, 159 insertions(+), 159 deletions(-)
doc/guides/rawdevs/ntb.rst +5 -3
@@ -153,6 +153,8 @@ Limitation This PMD is only supported on Intel Xeon Platforms: -- 4th Generation Intel® Xeon® Scalable Processors. -- 3rd Generation Intel® Xeon® Scalable Processors. -- 2nd Generation Intel® Xeon® Scalable Processors. +- 6th Generation Intel® Xeon® Scalable Processors. (NTB GEN5 device id: 0x0DB4) +- 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E) +- 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E) +- 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E) +- 2nd Generation Intel® Xeon® Scalable Processors. (NTB GEN3 device id: 0x201C)
drivers/raw/ntb/ntb.c +6 -4
@@ -24,8 +24,9 @@#include "ntb.h" static const struct rte_pci_id pci_id_ntb_map[] = { - {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_SKX ) }, - {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_ICX ) }, + {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN3 ) }, + {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN4 ) }, + {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN5 ) }, { .vendor_id =0 ,/* sentinel */ }, };
@@ -1378,8 +1379,9 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev) hw->link_width =NTB_WIDTH_NONE ;switch (pci_dev->id.device_id) { -case NTB_INTEL_DEV_ID_B2B_SKX : -case NTB_INTEL_DEV_ID_B2B_ICX : +case NTB_INTEL_DEV_ID_B2B_GEN3 : +case NTB_INTEL_DEV_ID_B2B_GEN4 : +case NTB_INTEL_DEV_ID_B2B_GEN5 : hw->ntb_ops = &intel_ntb_ops;break ;default :
drivers/raw/ntb/ntb.h +3 -3
@@ -17,9 +17,9 @@ extern int ntb_logtype;#define NTB_INTEL_VENDOR_ID 0x8086/* Device IDs */ -#define NTB_INTEL_DEV_ID_B2B_SKX 0x201C -#define NTB_INTEL_DEV_ID_B2B_ICX 0x347E -#define NTB_INTEL_DEV_ID_B2B_SPR 0x347E +#define NTB_INTEL_DEV_ID_B2B_GEN3 0x201C +#define NTB_INTEL_DEV_ID_B2B_GEN4 0x347E +#define NTB_INTEL_DEV_ID_B2B_GEN5 0x0DB4/* Reserved to app to use. */ #define NTB_SPAD_USER "spad_user_"
drivers/raw/ntb/ntb_hw_intel.c +84 -106
347 lines not on this page · raw message
drivers/raw/ntb/ntb_hw_intel.h +58 -38
128 lines not on this page · raw message
usertools/dpdk-devbind.py +3 -5
@@ -60,10 +60,8 @@ 'SVendor': None, 'SDevice': None} intel_idxd_spr = {'Class': '08', 'Vendor': '8086', 'Device': '0b25', 'SVendor': None, 'SDevice': None} -intel_ntb_skx = {'Class': '06', 'Vendor': '8086', 'Device': '201c', - 'SVendor': None, 'SDevice': None} -intel_ntb_icx = {'Class': '06', 'Vendor': '8086', 'Device': '347e', - 'SVendor': None, 'SDevice': None} +intel_ntb = {'Class': '06', 'Vendor': '8086', 'Device': '201c,347e,0db4', + 'SVendor': None, 'SDevice': None} cnxk_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa', 'SVendor': None, 'SDevice': None}
@@ -89,7 +87,7 @@ regex_devices = [cn9k_ree] ml_devices = [cnxk_ml] misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev, - intel_ntb_skx, intel_ntb_icx, + intel_ntb, virtio_blk] # global dict ethernet devices present. Dictionary indexed by PCI address.
Signature · 1 line
2.34.1
Quoted 37 lines
-----Original Message-----
From: Guo, Junfeng <[email protected]>
Sent: Friday, September 15, 2023 3:08 PM
To: Wu, Jingjing <[email protected]>
Cc: [email protected]; Guo, Junfeng <[email protected]>
Subject: [PATCH] raw/ntb: add support for 5th and 6th Gen Intel XeonAdd support for 5th and 6th Gen Intel Xeon Scalable processors. Note that NTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors share the same device id, and compliant to PCIe 4.0 spec. And the NTB devices within 6th Gen Intel Xeon compliant to PCIe 5.0.
Signed-off-by Junfeng Guo <[email protected]>--- doc/guides/rawdevs/ntb.rst | 8 +- drivers/raw/ntb/ntb.c | 10 +- drivers/raw/ntb/ntb.h | 6 +- drivers/raw/ntb/ntb_hw_intel.c | 190 +++++++++++++++------------------ drivers/raw/ntb/ntb_hw_intel.h | 96 ++++++++++------- usertools/dpdk-devbind.py | 8 +- 6 files changed, 159 insertions(+), 159 deletions(-)doc/guides/rawdevs/ntb.rst +1
-3@@ -153,6 +153,8 @@ Limitation This PMD is only supported on Intel Xeon Platforms: -- 4th Generation Intel® Xeon® Scalable Processors. -- 3rd Generation Intel® Xeon® Scalable Processors. -- 2nd Generation Intel® Xeon® Scalable Processors. +- 6th Generation Intel® Xeon® Scalable Processors. (NTB GEN5 device id:
0x0DB4)
Quoted 8 lines
+- 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id:
0x347E)
+- 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id:0x347E)
+- 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id:0x347E)
+- 2nd Generation Intel® Xeon® Scalable Processors. (NTB GEN3 device id:0x201C)
Add release note update too as new platform is added?
Quoted 54 lines
-----Original Message-----
From: Wu, Jingjing <[email protected]>
Sent: Friday, September 15, 2023 17:14
To: Guo, Junfeng <[email protected]>
Cc: [email protected]
Subject: RE: [PATCH] raw/ntb: add support for 5th and 6th Gen Intel XeonQuoted 27 lines
-----Original Message-----
From: Guo, Junfeng <[email protected]>
Sent: Friday, September 15, 2023 3:08 PM
To: Wu, Jingjing <[email protected]>
Cc: [email protected]; Guo, Junfeng <[email protected]>
Subject: [PATCH] raw/ntb: add support for 5th and 6th Gen Intel XeonAdd support for 5th and 6th Gen Intel Xeon Scalable processors. Note that NTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors share the same device id, and compliant to PCIe 4.0 spec. And the NTB devices within 6th Gen Intel Xeon compliant to PCIe 5.0.
Signed-off-by Junfeng Guo <[email protected]>--- doc/guides/rawdevs/ntb.rst | 8 +- drivers/raw/ntb/ntb.c | 10 +- drivers/raw/ntb/ntb.h | 6 +- drivers/raw/ntb/ntb_hw_intel.c | 190 +++++++++++++++------------------ drivers/raw/ntb/ntb_hw_intel.h | 96 ++++++++++------- usertools/dpdk-devbind.py | 8 +- 6 files changed, 159 insertions(+), 159 deletions(-)doc/guides/rawdevs/ntb.rst +0
-0doc/guides/rawdevs/ntb.rst Limitation · line 156
Quoted 7 lines
doc/guides/rawdevs/ntb.rst +1
-3@@ -153,6 +153,8 @@ Limitation This PMD is only supported on Intel Xeon Platforms: -- 4th Generation Intel® Xeon® Scalable Processors. -- 3rd Generation Intel® Xeon® Scalable Processors. -- 2nd Generation Intel® Xeon® Scalable Processors. +- 6th Generation Intel® Xeon® Scalable Processors. (NTB GEN5 deviceid:
Quoted 2 lines
0x0DB4)
+- 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 deviceid:
Quoted 2 lines
0x347E)
+- 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 deviceid:
Quoted 2 lines
0x347E)
+- 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device
Quoted 7 lines
id:
Quoted 2 lines
0x347E)
+- 2nd Generation Intel® Xeon® Scalable Processors. (NTB GEN3 deviceid:
Quoted 1 line
0x201C)Add release note update too as new platform is added?
Yes, just as before we did to support NTB on 4th Gen Intel Xeon platforms. And here we also added the device id info for each supported Intel Xeon. Thanks!
RFC 1/1 raw/ntb: add support for 6th Gen Intel Xeon
In reply to Junfeng GuoAdd support for the 6th Gen Intel Xeon Scalable processors. Note that NTB devices within the 6th Gen Intel Xeon compliant to PCIe 5.0 spec.
---
Depends-on: series-30460 \
("raw/ntb: refactor to support NTB on 5th Gen Intel Xeon")
--- doc/guides/rawdevs/ntb.rst | 1 + drivers/raw/ntb/ntb.c | 2 ++ drivers/raw/ntb/ntb.h | 1 + drivers/raw/ntb/ntb_hw_intel.c | 66 +++++++++++++++++----------------- drivers/raw/ntb/ntb_hw_intel.h | 40 ++++++++++++--------- usertools/dpdk-devbind.py | 2 +- 6 files changed, 61 insertions(+), 51 deletions(-)
doc/guides/rawdevs/ntb.rst +1 -0
@@ -153,6 +153,7 @@ Limitation This PMD is only supported on Intel Xeon Platforms: +- 6th Generation Intel® Xeon® Scalable Processors. (NTB GEN5 device id: 0x0DB4) - 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E) - 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E) - 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)
drivers/raw/ntb/ntb.c +2 -0
@@ -26,6 +26,7 @@static const struct rte_pci_id pci_id_ntb_map[] = { {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN3 ) }, {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN4 ) }, + {RTE_PCI_DEVICE (NTB_INTEL_VENDOR_ID ,NTB_INTEL_DEV_ID_B2B_GEN5 ) }, { .vendor_id =0 ,/* sentinel */ }, };
@@ -1380,6 +1381,7 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)switch (pci_dev->id.device_id) {case NTB_INTEL_DEV_ID_B2B_GEN3 :case NTB_INTEL_DEV_ID_B2B_GEN4 : +case NTB_INTEL_DEV_ID_B2B_GEN5 : hw->ntb_ops = &intel_ntb_ops;break ;default :
drivers/raw/ntb/ntb.h +1 -0
@@ -19,6 +19,7 @@ extern int ntb_logtype;/* Device IDs */ #define NTB_INTEL_DEV_ID_B2B_GEN3 0x201C#define NTB_INTEL_DEV_ID_B2B_GEN4 0x347E +#define NTB_INTEL_DEV_ID_B2B_GEN5 0x0DB4/* Reserved to app to use. */ #define NTB_SPAD_USER "spad_user_"
drivers/raw/ntb/ntb_hw_intel.c +33 -33
170 lines not on this page · raw message
drivers/raw/ntb/ntb_hw_intel.h +23 -17
@@ -42,11 +42,11 @@#define XEON_CORERRSTS_OFFSET 0x0158#define XEON_NTB3_LINK_STATUS_OFFSET 0x01a2/* Link status and PPD are in MMIO but not config space for Gen4/5 NTB */ -#define XEON_NTB4_PPD0_OFFSET 0xb0d4 -#define XEON_NTB4_PPD1_OFFSET 0xb4c0 -#define XEON_NTB4_LINK_CTRL_OFFSET 0xb050 -#define XEON_NTB4_LINK_STATUS_OFFSET 0xb052 -#define XEON_NTB4_LINK_CTRL_LINK_DIS 0x0010 +#define XEON_NTB4_5_PPD0_OFFSET 0xb0d4 +#define XEON_NTB4_5_PPD1_OFFSET 0xb4c0 +#define XEON_NTB4_5_LINK_CTRL_OFFSET 0xb050 +#define XEON_NTB4_5_LINK_STATUS_OFFSET 0xb052 +#define XEON_NTB4_5_LINK_CTRL_LINK_DIS 0x0010#define XEON_NTBCNTL_OFFSET 0x0000
@@ -56,16 +56,16 @@#define XEON_IMBAR2XBASE_OFFSET 0x0020/* SBAR4XLAT */ #define XEON_IMBAR2XLMT_OFFSET 0x0028/* SBAR4LMT */ #define XEON_XBASEIDX_INTERVAL 0x0002 -#define XEON_NTB4_IM1XBASEIDX_OFFSET 0x0074 -#define XEON_NTB4_IM2XBASEIDX_OFFSET 0x0076 +#define XEON_NTB4_5_IM1XBASEIDX_OFFSET 0x0074 +#define XEON_NTB4_5_IM2XBASEIDX_OFFSET 0x0076#define XEON_IM_INT_STATUS_OFFSET 0x0040#define XEON_IM_INT_DISABLE_OFFSET 0x0048#define XEON_IM_SPAD_OFFSET 0x0080/* SPAD */ #define XEON_NTB3_B2B_SPAD_OFFSET 0x0180/* NTB GEN3 B2B SPAD */ -#define XEON_NTB4_B2B_SPAD_OFFSET 0x8080/* NTB GEN4/5 B2B SPAD */ +#define XEON_NTB4_5_B2B_SPAD_OFFSET 0x8080/* NTB GEN4/5 B2B SPAD */ #define XEON_USMEMMISS_OFFSET 0x0070#define XEON_NTB3_INTVEC_OFFSET 0x00d0 -#define XEON_NTB4_INTVEC_OFFSET 0x0050 +#define XEON_NTB4_5_INTVEC_OFFSET 0x0050#define XEON_IM_DOORBELL_OFFSET 0x0100/* SDOORBELL0 */ #define XEON_EMBAR0XBASE_OFFSET 0x4008/* B2B_XLAT */ #define XEON_EMBAR1XBASE_OFFSET 0x4010/* PBAR2XLAT */
@@ -95,15 +95,15 @@#define XEON_GEN3_NTB4_PPD_DEV_DSD 0x1000#define XEON_GEN3_NTB4_PPD_DEV_USD 0x0000 -#define XEON_NTB4_PPD_CONN_MASK 0x0700 -#define XEON_NTB4_PPD_CONN_B2B 0x0200 -#define XEON_NTB4_PPD_DEV_MASK 0x4000 -#define XEON_NTB4_PPD_DEV_DSD 0x4000 -#define XEON_NTB4_PPD_DEV_USD 0x0000 +#define XEON_NTB4_5_PPD_CONN_MASK 0x0700 +#define XEON_NTB4_5_PPD_CONN_B2B 0x0200 +#define XEON_NTB4_5_PPD_DEV_MASK 0x4000 +#define XEON_NTB4_5_PPD_DEV_DSD 0x4000 +#define XEON_NTB4_5_PPD_DEV_USD 0x0000 -#define XEON_NTB4_PPD_LINKTRN 0x0008 -#define XEON_NTB4_SLOTSTS 0xb05a -#define XEON_NTB4_SLOTSTS_DLLSCS 0x100 +#define XEON_NTB4_5_PPD_LINKTRN 0x0008 +#define XEON_NTB4_5_SLOTSTS 0xb05a +#define XEON_NTB4_5_SLOTSTS_DLLSCS 0x100#define XEON_MW_COUNT 2
@@ -129,4 +129,10 @@ is_gen4_ntb(const struct rte_pci_device *pci_dev) return pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_GEN4; } +static inline bool +is_gen5_ntb (const struct rte_pci_device *pci_dev) +{ +return pci_dev->id.device_id ==NTB_INTEL_DEV_ID_B2B_GEN5 ; +} +#endif /* _NTB_HW_INTEL_H_ */
usertools/dpdk-devbind.py +1 -1
@@ -60,7 +60,7 @@ 'SVendor': None, 'SDevice': None} intel_idxd_spr = {'Class': '08', 'Vendor': '8086', 'Device': '0b25', 'SVendor': None, 'SDevice': None} -intel_ntb = {'Class': '06', 'Vendor': '8086', 'Device': '201c,347e', +intel_ntb = {'Class': '06', 'Vendor': '8086', 'Device': '201c,347e,0db4', 'SVendor': None, 'SDevice': None} cnxk_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa',
Signature · 1 line
2.34.1
Re: [RFC v1] raw/ntb: add support for 6th Gen Intel Xeon
Quoted 4 lines · On Fri, 8 Dec 2023 16:07:59 +0800 Junfeng Guo <[email protected]> wrote:
Add support for the 6th Gen Intel Xeon Scalable processors. Note that NTB devices within the 6th Gen Intel Xeon compliant to PCIe 5.0 spec.
Signed-off-by Junfeng Guo <[email protected]>
I would combine the 5th and 6th patches together in new version.