riscv,isa-extensions additions

RFC In review Conor Dooley 6 participants 17 messages Sep 22, 2023 – Oct 9, 2023

Subsystems (9)

Device tree bindings RISC-V Arm/RISC-V/Renesas architecture Arm/Allwinner sunXi SoC support +5 more subsystems

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Conor Dooley

author maintainer

2023-09-22 08:15 UTC #0 lore raw

v2 cover riscv,isa-extensions additions

From: Conor Dooley <[email protected]>

I'm suffering from a hw failure on my main dev machine & relegated to a recently acquired & not really configured laptop for a bit, so hopefully nothing with this series goes awry. (rfc v2: I think my board farm might actually have been the source of the failure - I did hear a large pop when I turned it on the day before the thing started not booting. Motherboard seems to be kaput!)

I've had two (or more, dunnno) people ask me where the patches for the DTs were swapping them over, so here's what I had before the hw failure. I've marked this RFC as a result & I'd like to come back and revisit these patches once I'm out of this limited environment.
This "RFC v2" just fixes the silly issue that was pointed out by Chen Wang & the patchwork automation, where I used the wrong property name everywhere.

The canaan stuff is absent here, mostly because I don't actually know what to do with it. They don't actually implement the same versions of the F stuff as everyone else (Stefan O'Rear pointed that out to me somewhere recently).

Cheers,
Conor.

CC Rob Herring <[email protected]>

CC Krzysztof Kozlowski <[email protected]>

CC Conor Dooley <[email protected]>

CC Paul Walmsley <[email protected]>

CC Palmer Dabbelt <[email protected]>

CC Albert Ou <[email protected]>

CC Chen-Yu Tsai <[email protected]>

CC Jernej Skrabec <[email protected]>

CC Samuel Holland <[email protected]>

CC Daire McNamara <[email protected]>

CC Geert Uytterhoeven <[email protected]>

CC Magnus Damm <[email protected]>

CC Emil Renner Berthing <[email protected]>

CC Jisheng Zhang <[email protected]>

CC Guo Ren <[email protected]>

CC Fu Wei <[email protected]>

CC Chen Wang <[email protected]>

CC [email protected]

Conor Dooley (6):
riscv: dts: microchip: convert isa detection to new properties
riscv: dts: sifive: convert isa detection to new properties
riscv: dts: starfive: convert isa detection to new properties
riscv: dts: renesas: convert isa detection to new properties
riscv: dts: allwinner: convert isa detection to new properties
riscv: dts: thead: convert isa detection to new properties

 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi |  3 +++
 arch/riscv/boot/dts/microchip/mpfs.dtsi       | 15 +++++++++++++++
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  3 +++
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi    | 15 +++++++++++++++
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi    | 15 +++++++++++++++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      |  6 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 15 +++++++++++++++
 arch/riscv/boot/dts/thead/th1520.dtsi         | 12 ++++++++++++
 8 files changed, 84 insertions(+)

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:15 UTC #1 lore raw

RFC v2 1/6 riscv: dts: microchip: convert isa detection to new properties

From: Conor Dooley <[email protected]>

Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/riscv/boot/dts/microchip/mpfs.dtsi +15 -0

index 104504352e99..a6faf24f1dba 100644
@@ -22,6 +22,9 @@ cpu0: cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			status = "disabled";

@@ -48,6 +51,9 @@ cpu1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -76,6 +82,9 @@ cpu2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -104,6 +113,9 @@ cpu3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

@@ -132,6 +144,9 @@ cpu4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			clocks = <&clkcfg CLK_CPU>;
 			tlb-split;
 			next-level-cache = <&cctrllr>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:15 UTC #2 lore raw

RFC v2 2/6 riscv: dts: sifive: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

arch/riscv/boot/dts/sifive/fu540-c000.dtsi +15 -0

index 24bba83bec77..156330a9bbf3 100644
@@ -30,6 +30,9 @@ cpu0: cpu@0 {
 			i-cache-size = <16384>;
 			reg = <0>;
 			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			status = "disabled";
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -53,6 +56,9 @@ cpu1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			reg = <1>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu1_intc: interrupt-controller {

@@ -77,6 +83,9 @@ cpu2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			reg = <2>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu2_intc: interrupt-controller {

@@ -101,6 +110,9 @@ cpu3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			reg = <3>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu3_intc: interrupt-controller {

@@ -125,6 +137,9 @@ cpu4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			reg = <4>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			next-level-cache = <&l2cache>;
 			cpu4_intc: interrupt-controller {

arch/riscv/boot/dts/sifive/fu740-c000.dtsi +15 -0

index 5235fd1c9cb6..6150f3397bff 100644
@@ -31,6 +31,9 @@ cpu0: cpu@0 {
 			next-level-cache = <&ccache>;
 			reg = <0x0>;
 			riscv,isa = "rv64imac";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+					       "zihpm";
 			status = "disabled";
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -55,6 +58,9 @@ cpu1: cpu@1 {
 			next-level-cache = <&ccache>;
 			reg = <0x1>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -79,6 +85,9 @@ cpu2: cpu@2 {
 			next-level-cache = <&ccache>;
 			reg = <0x2>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu2_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -103,6 +112,9 @@ cpu3: cpu@3 {
 			next-level-cache = <&ccache>;
 			reg = <0x3>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu3_intc: interrupt-controller {
 				#interrupt-cells = <1>;

@@ -127,6 +139,9 @@ cpu4: cpu@4 {
 			next-level-cache = <&ccache>;
 			reg = <0x4>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 			cpu4_intc: interrupt-controller {
 				#interrupt-cells = <1>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:15 UTC #4 lore raw

RFC v2 3/6 riscv: dts: starfive: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/starfive/jh7100.dtsi |  6 ++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 2 files changed, 21 insertions(+)

arch/riscv/boot/dts/starfive/jh7100.dtsi +6 -0

index 35ab54fb235f..e68cafe7545f 100644
@@ -33,6 +33,9 @@ U74_0: cpu@0 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 
 			cpu0_intc: interrupt-controller {

@@ -58,6 +61,9 @@ U74_1: cpu@1 {
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			tlb-split;
 
 			cpu1_intc: interrupt-controller {

arch/riscv/boot/dts/starfive/jh7110.dtsi +15 -0

index e85464c328d0..90b35be9aa6c 100644
@@ -28,6 +28,9 @@ S7_0: cpu@0 {
 			i-cache-size = <16384>;
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imac_zba_zbb";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			status = "disabled";
 
 			cpu0_intc: interrupt-controller {

@@ -54,6 +57,9 @@ U74_1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -84,6 +90,9 @@ U74_2: cpu@2 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -114,6 +123,9 @@ U74_3: cpu@3 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

@@ -144,6 +156,9 @@ U74_4: cpu@4 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc_zba_zbb";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+					       "zicsr", "zifencei", "zihpm";
 			tlb-split;
 			operating-points-v2 = <&cpu_opp>;
 			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:15 UTC #5 lore raw

RFC v2 4/6 riscv: dts: renesas: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +3 -0

index 6ec1c6f9a403..8a726407fb76 100644
@@ -24,6 +24,9 @@ cpu0: cpu@0 {
 			reg = <0x0>;
 			status = "okay";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			mmu-type = "riscv,sv39";
 			i-cache-size = <0x8000>;
 			i-cache-line-size = <0x40>;

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:15 UTC #6 lore raw

RFC v2 5/6 riscv: dts: allwinner: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +3 -0

index 8275630af977..947e975d2476 100644
@@ -25,6 +25,9 @@ cpu0: cpu@0 {
 			mmu-type = "riscv,sv39";
 			operating-points-v2 = <&opp_table_cpu>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

Signature · 1 line

2.41.0

Conor Dooley

author maintainer

2023-09-22 08:16 UTC #8 lore raw

RFC v2 6/6 riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/thead/th1520.dtsi +12 -0

index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -41,6 +44,9 @@ c910_1: cpu@1 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -62,6 +68,9 @@ c910_2: cpu@2 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -83,6 +92,9 @@ c910_3: cpu@3 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

Signature · 1 line

2.41.0

Guo Ren

maintainer

2023-09-23 07:50 UTC #9 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

Quoted 17 lines · Conor Dooley

From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/thead/th1520.dtsi +0 -0
index ce708183b6f6..723f65487246 100644

arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 23

Quoted 4 lines

arch/riscv/boot/dts/thead/th1520.dtsi +1 -0

@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";

Why not riscv,isa-base = "rv64"? I saw "i" in the riscv,isa-extensions.

Maybe this question should be in this mailing thread and a little late:
https://lore.kernel.org/linux-riscv/20230713-tablet-jimmy-987fea0eb2e1@wendy/

Quoted 36 lines

arch/riscv/boot/dts/thead/th1520.dtsi +11 -1

+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <0>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;

@@ -41,6 +44,9 @@ c910_1: cpu@1 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <1>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;

@@ -62,6 +68,9 @@ c910_2: cpu@2 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <2>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;

@@ -83,6 +92,9 @@ c910_3: cpu@3 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        reg = <3>;
                        i-cache-block-size = <64>;
                        i-cache-size = <65536>;
--

Quoted 2 lines

2.41.0

--
Best Regards
Guo Ren

Conor Dooley

author maintainer

2023-09-23 10:25 UTC #10 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

Quoted 13 lines · Guo Ren

Quoted 12 lines · Conor Dooley
From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Quoted 11 lines

arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 23

Quoted 9 lines

arch/riscv/boot/dts/thead/th1520.dtsi +1 -0

index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";

Why not riscv,isa-base = "rv64"? I saw "i" in the riscv,isa-extensions.

I did it that way as a hedge against things changing in the future. I have little trust in that part of the ISA specifications.

Icenowy Zheng

2023-09-23 23:23 UTC #12 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

Quoted 17 lines · 在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：

From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/thead/th1520.dtsi +0 -0
index ce708183b6f6..723f65487246 100644

arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 26

Quoted 7 lines

arch/riscv/boot/dts/thead/th1520.dtsi +3 -0

@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";

Zfh is supported by T-Head C9xx with float too.

In addition, should X extensions get listed here?

Quoted 36 lines

arch/riscv/boot/dts/thead/th1520.dtsi +0 -0

                         reg = <0>;
                         i-cache-block-size = <64>;

i-cache-size = <65536>;

arch/riscv/boot/dts/thead/th1520.dtsi +3 -0

@@ -41,6 +44,9 @@ c910_1: cpu@1 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                         reg = <1>;
                         i-cache-block-size = <64>;

i-cache-size = <65536>;

arch/riscv/boot/dts/thead/th1520.dtsi +3 -0

@@ -62,6 +68,9 @@ c910_2: cpu@2 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                         reg = <2>;
                         i-cache-block-size = <64>;

i-cache-size = <65536>;

arch/riscv/boot/dts/thead/th1520.dtsi +3 -0

@@ -83,6 +92,9 @@ c910_3: cpu@3 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                         reg = <3>;
                         i-cache-block-size = <64>;

i-cache-size = <65536>;

Jernej Škrabec

maintainer Acked-by on v2 5/6

2023-09-24 19:42 UTC #7 lore raw

Re: [RFC v2 5/6] riscv: dts: allwinner: convert isa detection to new properties

In reply to Conor Dooley

Dne petek, 22. september 2023 ob 10:13:50 CEST je Conor Dooley napisal(a):

Quoted 7 lines

From: Conor Dooley <[email protected]>
Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>

Acked-by Jernej Skrabec <[email protected]>

Best regards,
Jernej

Quoted 19 lines

---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++
 1 file changed, 3 insertions(+)

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +3 -0

index 8275630af977..947e975d2476 100644
@@ -25,6 +25,9 @@ cpu0: cpu@0 {
 			mmu-type = "riscv,sv39";
 			operating-points-v2 = <&opp_table_cpu>;
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			#cooling-cells = <2>;
 
 			cpu0_intc: interrupt-controller {

Conor Dooley

author maintainer

2023-09-25 16:00 UTC #13 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

In reply to Icenowy Zheng

Quoted 12 lines · Icenowy Zheng

Quoted 11 lines · 在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：
From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Quoted 15 lines

arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 26

Quoted 13 lines

arch/riscv/boot/dts/thead/th1520.dtsi +3 -0

index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";

Zfh is supported by T-Head C9xx with float too.

You say xx, so just to be sure: Is it always supported, or only with some config for the IP (I wanna know if I need to look out for it while reviewing other SoCs etc)?
Also, do you have a link to the documentation for it? English is the only relevant language I speak, so if the doc is in Chinese, I'll need some help!

Quoted 1 line

In addition, should X extensions get listed here?

Yes, but someone who cares about documenting these extensions should do it ;)

Thanks,
Conor.

Samuel Holland

maintainer Reviewed-by on v2 2/6

2023-09-25 17:39 UTC #3 lore raw

Re: [RFC v2 2/6] riscv: dts: sifive: convert isa detection to new properties

In reply to Conor Dooley

Quoted 11 lines · Conor Dooley

From: Conor Dooley <[email protected]>
Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++
 2 files changed, 30 insertions(+)

Reviewed-by Samuel Holland <[email protected]>

Icenowy Zheng

2023-09-26 03:16 UTC #14 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

Quoted 31 lines · 在 2023-09-25星期一的 16:59 +0100，Conor Dooley写道：

Quoted 21 lines · Icenowy Zheng
Quoted 20 lines · 在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：
From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/thead/th1520.dtsi +0 -0
index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
Quoted 8 lines
arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 28
Quoted 6 lines
arch/riscv/boot/dts/thead/th1520.dtsi +3 -0
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a",
 "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei",
 "zihpm";
Zfh is supported by T-Head C9xx with float too.

Quoted 4 lines

You say xx, so just to be sure: Is it always supported, or only with some config for the IP (I wanna know if I need to look out for it while
reviewing other SoCs etc)?

I think it's grouped with FD.

Quoted 4 lines

Also, do you have a link to the documentation for it? English is the only relevant language I speak, so if the doc is in Chinese, I'll need
some help!

Sorry, but T-Head's official document [1] is only in Chinese. In addition, in this document half-float is listed as a "T-Head extension", but the encoding matches Zfh. See 15.6 Appendix B-6 Half Float (15.6 附录 B-6 浮点半精度指令术语) .

[1]
https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf

Quoted 6 lines

Quoted 2 lines
In addition, should X extensions get listed here?
Yes, but someone who cares about documenting these extensions should do
it ;)

Well at least a bunch of Xthead's are now documented.

Maybe they will get appended after this patchset get introduced.

By the way, how to deal with the draft V of C9xx?

Quoted 3 lines

Thanks,
Conor.

Conor Dooley

author maintainer

2023-09-26 09:15 UTC #15 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

Quoted 44 lines · Icenowy Zheng

Quoted 31 lines · 在 2023-09-25星期一的 16:59 +0100，Conor Dooley写道：
Quoted 21 lines · Icenowy Zheng
Quoted 20 lines · 在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：
From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/riscv/boot/dts/thead/th1520.dtsi +0 -0
index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                         compatible = "thead,c910", "riscv";
                         device_type = "cpu";
                         riscv,isa = "rv64imafdc";
Quoted 8 lines
arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 28
Quoted 6 lines
arch/riscv/boot/dts/thead/th1520.dtsi +3 -0
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a",
 "f",
 "d", "c", "zicntr", "zicsr",
+                                              "zifencei",
 "zihpm";
Zfh is supported by T-Head C9xx with float too.
Quoted 4 lines
You say xx, so just to be sure: Is it always supported, or only with some config for the IP (I wanna know if I need to look out for it while
reviewing other SoCs etc)?
I think it's grouped with FD.
Quoted 4 lines
Also, do you have a link to the documentation for it? English is the only relevant language I speak, so if the doc is in Chinese, I'll need
some help!

Quoted 4 lines

Sorry, but T-Head's official document [1] is only in Chinese. In addition, in this document half-float is listed as a "T-Head extension", but the encoding matches Zfh. See 15.6 Appendix B-6 Half Float (15.6 附录 B-6 浮点半精度指令术语) .

Hmm, I'm not sure that I want to do this. Since it is only an "I think" and it's not *actually* advertised as being Zfh but apparently has matching encoding, I would rather someone who is capable of understanding that document submitted the patch.

Quoted 11 lines

[1]
https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
Quoted 6 lines
Quoted 2 lines
In addition, should X extensions get listed here?
Yes, but someone who cares about documenting these extensions should do
it ;)
Well at least a bunch of Xthead's are now documented.

I meant documented in the dt-binding, not documented in a pdf on GitHub.

Quoted 3 lines

Maybe they will get appended after this patchset get introduced.
By the way, how to deal with the draft V of C9xx?

Same deal, it'll have to be defined as a vendor extension in the dt-binding.

Cheers,
Conor.

Jisheng Zhang

Reviewed-by on v2 6/6

2023-10-04 12:25 UTC #16 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

Quoted 7 lines · Conor Dooley

From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>

Reviewed-by Jisheng Zhang <[email protected]>

Quoted 51 lines

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/riscv/boot/dts/thead/th1520.dtsi +12 -0

index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -41,6 +44,9 @@ c910_1: cpu@1 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -62,6 +68,9 @@ c910_2: cpu@2 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -83,6 +92,9 @@ c910_3: cpu@3 {
 			compatible = "thead,c910", "riscv";
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+					       "zifencei", "zihpm";
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

Signature · 1 line

2.41.0

Guo Ren

maintainer Acked-by

2023-10-09 01:01 UTC #11 lore raw

Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

In reply to Conor Dooley

Quoted 27 lines · Conor Dooley

Quoted 13 lines · Guo Ren
Quoted 12 lines · Conor Dooley
From: Conor Dooley <[email protected]>
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Signed-off-by Conor Dooley <[email protected]>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
Quoted 11 lines
arch/riscv/boot/dts/thead/th1520.dtsi c910_0: cpu@0 { · line 23
Quoted 9 lines
arch/riscv/boot/dts/thead/th1520.dtsi +1 -0
index ce708183b6f6..723f65487246 100644
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
                        compatible = "thead,c910", "riscv";
                        device_type = "cpu";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
Why not riscv,isa-base = "rv64"? I saw "i" in the riscv,isa-extensions.

Quoted 2 lines

I did it that way as a hedge against things changing in the future. I have little trust in that part of the ISA specifications.

Okay, that's clear enough.

Acked-by Guo Ren <[email protected]>

Signature · 2 lines

Best Regards
 Guo Ren