5.15.134-rc1 review
Subsystems (6)
Greg Kroah-Hartman
maintainercover 5.15.134-rc1 review
This is the start of the stable review cycle for the 5.15.134 release. There are 183 patches in this series, all will be posted as a response to this one. If anyone has any issues with these being applied, please let me know.
Responses should be made by Fri, 06 Oct 2023 17:51:12 +0000. Anything received after that time might be too late.
The whole patch series can be found in one patch at:
https://www.kernel.org/pub/linux/kernel/v5.x/stable-review/patch-5.15.134-rc1.gz
or in the git tree and branch at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git linux-5.15.y
and the diffstat can be found below.
thanks,
greg k-h
-------------
Pseudo-Shortlog of commits:
Greg Kroah-Hartman <[email protected]>
Linux 5.15.134-rc1
Florian Westphal <[email protected]>
netfilter: nf_tables: fix kdoc warnings after gc rework
Jani Nikula <[email protected]>
drm/meson: fix memory leak on ->hpd_notify callback
Greg Ungerer <[email protected]>
fs: binfmt_elf_efpic: fix personality for ELF-FDPIC
Matthias Schiffer <[email protected]>
ata: libata-sata: increase PMP SRST timeout to 10s
Damien Le Moal <[email protected]>
ata: libata-core: Do not register PM operations for SAS ports
Damien Le Moal <[email protected]>
ata: libata-core: Fix port and device removal
Damien Le Moal <[email protected]>
ata: libata-core: Fix ata_port_request_pm() locking
Mika Westerberg <[email protected]>
net: thunderbolt: Fix TCPv6 GSO checksum calculation
Nick Desaulniers <[email protected]>
bpf: Fix BTF_ID symbol generation collision in tools/
Jiri Olsa <[email protected]>
bpf: Fix BTF_ID symbol generation collision
Josef Bacik <[email protected]>
btrfs: properly report 0 avail for very full file systems
Steven Rostedt (Google) <[email protected]>
ring-buffer: Update "shortest_full" in polling
Ben Wolsieffer <[email protected]>
proc: nommu: /proc/<pid>/maps: release mmap read lock
Trond Myklebust <[email protected]>
Revert "SUNRPC dont update timeout value on connection reset"
Jens Axboe <[email protected]>
io_uring/fs: remove sqe->rw_flags checking from LINKAT
Joel Fernandes (Google) <[email protected]>
sched/rt: Fix live lock between select_fallback_rq() and RT push
Liam R. Howlett <[email protected]>
kernel/sched: Modify initial boot task idle setup
Heiner Kallweit <[email protected]>
i2c: i801: unregister tco_pdev in i801_probe() error path
Niklas Cassel <[email protected]>
ata: libata-scsi: ignore reserved bits for REPORT SUPPORTED OPERATION CODES
Kailang Yang <[email protected]>
ALSA: hda: Disable power save for solving pop issue on Lenovo ThinkCentre M70q
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: disallow rule removal from chain binding
Pan Bian <[email protected]>
nilfs2: fix potential use after free in nilfs_gccache_submit_read_data()
Andy Shevchenko <[email protected]>
serial: 8250_port: Check IRQ data before use
Daniel Starke <[email protected]>
Revert "tty: n_gsm: fix UAF in gsm_cleanup_mux"
Ricky WU <[email protected]>
misc: rtsx: Fix some platforms can not boot and move the l1ss judgment to probe
Pu Wen <[email protected]>
x86/srso: Add SRSO mitigation for Hygon processors
Nicolin Chen <[email protected]>
iommu/arm-smmu-v3: Fix soft lockup triggered by arm_smmu_mm_invalidate_range
Vishal Goel <[email protected]>
Smack:- Use overlay inode label in smack_inode_copy_up()
Roberto Sassu <[email protected]>
smack: Retrieve transmuting information in smack_inode_getsecurity()
Roberto Sassu <[email protected]>
smack: Record transmuting in smk_transmuted
Irvin Cote <[email protected]>
nvme-pci: always return an ERR_PTR from nvme_pci_alloc_dev
Gleb Chesnokov <[email protected]>
scsi: qla2xxx: Fix NULL pointer dereference in target mode
Ian Rogers <[email protected]>
perf metric: Return early if no CPU PMU table exists
Andrii Staikov <[email protected]>
i40e: fix potential NULL pointer dereferencing of pf->vf i40e_sync_vsi_filters()
Mika Westerberg <[email protected]>
watchdog: iTCO_wdt: Set NO_REBOOT if the watchdog is not already running
Mika Westerberg <[email protected]>
watchdog: iTCO_wdt: No need to stop the timer in probe
Pratyush Yadav <[email protected]>
nvme-pci: do not set the NUMA node of device if it has none
Christoph Hellwig <[email protected]>
nvme-pci: factor out a nvme_pci_alloc_dev helper
Christoph Hellwig <[email protected]>
nvme-pci: factor the iod mempool creation into a helper
Chengming Zhou <[email protected]>
cgroup: Fix suspicious rcu_dereference_check() usage warning
Chengming Zhou <[email protected]>
sched/cpuacct: Optimize away RCU read lock
Arnaldo Carvalho de Melo <[email protected]>
perf build: Define YYNOMEM as YYNOABORT for bison < 3.81
Thomas Zimmermann <[email protected]>
fbdev/sh7760fb: Depend on FB=y
Johnathan Mantey <[email protected]>
ncsi: Propagate carrier gain/loss events to the NCSI controller
Benjamin Gray <[email protected]>
powerpc/watchpoints: Annotate atomic context in more places
Benjamin Gray <[email protected]>
powerpc/watchpoint: Disable pagefaults when getting user instruction
Benjamin Gray <[email protected]>
powerpc/watchpoints: Disable preemption in thread_change_pc()
Hans Verkuil <[email protected]>
media: vb2: frame_vector.c: replace WARN_ONCE with a comment
Chancel Liu <[email protected]>
ASoC: imx-rpmsg: Set ignore_pmdown_time for dai_link
Stanislav Fomichev <[email protected]>
bpf: Clarify error expectations from bpf_clone_redirect
Shengjiu Wang <[email protected]>
ASoC: fsl: imx-pcm-rpmsg: Add SNDRV_PCM_INFO_BATCH flag
Valentin Caron <[email protected]>
spi: stm32: add a delay before SPI disable
Han Xu <[email protected]>
spi: nxp-fspi: reset the FLSHxCR1 registers
Niklas Cassel <[email protected]>
ata: libata-eh: do not clear ATA_PFLAG_EH_PENDING in ata_eh_reset()
Steve French <[email protected]>
smb3: correct places where ENOTSUPP is used instead of preferred EOPNOTSUPP
Michal Grzedzicki <[email protected]>
scsi: pm80xx: Avoid leaking tags when processing OPC_INB_SET_CONTROLLER_CONFIG command
Michal Grzedzicki <[email protected]>
scsi: pm80xx: Use phy-specific SAS address when sending PHY_START command
David Francis <[email protected]>
drm/amdgpu: Handle null atom context in VBIOS info ioctl
Swapnil Patel <[email protected]>
drm/amd/display: Don't check registers, if using AUX BL control
David Thompson <[email protected]>
platform/mellanox: mlxbf-bootctl: add NET dependency into Kconfig
Steven Rostedt (Google) <[email protected]>
ring-buffer: Do not attempt to read past "commit"
Ricardo B. Marliere <[email protected]>
selftests: fix dependency checker script
Filipe Manana <[email protected]>
btrfs: improve error message after failure to add delayed dir index item
Zheng Yejian <[email protected]>
ring-buffer: Avoid softlockup in ring_buffer_resize()
Zheng Yejian <[email protected]>
selftests/ftrace: Correctly enable event in instance-event.tc
Kiwoong Kim <[email protected]>
scsi: ufs: core: Move __ufshcd_send_uic_cmd() outside host_lock
Javed Hasan <[email protected]>
scsi: qedf: Add synchronization between I/O completions and abort
Helge Deller <[email protected]>
parisc: irq: Make irq_stack_union static to avoid sparse warning
Helge Deller <[email protected]>
parisc: drivers: Fix sparse warning
Helge Deller <[email protected]>
parisc: iosapic.c: Fix sparse warnings
Helge Deller <[email protected]>
parisc: sba: Fix compile warning wrt list of SBA devices
Tobias Schramm <[email protected]>
spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain
Tobias Schramm <[email protected]>
spi: sun6i: reduce DMA RX transfer width to single byte
Sergey Senozhatsky <[email protected]>
dma-debug: don't call __dma_entry_alloc_check_leak() under free_entries_lock
William A. Kennington III <[email protected]>
i2c: npcm7xx: Fix callback completion ordering
Wenhua Lin <[email protected]>
gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip
Nathan Rossi <[email protected]>
soc: imx8m: Enable OCOTP clock for imx8mm before reading registers
Max Filippov <[email protected]>
xtensa: boot/lib: fix function prototypes
Randy Dunlap <[email protected]>
xtensa: boot: don't add include-dirs
Randy Dunlap <[email protected]>
xtensa: iss/network: make functions static
Max Filippov <[email protected]>
xtensa: add default definition for XCHAL_HAVE_DIV32
Christophe JAILLET <[email protected]>
firmware: imx-dsp: Fix an error handling path in imx_dsp_setup_channels()
Dan Carpenter <[email protected]>
power: supply: ucs1002: fix error code in ucs1002_get_property()
Tony Lindgren <[email protected]>
bus: ti-sysc: Fix SYSC_QUIRK_SWSUP_SIDLE_ACT handling for uart wake-up
Tony Lindgren <[email protected]>
ARM: dts: ti: omap: motorola-mapphone: Fix abe_clkctrl warning on boot
Tony Lindgren <[email protected]>
ARM: dts: ti: omap: Fix bandgap thermal cells addressing for omap3/4
Krzysztof Kozlowski <[email protected]>
ARM: dts: omap: correct indentation
Thomas Gleixner <[email protected]>
treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1)
Timo Alho <[email protected]>
clk: tegra: fix error return case for recalc_rate
Adam Ford <[email protected]>
bus: ti-sysc: Fix missing AM35xx SoC matching
Julien Panis <[email protected]>
bus: ti-sysc: Use fsleep() instead of usleep_range() in sysc_reset()
Marek Vasut <[email protected]>
drm/bridge: ti-sn65dsi83: Do not generate HFP/HBP/HSA and EOT packet
Christoph Hellwig <[email protected]>
MIPS: Alchemy: only build mmc support helpers if au1xmmc is enabled
Qu Wenruo <[email protected]>
btrfs: reset destination buffer when read_extent_buffer() gets invalid range
Nilesh Javali <[email protected]>
scsi: qla2xxx: Use raw_smp_processor_id() instead of smp_processor_id()
Shreyas Deodhar <[email protected]>
scsi: qla2xxx: Select qpair depending on which CPU post_cmd() gets called
Werner Fischer <[email protected]>
ata: ahci: Add Elkhart Lake AHCI controller
Mario Limonciello <[email protected]>
ata: ahci: Rename board_ahci_mobile
Paul Menzel <[email protected]>
ata: ahci: Add support for AMD A85 FCH (Hudson D4)
Paul Menzel <[email protected]>
ata: libata: Rename link flag ATA_LFLAG_NO_DB_DELAY
Xiao Liang <[email protected]>
netfilter: nft_exthdr: Fix non-linear header modification
Florian Westphal <[email protected]>
netfilter: exthdr: add support for tcp option removal
Namhyung Kim <[email protected]>
perf build: Update build rule for generated files
Ian Rogers <[email protected]>
perf jevents: Switch build to use jevents.py
Werner Sembach <[email protected]>
Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN
Huacai Chen <[email protected]>
Input: i8042 - rename i8042-x86ia64io.h to i8042-acpipnpio.h
Darrick J. Wong <[email protected]>
xfs: fix xfs_inodegc_stop racing with mod_delayed_work
Darrick J. Wong <[email protected]>
xfs: disable reaping in fscounters scrub
Darrick J. Wong <[email protected]>
xfs: check that per-cpu inodegc workers actually run on that cpu
Darrick J. Wong <[email protected]>
xfs: explicitly specify cpu when forcing inodegc delayed work to run immediately
Dave Chinner <[email protected]>
xfs: introduce xfs_inodegc_push()
Dave Chinner <[email protected]>
xfs: bound maximum wait time for inodegc work
Liang He <[email protected]>
i2c: mux: gpio: Add missing fwnode_handle_put()
Andy Shevchenko <[email protected]>
i2c: mux: gpio: Replace custom acpi_get_local_address()
Xiaoke Wang <[email protected]>
i2c: mux: demux-pinctrl: check the return value of devm_kstrdup()
Christophe JAILLET <[email protected]>
gpio: tb10x: Fix an error handling path in tb10x_gpio_probe()
Sasha Levin <[email protected]>
Fix up backport of 136191703038 ("interconnect: Teach lockdep about icc_bw_lock order")
Muhammad Husaini Zulkifli <[email protected]>
igc: Expose tx-usecs coalesce setting to user
Sebastian Andrzej Siewior <[email protected]>
bnxt_en: Flush XDP for bnxt_poll_nitroa0()'s NAPI
Sebastian Andrzej Siewior <[email protected]>
net: ena: Flush XDP packets on error.
Sebastian Andrzej Siewior <[email protected]>
locking/seqlock: Do the lockdep annotation before locking in do_write_seqcount_begin_nested()
Jozsef Kadlecsik <[email protected]>
netfilter: ipset: Fix race between IPSET_CMD_CREATE and IPSET_CMD_SWAP
Florian Westphal <[email protected]>
netfilter: nf_tables: disable toggling dormant table state more than once
Artem Chernyshev <[email protected]>
net: rds: Fix possible NULL-pointer dereference
Ziyang Xuan <[email protected]>
team: fix null-ptr-deref when team device type is changed
Eric Dumazet <[email protected]>
net: bridge: use DEV_STATS_INC()
Jie Wang <[email protected]>
net: hns3: add 5ms delay before clear firmware reset irq source
Jijie Shao <[email protected]>
net: hns3: fix fail to delete tc flower rules during reset issue
Jian Shen <[email protected]>
net: hns3: only enable unicast promisc when mac table full
Jie Wang <[email protected]>
net: hns3: fix GRE checksum offload issue
Josh Poimboeuf <[email protected]>
x86/srso: Fix SBPB enablement for spec_rstack_overflow=off
Josh Poimboeuf <[email protected]>
x86/srso: Fix srso_show_state() side effect
Stephen Boyd <[email protected]>
platform/x86: intel_scu_ipc: Fail IPC send if still busy
Stephen Boyd <[email protected]>
platform/x86: intel_scu_ipc: Don't override scu in intel_scu_ipc_dev_simple_command()
Stephen Boyd <[email protected]>
platform/x86: intel_scu_ipc: Check status upon timeout in ipc_wait_for_interrupt()
Stephen Boyd <[email protected]>
platform/x86: intel_scu_ipc: Check status after timeout in busy_loop()
Eric Dumazet <[email protected]>
dccp: fix dccp_v4_err()/dccp_v6_err() again
Kajol Jain <[email protected]>
powerpc/perf/hv-24x7: Update domain value check
Kyle Zeng <[email protected]>
ipv4: fix null-deref in ipv4_link_failure
Vinicius Costa Gomes <[email protected]>
igc: Fix infinite initialization loop with early XDP redirect
David Christensen <[email protected]>
ionic: fix 16bit math issue when PAGE_SIZE >= 64KB
Ivan Vecera <[email protected]>
i40e: Fix VF VLAN offloading when port VLAN is configured
Mateusz Palczewski <[email protected]>
i40e: Add VF VLAN pruning
Radoslaw Tyl <[email protected]>
iavf: do not process adminq tasks when __IAVF_IN_REMOVE_TASK is set
Shengjiu Wang <[email protected]>
ASoC: imx-audmix: Fix return error with devm_clk_get()
Sasha Neftin <[email protected]>
net/core: Fix ETH_P_1588 flow dissector
Sabrina Dubroca <[email protected]>
selftests: tls: swap the TX and RX sockets in some tests
Toke Høiland-Jørgensen <[email protected]>
bpf: Avoid deadlock when using queue and stack maps from NMI
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: disallow element removal on anonymous sets
Jerome Brunet <[email protected]>
ASoC: meson: spdifin: start hw on dai probe
Florian Westphal <[email protected]>
netfilter: nf_tables: fix memleak when more than 255 elements expired
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_hash: try later when GC hits EAGAIN on iteration
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_pipapo: stop GC iteration if GC transaction allocation fails
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_pipapo: call nft_trans_gc_queue_sync() in catchall GC
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_rbtree: use read spinlock to avoid datapath contention
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_rbtree: skip sync GC for new elements in this transaction
Florian Westphal <[email protected]>
netfilter: nf_tables: defer gc run if previous batch is still pending
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: use correct lock to protect gc_list
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: GC transaction race with abort path
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: GC transaction race with netns dismantle
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: fix GC transaction races with netns and netlink event exit path
Florian Westphal <[email protected]>
netfilter: nf_tables: don't fail inserts if duplicate has expired
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: remove busy mark and gc batch API
Pablo Neira Ayuso <[email protected]>
netfilter: nft_set_hash: mark set element as dead when deleting from packet path
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: adapt set backend to use GC transaction API
Pablo Neira Ayuso <[email protected]>
netfilter: nf_tables: GC transaction API to avoid race with control plane
Florian Westphal <[email protected]>
netfilter: nf_tables: don't skip expired elements during walk
Steven Rostedt (Google) <[email protected]>
tracing: Have event inject files inc the trace array ref count
Jan Kara <[email protected]>
ext4: do not let fstrim block system suspend
Jan Kara <[email protected]>
ext4: move setting of trimmed bit into ext4_try_to_trim_range()
Kemeng Shi <[email protected]>
ext4: replace the traditional ternary conditional operator with with max()/min()
Lukas Czerner <[email protected]>
ext4: change s_last_trim_minblks type to unsigned long
Lukas Bulwahn <[email protected]>
ext4: scope ret locally in ext4_try_to_trim_range()
Szuying Chen <[email protected]>
ata: libahci: clear pending interrupt status
Hannes Reinecke <[email protected]>
ata: ahci: Drop pointless VPRINTK() calls and convert the remaining ones
Steven Rostedt (Google) <[email protected]>
tracing: Increase trace array ref count on enable and filter files
John Keeping <[email protected]>
tracing: Make trace_marker{,_raw} stream-like
Olga Kornievskaia <[email protected]>
NFSv4.1: fix pnfs MDS=DS session trunking
Olga Kornievskaia <[email protected]>
NFSv4.1: use EXCHGID4_FLAG_USE_PNFS_DS for DS server
Trond Myklebust <[email protected]>
SUNRPC: Mark the cred for revalidation if the server rejects it
Trond Myklebust <[email protected]>
NFS/pNFS: Report EINVAL errors from connect() to the server
Trond Myklebust <[email protected]>
NFS: More fixes for nfs_direct_write_reschedule_io()
Trond Myklebust <[email protected]>
NFS: Use the correct commit info in nfs_join_page_group()
-------------
Diffstat:
Makefile | 4 +-
arch/arm/boot/dts/am33xx.dtsi | 5 +-
arch/arm/boot/dts/am3517.dtsi | 5 +-
arch/arm/boot/dts/am4372.dtsi | 5 +-
arch/arm/boot/dts/artpec6-devboard.dts | 9 +-
arch/arm/boot/dts/dm814x.dtsi | 6 +-
arch/arm/boot/dts/dm816x.dtsi | 6 +-
arch/arm/boot/dts/dra62x.dtsi | 6 +-
arch/arm/boot/dts/dra7-dspeve-thermal.dtsi | 5 +-
arch/arm/boot/dts/dra7-iva-thermal.dtsi | 5 +-
arch/arm/boot/dts/imx6q-gk802.dts | 9 +-
arch/arm/boot/dts/motorola-mapphone-common.dtsi | 4 +-
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi | 6 +-
arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 6 +-
arch/arm/boot/dts/omap2.dtsi | 5 +-
arch/arm/boot/dts/omap2420.dtsi | 5 +-
arch/arm/boot/dts/omap2430.dtsi | 5 +-
arch/arm/boot/dts/omap3-cm-t3517.dts | 12 +-
arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 8 +-
arch/arm/boot/dts/omap3-gta04.dtsi | 6 +-
arch/arm/boot/dts/omap3-ldp.dts | 2 +-
arch/arm/boot/dts/omap3-n900.dts | 38 +-
arch/arm/boot/dts/omap3-zoom3.dts | 44 +--
arch/arm/boot/dts/omap3.dtsi | 5 +-
arch/arm/boot/dts/omap34xx.dtsi | 5 +-
arch/arm/boot/dts/omap36xx.dtsi | 5 +-
arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 34 +-
arch/arm/boot/dts/omap443x.dtsi | 6 +-
arch/arm/boot/dts/omap4460.dtsi | 6 +-
arch/arm/boot/dts/omap5-cm-t54.dts | 56 +--
arch/arm/boot/dts/omap5-core-thermal.dtsi | 5 +-
arch/arm/boot/dts/omap5-gpu-thermal.dtsi | 5 +-
arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 5 +-
.../dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 9 +-
.../boot/dts/orion5x-maxtor-shared-storage-2.dts | 5 +-
arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 9 +-
arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 9 +-
arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 9 +-
arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 9 +-
arch/arm/boot/dts/orion5x.dtsi | 9 +-
arch/arm/include/asm/hardware/cache-aurora-l2.h | 5 +-
arch/arm/include/asm/hardware/cache-feroceon-l2.h | 6 +-
arch/arm/include/asm/hardware/cache-tauros2.h | 5 +-
arch/arm/mach-davinci/board-da830-evm.c | 6 +-
arch/arm/mach-davinci/board-da850-evm.c | 6 +-
arch/arm/mach-davinci/board-dm355-evm.c | 6 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 5 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 6 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 7 +-
arch/arm/mach-davinci/board-mityomapl138.c | 5 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 5 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 5 +-
arch/arm/mach-davinci/common.c | 6 +-
arch/arm/mach-davinci/cpuidle.h | 5 +-
arch/arm/mach-davinci/da830.c | 6 +-
arch/arm/mach-davinci/da850.c | 6 +-
arch/arm/mach-davinci/dm355.c | 6 +-
arch/arm/mach-davinci/dm644x.c | 6 +-
arch/arm/mach-davinci/dm646x.c | 6 +-
arch/arm/mach-davinci/include/mach/common.h | 6 +-
arch/arm/mach-davinci/include/mach/cputype.h | 6 +-
arch/arm/mach-davinci/include/mach/da8xx.h | 6 +-
arch/arm/mach-davinci/include/mach/hardware.h | 6 +-
arch/arm/mach-davinci/include/mach/serial.h | 6 +-
arch/arm/mach-davinci/mux.c | 6 +-
arch/arm/mach-davinci/mux.h | 6 +-
arch/arm/mach-davinci/pm_domain.c | 5 +-
arch/arm/mach-dove/bridge-regs.h | 9 +-
arch/arm/mach-dove/cm-a510.c | 5 +-
arch/arm/mach-dove/common.c | 5 +-
arch/arm/mach-dove/common.h | 5 +-
arch/arm/mach-dove/dove-db-setup.c | 5 +-
arch/arm/mach-dove/dove.h | 9 +-
arch/arm/mach-dove/irq.c | 5 +-
arch/arm/mach-dove/irqs.h | 9 +-
arch/arm/mach-dove/mpp.c | 5 +-
arch/arm/mach-dove/pcie.c | 5 +-
arch/arm/mach-dove/pm.h | 6 +-
arch/arm/mach-lpc18xx/board-dt.c | 5 +-
arch/arm/mach-lpc32xx/pm.c | 6 +-
arch/arm/mach-lpc32xx/suspend.S | 6 +-
arch/arm/mach-mv78xx0/bridge-regs.h | 6 +-
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 5 +-
arch/arm/mach-mv78xx0/common.c | 5 +-
arch/arm/mach-mv78xx0/common.h | 5 +-
arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 5 +-
arch/arm/mach-mv78xx0/irq.c | 5 +-
arch/arm/mach-mv78xx0/irqs.h | 9 +-
arch/arm/mach-mv78xx0/mpp.c | 5 +-
arch/arm/mach-mv78xx0/mpp.h | 6 +-
arch/arm/mach-mv78xx0/mv78xx0.h | 5 +-
arch/arm/mach-mv78xx0/pcie.c | 5 +-
arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 5 +-
arch/arm/mach-mvebu/armada-370-xp.h | 5 +-
arch/arm/mach-mvebu/board-v7.c | 5 +-
arch/arm/mach-mvebu/coherency.c | 5 +-
arch/arm/mach-mvebu/coherency.h | 6 +-
arch/arm/mach-mvebu/coherency_ll.S | 5 +-
arch/arm/mach-mvebu/common.h | 5 +-
arch/arm/mach-mvebu/cpu-reset.c | 5 +-
arch/arm/mach-mvebu/dove.c | 5 +-
arch/arm/mach-mvebu/headsmp-a9.S | 5 +-
arch/arm/mach-mvebu/headsmp.S | 5 +-
arch/arm/mach-mvebu/kirkwood.c | 5 +-
arch/arm/mach-mvebu/kirkwood.h | 5 +-
arch/arm/mach-mvebu/mvebu-soc-id.c | 5 +-
arch/arm/mach-mvebu/mvebu-soc-id.h | 5 +-
arch/arm/mach-mvebu/platsmp-a9.c | 5 +-
arch/arm/mach-mvebu/platsmp.c | 5 +-
arch/arm/mach-mvebu/pm-board.c | 5 +-
arch/arm/mach-mvebu/pm.c | 5 +-
arch/arm/mach-mvebu/pmsu.c | 5 +-
arch/arm/mach-mvebu/pmsu.h | 5 +-
arch/arm/mach-mvebu/pmsu_ll.S | 5 +-
arch/arm/mach-mvebu/system-controller.c | 5 +-
arch/arm/mach-omap1/include/mach/mtd-xip.h | 6 +-
arch/arm/mach-omap1/pm_bus.c | 6 +-
arch/arm/mach-omap2/prcm43xx.h | 5 +-
arch/arm/mach-omap2/vc.c | 6 +-
arch/arm/mach-orion5x/board-d2net.c | 5 +-
arch/arm/mach-orion5x/board-dt.c | 5 +-
arch/arm/mach-orion5x/board-rd88f5182.c | 5 +-
arch/arm/mach-orion5x/bridge-regs.h | 9 +-
arch/arm/mach-orion5x/common.c | 5 +-
arch/arm/mach-orion5x/db88f5281-setup.c | 5 +-
arch/arm/mach-orion5x/irq.c | 5 +-
arch/arm/mach-orion5x/irqs.h | 5 +-
arch/arm/mach-orion5x/kurobox_pro-setup.c | 5 +-
arch/arm/mach-orion5x/ls_hgl-setup.c | 5 +-
arch/arm/mach-orion5x/mpp.c | 5 +-
arch/arm/mach-orion5x/net2big-setup.c | 6 +-
arch/arm/mach-orion5x/orion5x.h | 5 +-
arch/arm/mach-orion5x/pci.c | 5 +-
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 5 +-
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 5 +-
arch/arm/mach-orion5x/rd88f5182-setup.c | 5 +-
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 5 +-
arch/arm/mach-orion5x/ts78xx-setup.c | 5 +-
arch/arm/mach-orion5x/wnr854t-setup.c | 9 +-
arch/arm/mach-orion5x/wrt350n-v2-setup.c | 9 +-
arch/arm/mach-pxa/eseries.c | 7 +-
arch/arm/mach-pxa/standby.S | 6 +-
arch/arm/mach-spear/generic.h | 5 +-
arch/arm/mach-spear/include/mach/misc_regs.h | 5 +-
arch/arm/mach-spear/include/mach/spear.h | 5 +-
arch/arm/mach-spear/pl080.c | 5 +-
arch/arm/mach-spear/pl080.h | 5 +-
arch/arm/mach-spear/restart.c | 5 +-
arch/arm/mach-spear/spear1310.c | 5 +-
arch/arm/mach-spear/spear1340.c | 5 +-
arch/arm/mach-spear/spear13xx.c | 5 +-
arch/arm/mach-spear/spear300.c | 5 +-
arch/arm/mach-spear/spear310.c | 5 +-
arch/arm/mach-spear/spear320.c | 5 +-
arch/arm/mach-spear/spear3xx.c | 5 +-
arch/arm/mach-spear/spear6xx.c | 5 +-
arch/arm/mach-spear/time.c | 5 +-
arch/arm/mm/cache-feroceon-l2.c | 5 +-
arch/arm/mm/cache-tauros2.c | 5 +-
arch/mips/alchemy/devboards/db1000.c | 4 +
arch/mips/alchemy/devboards/db1200.c | 6 +
arch/mips/alchemy/devboards/db1300.c | 4 +
arch/parisc/include/asm/ropes.h | 3 +
arch/parisc/kernel/drivers.c | 2 +-
arch/parisc/kernel/irq.c | 2 +-
arch/powerpc/kernel/hw_breakpoint.c | 16 +-
arch/powerpc/kernel/hw_breakpoint_constraints.c | 7 +-
arch/powerpc/perf/hv-24x7.c | 2 +-
arch/x86/kernel/cpu/bugs.c | 4 +-
arch/x86/kernel/cpu/common.c | 2 +-
arch/xtensa/boot/Makefile | 3 +-
arch/xtensa/boot/lib/zmem.c | 5 +-
arch/xtensa/include/asm/core.h | 4 +
arch/xtensa/platforms/iss/network.c | 4 +-
drivers/ata/ahci.c | 111 +++---
drivers/ata/ahci_brcm.c | 2 +-
drivers/ata/ahci_xgene.c | 4 -
drivers/ata/libahci.c | 49 +--
drivers/ata/libata-core.c | 47 ++-
drivers/ata/libata-eh.c | 13 +-
drivers/ata/libata-sata.c | 2 +-
drivers/ata/libata-scsi.c | 2 +-
drivers/ata/libata-transport.c | 9 +-
drivers/ata/libata.h | 2 +
drivers/bus/ti-sysc.c | 31 +-
drivers/char/agp/parisc-agp.c | 2 -
drivers/clk/tegra/clk-bpmp.c | 2 +-
drivers/firmware/imx/imx-dsp.c | 1 +
drivers/gpio/gpio-pmic-eic-sprd.c | 1 +
drivers/gpio/gpio-tb10x.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 17 +-
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +-
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 4 +-
drivers/gpu/drm/meson/meson_encoder_hdmi.c | 2 +
drivers/i2c/busses/i2c-i801.c | 1 +
drivers/i2c/busses/i2c-npcm7xx.c | 17 +-
drivers/i2c/muxes/i2c-demux-pinctrl.c | 4 +
drivers/i2c/muxes/i2c-mux-gpio.c | 47 +--
.../serio/{i8042-x86ia64io.h => i8042-acpipnpio.h} | 13 +-
drivers/input/serio/i8042.h | 2 +-
drivers/interconnect/core.c | 1 +
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 27 +-
drivers/media/common/videobuf2/frame_vector.c | 6 +-
drivers/misc/cardreader/rts5227.c | 55 +--
drivers/misc/cardreader/rts5228.c | 57 +--
drivers/misc/cardreader/rts5249.c | 56 +--
drivers/misc/cardreader/rts5260.c | 43 +--
drivers/misc/cardreader/rts5261.c | 52 +--
drivers/misc/cardreader/rtsx_pcr.c | 51 ++-
drivers/net/ethernet/amazon/ena/ena_netdev.c | 3 +
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 5 +
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 9 +
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 13 +-
drivers/net/ethernet/intel/i40e/i40e.h | 1 +
drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 9 +
drivers/net/ethernet/intel/i40e/i40e_main.c | 138 ++++++-
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 16 +-
drivers/net/ethernet/intel/iavf/iavf_main.c | 3 +-
drivers/net/ethernet/intel/igc/igc_ethtool.c | 31 +-
drivers/net/ethernet/intel/igc/igc_main.c | 2 +-
drivers/net/ethernet/pensando/ionic/ionic_dev.h | 1 +
drivers/net/ethernet/pensando/ionic/ionic_txrx.c | 10 +-
drivers/net/team/team.c | 10 +-
drivers/net/thunderbolt.c | 3 +-
drivers/nvme/host/pci.c | 121 ++++---
drivers/parisc/iosapic.c | 4 +-
drivers/parisc/iosapic_private.h | 4 +-
drivers/platform/mellanox/Kconfig | 1 +
drivers/platform/x86/intel_scu_ipc.c | 66 ++--
drivers/power/supply/ucs1002_power.c | 3 +-
drivers/scsi/pm8001/pm8001_hwi.c | 2 +-
drivers/scsi/pm8001/pm80xx_hwi.c | 4 +-
drivers/scsi/qedf/qedf_io.c | 10 +-
drivers/scsi/qedf/qedf_main.c | 7 +-
drivers/scsi/qla2xxx/qla_def.h | 3 +
drivers/scsi/qla2xxx/qla_init.c | 5 +-
drivers/scsi/qla2xxx/qla_inline.h | 58 +++
drivers/scsi/qla2xxx/qla_isr.c | 12 +-
drivers/scsi/qla2xxx/qla_nvme.c | 4 +
drivers/scsi/qla2xxx/qla_os.c | 6 +
drivers/scsi/qla2xxx/qla_target.c | 3 +-
drivers/scsi/qla2xxx/tcm_qla2xxx.c | 4 +-
drivers/scsi/ufs/ufshcd.c | 6 +-
drivers/soc/imx/soc-imx8m.c | 10 +
drivers/spi/spi-nxp-fspi.c | 7 +
drivers/spi/spi-stm32.c | 8 +
drivers/spi/spi-sun6i.c | 31 +-
drivers/tty/n_gsm.c | 4 +-
drivers/tty/serial/8250/8250_port.c | 5 +-
drivers/video/fbdev/Kconfig | 2 +-
drivers/watchdog/iTCO_wdt.c | 26 +-
fs/binfmt_elf_fdpic.c | 5 +-
fs/btrfs/delayed-inode.c | 7 +-
fs/btrfs/extent_io.c | 8 +-
fs/btrfs/super.c | 2 +-
fs/cifs/inode.c | 2 +-
fs/cifs/smb2ops.c | 6 +-
fs/ext4/ext4.h | 2 +-
fs/ext4/mballoc.c | 67 ++--
fs/nfs/direct.c | 25 +-
fs/nfs/flexfilelayout/flexfilelayout.c | 1 +
fs/nfs/nfs4client.c | 9 +-
fs/nfs/nfs4proc.c | 4 +
fs/nfs/write.c | 23 +-
fs/nilfs2/gcinode.c | 6 +-
fs/proc/task_nommu.c | 27 +-
fs/xfs/scrub/common.c | 25 --
fs/xfs/scrub/common.h | 2 -
fs/xfs/scrub/fscounters.c | 13 +-
fs/xfs/scrub/scrub.c | 2 -
fs/xfs/scrub/scrub.h | 1 -
fs/xfs/xfs_icache.c | 92 +++--
fs/xfs/xfs_icache.h | 1 +
fs/xfs/xfs_mount.h | 5 +-
fs/xfs/xfs_qm_syscalls.c | 9 +-
fs/xfs/xfs_super.c | 12 +-
fs/xfs/xfs_trace.h | 1 +
include/linux/btf_ids.h | 2 +-
include/linux/cgroup.h | 3 +-
include/linux/if_team.h | 2 +
include/linux/libata.h | 4 +-
include/linux/nfs_fs_sb.h | 1 +
include/linux/nfs_page.h | 4 +-
include/linux/seqlock.h | 2 +-
include/net/netfilter/nf_tables.h | 127 +++----
include/uapi/linux/bpf.h | 4 +-
io_uring/io_uring.c | 2 +-
kernel/bpf/queue_stack_maps.c | 21 +-
kernel/dma/debug.c | 20 +-
kernel/sched/core.c | 2 +-
kernel/sched/cpuacct.c | 4 +-
kernel/sched/cpupri.c | 1 +
kernel/sched/idle.c | 1 +
kernel/trace/ring_buffer.c | 10 +
kernel/trace/trace.c | 45 ++-
kernel/trace/trace.h | 2 +
kernel/trace/trace_events.c | 6 +-
kernel/trace/trace_events_inject.c | 3 +-
net/bridge/br_forward.c | 4 +-
net/bridge/br_input.c | 4 +-
net/core/flow_dissector.c | 2 +-
net/dccp/ipv4.c | 9 +-
net/dccp/ipv6.c | 9 +-
net/ipv4/route.c | 4 +-
net/ncsi/ncsi-aen.c | 5 +
net/netfilter/ipset/ip_set_core.c | 12 +-
net/netfilter/nf_tables_api.c | 400 +++++++++++++++++----
net/netfilter/nft_exthdr.c | 110 +++++-
net/netfilter/nft_set_hash.c | 87 +++--
net/netfilter/nft_set_pipapo.c | 71 ++--
net/netfilter/nft_set_rbtree.c | 161 +++++----
net/rds/rdma_transport.c | 12 +-
net/sunrpc/clnt.c | 15 +-
security/smack/smack.h | 1 +
security/smack/smack_lsm.c | 65 +++-
sound/pci/hda/hda_intel.c | 1 +
sound/soc/fsl/imx-audmix.c | 2 +-
sound/soc/fsl/imx-pcm-rpmsg.c | 1 +
sound/soc/fsl/imx-rpmsg.c | 8 +
sound/soc/meson/axg-spdifin.c | 49 +--
tools/build/Makefile.build | 10 +
tools/include/linux/btf_ids.h | 2 +-
tools/include/uapi/linux/bpf.h | 4 +-
tools/perf/Makefile.config | 19 +
tools/perf/Makefile.perf | 1 +
tools/perf/pmu-events/Build | 19 +-
tools/perf/pmu-events/empty-pmu-events.c | 158 ++++++++
tools/perf/util/Build | 6 +
tools/perf/util/metricgroup.c | 3 +
.../ftrace/test.d/instances/instance-event.tc | 2 +-
tools/testing/selftests/kselftest_deps.sh | 77 +++-
tools/testing/selftests/net/tls.c | 8 +-
332 files changed, 2602 insertions(+), 1896 deletions(-)Greg Kroah-Hartman
maintainerPATCH 1/183 NFS: Use the correct commit info in nfs_join_page_group()
5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Trond Myklebust <[email protected]>
[ Upstream commit b193a78ddb5ee7dba074d3f28dc050069ba083c0 ]
Ensure that nfs_clear_request_commit() updates the correct counters when it removes them from the commit list.
--- fs/nfs/direct.c | 8 +++++--- fs/nfs/write.c | 23 ++++++++++++----------- include/linux/nfs_page.h | 4 +++- 3 files changed, 20 insertions(+), 15 deletions(-)
fs/nfs/direct.c +5 -3
@@ -525,7 +525,9 @@ static void nfs_direct_add_page_head(struct list_head *list,kref_get (&head->wb_kref); } -static void nfs_direct_join_group (struct list_head *list,struct inode *inode) +static void nfs_direct_join_group (struct list_head *list, +struct nfs_commit_info *cinfo, +struct inode *inode) {struct nfs_page *req, *subreq;
@@ -547,7 +549,7 @@ static void nfs_direct_join_group(struct list_head *list, struct inode *inode)nfs_release_request (subreq); } }while ((subreq = subreq->wb_this_page) != req); -nfs_join_page_group (req, inode); +nfs_join_page_group (req, cinfo, inode); } }
@@ -573,7 +575,7 @@ static void nfs_direct_write_reschedule(struct nfs_direct_req *dreq)nfs_init_cinfo_from_dreq (&cinfo, dreq);nfs_direct_write_scan_commit_list (dreq->inode, &reqs, &cinfo); -nfs_direct_join_group (&reqs, dreq->inode); +nfs_direct_join_group (&reqs, &cinfo, dreq->inode); dreq->count =0 ; dreq->max_count =0 ;
fs/nfs/write.c +12 -11
@@ -58,7 +58,8 @@ static const struct nfs_pgio_completion_ops nfs_async_write_completion_ops;static const struct nfs_commit_completion_ops nfs_commit_completion_ops;static const struct nfs_rw_ops nfs_rw_write_ops;static void nfs_inode_remove_request (struct nfs_page *req); -static void nfs_clear_request_commit (struct nfs_page *req); +static void nfs_clear_request_commit (struct nfs_commit_info *cinfo, +struct nfs_page *req);static void nfs_init_cinfo_from_inode (struct nfs_commit_info *cinfo,struct inode *inode); static struct nfs_page *
@@ -500,8 +501,8 @@ nfs_destroy_unlinked_subrequests(struct nfs_page *destroy_list,* the (former) group. All subrequests are removed from any write or commit * lists, unlinked from the group and destroyed. */ -void -nfs_join_page_group (struct nfs_page *head,struct inode *inode) +void nfs_join_page_group (struct nfs_page *head,struct nfs_commit_info *cinfo, +struct inode *inode) {struct nfs_page *subreq;struct nfs_page *destroy_list =NULL ;
@@ -531,7 +532,7 @@ nfs_join_page_group(struct nfs_page *head, struct inode *inode)* Commit list removal accounting is done after locks are dropped */ subreq = head;do { -nfs_clear_request_commit (subreq); +nfs_clear_request_commit (cinfo, subreq); subreq = subreq->wb_this_page; }while (subreq != head);
@@ -565,8 +566,10 @@ nfs_lock_and_join_requests(struct page *page) {struct inode *inode =page_file_mapping (page)->host;struct nfs_page *head; +struct nfs_commit_info cinfo;int ret; +nfs_init_cinfo_from_inode (&cinfo, inode);/* * A reference is taken only on the head request which acts as a * reference to the whole page group - the group will not be destroyed
@@ -583,7 +586,7 @@ nfs_lock_and_join_requests(struct page *page)return ERR_PTR (ret); } -nfs_join_page_group (head, inode); +nfs_join_page_group (head, &cinfo, inode);return head; }
@@ -945,18 +948,16 @@ nfs_clear_page_commit(struct page *page) }/* Called holding the request lock on @req */ -static void -nfs_clear_request_commit (struct nfs_page *req) +static void nfs_clear_request_commit (struct nfs_commit_info *cinfo, +struct nfs_page *req) {if (test_bit (PG_CLEAN , &req->wb_flags)) {struct nfs_open_context *ctx =nfs_req_openctx (req);struct inode *inode =d_inode (ctx->dentry); -struct nfs_commit_info cinfo; -nfs_init_cinfo_from_inode (&cinfo, inode);mutex_lock (&NFS_I (inode)->commit_mutex); -if (!pnfs_clear_request_commit (req, &cinfo)) { -nfs_request_remove_commit_list (req, &cinfo); +if (!pnfs_clear_request_commit (req, cinfo)) { +nfs_request_remove_commit_list (req, cinfo); }mutex_unlock (&NFS_I (inode)->commit_mutex);nfs_clear_page_commit (req->wb_page);
include/linux/nfs_page.h +3 -1
@@ -145,7 +145,9 @@ extern void nfs_unlock_request(struct nfs_page *req);extern void nfs_unlock_and_release_request (struct nfs_page *);extern struct nfs_page *nfs_page_group_lock_head (struct nfs_page *req);extern int nfs_page_group_lock_subrequests (struct nfs_page *head); -extern void nfs_join_page_group (struct nfs_page *head,struct inode *inode); +extern void nfs_join_page_group (struct nfs_page *head, +struct nfs_commit_info *cinfo, +struct inode *inode);extern int nfs_page_group_lock (struct nfs_page *);extern void nfs_page_group_unlock (struct nfs_page *);extern bool nfs_page_group_sync_on_bit (struct nfs_page *,unsigned int );
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 2/183 NFS: More fixes for nfs_direct_write_reschedule_io()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Trond Myklebust <[email protected]>
[ Upstream commit b11243f720ee5f9376861099019c8542969b6318 ]
Ensure that all requests are put back onto the commit list so that they can be rescheduled.
--- fs/nfs/direct.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
fs/nfs/direct.c +11 -6
@@ -786,16 +786,21 @@ static void nfs_write_sync_pgio_error(struct list_head *head, int error)static void nfs_direct_write_reschedule_io (struct nfs_pgio_header *hdr) {struct nfs_direct_req *dreq = hdr->dreq; +struct nfs_page *req; +struct nfs_commit_info cinfo; +nfs_init_cinfo_from_dreq (&cinfo, dreq);spin_lock (&dreq->lock); -if (dreq->error ==0 ) { +if (dreq->error ==0 ) dreq->flags =NFS_ODIRECT_RESCHED_WRITES ; -/* fake unstable write to let common nfs resend pages */ - hdr->verf.committed =NFS_UNSTABLE ; - hdr->good_bytes = hdr->args.offset + hdr->args.count - - hdr->io_start; - } +set_bit (NFS_IOHDR_REDO , &hdr->flags);spin_unlock (&dreq->lock); +while (!list_empty (&hdr->pages)) { + req =nfs_list_entry (hdr->pages.next); +nfs_list_remove_request (req); +nfs_unlock_request (req); +nfs_mark_request_commit (req,NULL , &cinfo,0 ); + } }static const struct nfs_pgio_completion_ops nfs_direct_write_completion_ops = {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 3/183 NFS/pNFS: Report EINVAL errors from connect() to the server
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Trond Myklebust <[email protected]>
[ Upstream commit dd7d7ee3ba2a70d12d02defb478790cf57d5b87b ]
With IPv6, connect() can occasionally return EINVAL if a route is unavailable. If this happens during I/O to a data server, we want to report it using LAYOUTERROR as an inability to connect.
--- fs/nfs/flexfilelayout/flexfilelayout.c | 1 + 1 file changed, 1 insertion(+)
fs/nfs/flexfilelayout/flexfilelayout.c +1 -0
@@ -1238,6 +1238,7 @@ static void ff_layout_io_track_ds_error(struct pnfs_layout_segment *lseg,case -EPFNOSUPPORT :case -EPROTONOSUPPORT :case -EOPNOTSUPP : +case -EINVAL :case -ECONNREFUSED :case -ECONNRESET :case -EHOSTDOWN :
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 4/183 SUNRPC: Mark the cred for revalidation if the server rejects it
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Trond Myklebust <[email protected]>
[ Upstream commit 611fa42dfa9d2f3918ac5f4dd5705dfad81b323d ]
If the server rejects the credential as being stale, or bad, then we should mark it for revalidation before retransmitting.
--- net/sunrpc/clnt.c | 1 + 1 file changed, 1 insertion(+)
net/sunrpc/clnt.c +1 -0
@@ -2668,6 +2668,7 @@ rpc_decode_header(struct rpc_task *task, struct xdr_stream *xdr)case rpc_autherr_rejectedverf:case rpcsec_gsserr_credproblem:case rpcsec_gsserr_ctxproblem: +rpcauth_invalcred (task);if (!task->tk_cred_retry)break ; task->tk_cred_retry--;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 5/183 NFSv4.1: use EXCHGID4_FLAG_USE_PNFS_DS for DS server
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Olga Kornievskaia <[email protected]>
[ Upstream commit 51d674a5e4889f1c8e223ac131cf218e1631e423 ]
After receiving the location(s) of the DS server(s) in the GETDEVINCEINFO, create the request for the clientid to such server and indicate that the client is connecting to a DS.
Stable-dep-of: 806a3bc421a1 ("NFSv4.1: fix pnfs MDS=DS session trunking")
--- fs/nfs/nfs4client.c | 3 +++ fs/nfs/nfs4proc.c | 4 ++++ 2 files changed, 7 insertions(+)
fs/nfs/nfs4client.c +3 -0
@@ -231,6 +231,8 @@ struct nfs_client *nfs4_alloc_client(const struct nfs_client_initdata *cl_init)__set_bit (NFS_CS_DISCRTRY , &clp->cl_flags);__set_bit (NFS_CS_NO_RETRANS_TIMEOUT , &clp->cl_flags); +if (test_bit (NFS_CS_DS , &cl_init->init_flags)) +__set_bit (NFS_CS_DS , &clp->cl_flags);/* * Set up the connection to the server before we add add to the * global list.
@@ -993,6 +995,7 @@ struct nfs_client *nfs4_set_ds_client(struct nfs_server *mds_srv,if (mds_srv->flags &NFS_MOUNT_NORESVPORT )__set_bit (NFS_CS_NORESVPORT , &cl_init.init_flags); +__set_bit (NFS_CS_DS , &cl_init.init_flags);/* * Set an authflavor equual to the MDS value. Use the MDS nfs_client * cl_ipaddr so as to use the same EXCHANGE_ID co_ownerid as the MDS
fs/nfs/nfs4proc.c +4 -0
@@ -8715,6 +8715,8 @@ nfs4_run_exchange_id(struct nfs_client *clp, const struct cred *cred,#ifdef CONFIG_NFS_V4_1_MIGRATION calldata->args.flags |=EXCHGID4_FLAG_SUPP_MOVED_MIGR ;#endif +if (test_bit (NFS_CS_DS , &clp->cl_flags)) + calldata->args.flags |=EXCHGID4_FLAG_USE_PNFS_DS ; msg.rpc_argp = &calldata->args; msg.rpc_resp = &calldata->res; task_setup_data.callback_data = calldata;
@@ -8792,6 +8794,8 @@ static int _nfs4_proc_exchange_id(struct nfs_client *clp, const struct cred *cre/* Save the EXCHANGE_ID verifier session trunk tests */ memcpy (clp->cl_confirm.data, argp->verifier.data,sizeof (clp->cl_confirm.data)); +if (resp->flags &EXCHGID4_FLAG_USE_PNFS_DS ) +set_bit (NFS_CS_DS , &clp->cl_flags); out:trace_nfs4_exchange_id (clp, status);rpc_put_task (task);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 6/183 NFSv4.1: fix pnfs MDS=DS session trunking
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Olga Kornievskaia <[email protected]>
[ Upstream commit 806a3bc421a115fbb287c1efce63a48c54ee804b ]
Currently, when GETDEVICEINFO returns multiple locations where each is a different IP but the server's identity is same as MDS, then nfs4_set_ds_client() finds the existing nfs_client structure which has the MDS's max_connect value (and if it's 1), then the 1st IP on the DS's list will get dropped due to MDS trunking rules. Other IPs would be added as they fall under the pnfs trunking rules.
For the list of IPs the 1st goes thru calling nfs4_set_ds_client() which will eventually call nfs4_add_trunk() and call into rpc_clnt_test_and_add_xprt() which has the check for MDS trunking. The other IPs (after the 1st one), would call rpc_clnt_add_xprt() which doesn't go thru that check.
nfs4_add_trunk() is called when MDS trunking is happening and it needs to enforce the usage of max_connect mount option of the 1st mount. However, this shouldn't be applied to pnfs flow.
Instead, this patch proposed to treat MDS=DS as DS trunking and make sure that MDS's max_connect limit does not apply to the 1st IP returned in the GETDEVICEINFO list. It does so by marking the newly created client with a new flag NFS_CS_PNFS which then used to pass max_connect value to use into the rpc_clnt_test_and_add_xprt() instead of the existing rpc client's max_connect value set by the MDS connection.
For example, mount was done without max_connect value set so MDS's rpc client has cl_max_connect=1. Upon calling into rpc_clnt_test_and_add_xprt() and using rpc client's value, the caller passes in max_connect value which is previously been set in the pnfs path (as a part of handling GETDEVICEINFO list of IPs) in nfs4_set_ds_client().
However, when NFS_CS_PNFS flag is not set and we know we are doing MDS trunking, comparing a new IP of the same server, we then set the max_connect value to the existing MDS's value and pass that into rpc_clnt_test_and_add_xprt().
--- fs/nfs/nfs4client.c | 6 +++++- include/linux/nfs_fs_sb.h | 1 + net/sunrpc/clnt.c | 11 +++++++---- 3 files changed, 13 insertions(+), 5 deletions(-)
fs/nfs/nfs4client.c +5 -1
@@ -416,6 +416,8 @@ static void nfs4_add_trunk(struct nfs_client *clp, struct nfs_client *old) .net = old->cl_net, .servername = old->cl_hostname, }; +int max_connect =test_bit (NFS_CS_PNFS , &clp->cl_flags) ? + clp->cl_max_connect : old->cl_max_connect;if (clp->cl_proto != old->cl_proto)return ;
@@ -429,7 +431,7 @@ static void nfs4_add_trunk(struct nfs_client *clp, struct nfs_client *old) xprt_args.addrlen = clp_salen;rpc_clnt_add_xprt (old->cl_rpcclient, &xprt_args, - rpc_clnt_test_and_add_xprt,NULL ); + rpc_clnt_test_and_add_xprt, &max_connect); }/**
@@ -996,6 +998,8 @@ struct nfs_client *nfs4_set_ds_client(struct nfs_server *mds_srv,__set_bit (NFS_CS_NORESVPORT , &cl_init.init_flags);__set_bit (NFS_CS_DS , &cl_init.init_flags); +__set_bit (NFS_CS_PNFS , &cl_init.init_flags); + cl_init.max_connect =NFS_MAX_TRANSPORTS ;/* * Set an authflavor equual to the MDS value. Use the MDS nfs_client * cl_ipaddr so as to use the same EXCHANGE_ID co_ownerid as the MDS
include/linux/nfs_fs_sb.h +1 -0
@@ -48,6 +48,7 @@ struct nfs_client {#define NFS_CS_NOPING 6/* - don't ping on connect */ #define NFS_CS_DS 7/* - Server is a DS */ #define NFS_CS_REUSEPORT 8/* - reuse src port on reconnect */ +#define NFS_CS_PNFS 9/* - Server used for pnfs */ struct sockaddr_storage cl_addr;/* server identifier */ size_t cl_addrlen;char * cl_hostname;/* hostname of server */
net/sunrpc/clnt.c +7 -4
@@ -2822,19 +2822,22 @@ static const struct rpc_call_ops rpc_cb_add_xprt_call_ops = {* @clnt: pointer to struct rpc_clnt * @xps: pointer to struct rpc_xprt_switch, * @xprt: pointer struct rpc_xprt -* @dummy: unused +* @in_max_connect: pointer to the max_connect value for the passed in xprt transport */ int rpc_clnt_test_and_add_xprt (struct rpc_clnt *clnt,struct rpc_xprt_switch *xps,struct rpc_xprt *xprt, -void *dummy) +void *in_max_connect) {struct rpc_cb_add_xprt_calldata *data;struct rpc_task *task; +int max_connect = clnt->cl_max_connect; -if (xps->xps_nunique_destaddr_xprts +1 > clnt->cl_max_connect) { +if (in_max_connect) + max_connect = *(int *)in_max_connect; +if (xps->xps_nunique_destaddr_xprts +1 > max_connect) {rcu_read_lock ();pr_warn ("SUNRPC: reached max allowed number (%d) did not add " -"transport to server: %s\n" , clnt->cl_max_connect, +"transport to server: %s\n" , max_connect,rpc_peeraddr2str (clnt,RPC_DISPLAY_ADDR ));rcu_read_unlock ();return -EINVAL ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 7/183 tracing: Make trace_marker{,_raw} stream-like
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: John Keeping <[email protected]>
[ Upstream commit 2972e3050e3517a85ca1813b227d4c302e804343 ]
The tracing marker files are write-only streams with no meaningful concept of file position. Using stream_open() to mark them as stream-link indicates this and has the added advantage that a single file descriptor can now be used from multiple threads without contention thanks to clearing FMODE_ATOMIC_POS.
Note that this has the potential to break existing userspace by since both lseek(2) and pwrite(2) will now return ESPIPE when previously lseek would have updated the stored offset and pwrite would have appended to the trace. A survey of libtracefs and several other projects found to use trace_marker(_raw) [1][2][3] suggests that everyone limits themselves to calling write(2) and close(2) on these file descriptors so there is a good chance this will go unnoticed and the benefits of reduced overhead and lock contention seem worth the risk.
[1] https://github.com/google/perfetto
[2] https://github.com/intel/media-driver/
[3] https://w1.fi/cgit/hostap/
Stable-dep-of: f5ca233e2e66 ("tracing: Increase trace array ref count on enable and filter files")
--- kernel/trace/trace.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-)
kernel/trace/trace.c +8 -10
@@ -4887,6 +4887,12 @@ int tracing_open_generic_tr(struct inode *inode, struct file *filp)return 0 ; } +static int tracing_mark_open (struct inode *inode,struct file *filp) +{ +stream_open (inode, filp); +return tracing_open_generic_tr (inode, filp); +} +static int tracing_release (struct inode *inode,struct file *file) {struct trace_array *tr = inode->i_private;
@@ -7225,9 +7231,6 @@ tracing_mark_write(struct file *filp, const char __user *ubuf,if (tt)event_triggers_post_call (tr->trace_marker_file, tt); -if (written >0 ) - *fpos += written; -return written; }
@@ -7286,9 +7289,6 @@ tracing_mark_raw_write(struct file *filp, const char __user *ubuf,__buffer_unlock_commit (buffer, event); -if (written >0 ) - *fpos += written; -return written; }
@@ -7699,16 +7699,14 @@ static const struct file_operations tracing_free_buffer_fops = { };static const struct file_operations tracing_mark_fops = { - .open = tracing_open_generic_tr, + .open = tracing_mark_open, .write = tracing_mark_write, - .llseek = generic_file_llseek, .release = tracing_release_generic_tr, };static const struct file_operations tracing_mark_raw_fops = { - .open = tracing_open_generic_tr, + .open = tracing_mark_open, .write = tracing_mark_raw_write, - .llseek = generic_file_llseek, .release = tracing_release_generic_tr, };
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 8/183 tracing: Increase trace array ref count on enable and filter files
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Steven Rostedt (Google) <[email protected]>
[ Upstream commit f5ca233e2e66dc1c249bf07eefa37e34a6c9346a ]
When the trace event enable and filter files are opened, increment the trace array ref counter, otherwise they can be accessed when the trace array is being deleted. The ref counter keeps the trace array from being deleted while those files are opened.
--- kernel/trace/trace.c | 27 +++++++++++++++++++++++++++ kernel/trace/trace.h | 2 ++ kernel/trace/trace_events.c | 6 ++++-- 3 files changed, 33 insertions(+), 2 deletions(-)
kernel/trace/trace.c +27 -0
@@ -4887,6 +4887,33 @@ int tracing_open_generic_tr(struct inode *inode, struct file *filp)return 0 ; } +/* +* The private pointer of the inode is the trace_event_file. +* Update the tr ref count associated to it. +*/ +int tracing_open_file_tr (struct inode *inode,struct file *filp) +{ +struct trace_event_file *file = inode->i_private; +int ret; + + ret =tracing_check_open_get_tr (file->tr); +if (ret) +return ret; + + filp->private_data = inode->i_private; + +return 0 ; +} + +int tracing_release_file_tr (struct inode *inode,struct file *filp) +{ +struct trace_event_file *file = inode->i_private; + +trace_array_put (file->tr); + +return 0 ; +} +static int tracing_mark_open (struct inode *inode,struct file *filp) {stream_open (inode, filp);
kernel/trace/trace.h +2 -0
@@ -591,6 +591,8 @@ void tracing_reset_all_online_cpus(void);void tracing_reset_all_online_cpus_unlocked (void );int tracing_open_generic (struct inode *inode,struct file *filp);int tracing_open_generic_tr (struct inode *inode,struct file *filp); +int tracing_open_file_tr (struct inode *inode,struct file *filp); +int tracing_release_file_tr (struct inode *inode,struct file *filp);bool tracing_is_disabled (void );bool tracer_tracing_is_on (struct trace_array *tr);void tracer_tracing_on (struct trace_array *tr);
kernel/trace/trace_events.c +4 -2
@@ -2078,9 +2078,10 @@ static const struct file_operations ftrace_set_event_notrace_pid_fops = { };static const struct file_operations ftrace_enable_fops = { - .open = tracing_open_generic, + .open = tracing_open_file_tr, .read = event_enable_read, .write = event_enable_write, + .release = tracing_release_file_tr, .llseek = default_llseek, };
@@ -2097,9 +2098,10 @@ static const struct file_operations ftrace_event_id_fops = { };static const struct file_operations ftrace_event_filter_fops = { - .open = tracing_open_generic, + .open = tracing_open_file_tr, .read = event_filter_read, .write = event_filter_write, + .release = tracing_release_file_tr, .llseek = default_llseek, };
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 9/183 ata: ahci: Drop pointless VPRINTK() calls and convert the remaining ones
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Hannes Reinecke <[email protected]>
[ Upstream commit 93c7711494f47f9c829321e2a8711671b02f6e4c ]
Drop pointless VPRINTK() calls for entering and existing interrupt routines and convert the remaining calls to dev_dbg().
Stable-dep-of: 737dd811a3db ("ata: libahci: clear pending interrupt status")
--- drivers/ata/ahci.c | 4 +--- drivers/ata/ahci_xgene.c | 4 ---- drivers/ata/libahci.c | 18 ++++-------------- 3 files changed, 5 insertions(+), 21 deletions(-)
drivers/ata/ahci.c +1 -3
@@ -707,7 +707,7 @@ static void ahci_pci_init_controller(struct ata_host *host)/* clear port IRQ */ tmp =readl (port_mmio +PORT_IRQ_STAT ); -VPRINTK ("PORT_IRQ_STAT 0x%x\n" , tmp); +dev_dbg (&pdev->dev,"PORT_IRQ_STAT 0x%x\n" , tmp);if (tmp)writel (tmp, port_mmio +PORT_IRQ_STAT ); }
@@ -1499,7 +1499,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)u32 irq_stat, irq_masked;unsigned int handled =1 ; -VPRINTK ("ENTER\n" ); hpriv = host->private_data; mmio = hpriv->mmio; irq_stat =readl (mmio +HOST_IRQ_STAT );
@@ -1516,7 +1515,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) irq_stat =readl (mmio +HOST_IRQ_STAT );spin_unlock (&host->lock); }while (irq_stat); -VPRINTK ("EXIT\n" );return IRQ_RETVAL (handled); }
drivers/ata/ahci_xgene.c +0 -4
@@ -588,8 +588,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)void __iomem *mmio;u32 irq_stat, irq_masked; -VPRINTK ("ENTER\n" ); - hpriv = host->private_data; mmio = hpriv->mmio;
@@ -612,8 +610,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)spin_unlock (&host->lock); -VPRINTK ("EXIT\n" ); -return IRQ_RETVAL (rc); }
drivers/ata/libahci.c +4 -14
@@ -1216,12 +1216,12 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,/* clear SError */ tmp =readl (port_mmio +PORT_SCR_ERR ); -VPRINTK ("PORT_SCR_ERR 0x%x\n" , tmp); +dev_dbg (dev,"PORT_SCR_ERR 0x%x\n" , tmp);writel (tmp, port_mmio +PORT_SCR_ERR );/* clear port IRQ */ tmp =readl (port_mmio +PORT_IRQ_STAT ); -VPRINTK ("PORT_IRQ_STAT 0x%x\n" , tmp); +dev_dbg (dev,"PORT_IRQ_STAT 0x%x\n" , tmp);if (tmp)writel (tmp, port_mmio +PORT_IRQ_STAT );
@@ -1252,10 +1252,10 @@ void ahci_init_controller(struct ata_host *host) } tmp =readl (mmio +HOST_CTL ); -VPRINTK ("HOST_CTL 0x%x\n" , tmp); +dev_dbg (host->dev,"HOST_CTL 0x%x\n" , tmp);writel (tmp |HOST_IRQ_EN , mmio +HOST_CTL ); tmp =readl (mmio +HOST_CTL ); -VPRINTK ("HOST_CTL 0x%x\n" , tmp); +dev_dbg (host->dev,"HOST_CTL 0x%x\n" , tmp); }EXPORT_SYMBOL_GPL (ahci_init_controller);
@@ -1906,8 +1906,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)void __iomem *port_mmio =ahci_port_base (ap);u32 status; -VPRINTK ("ENTER\n" ); - status =readl (port_mmio +PORT_IRQ_STAT );writel (status, port_mmio +PORT_IRQ_STAT );
@@ -1915,8 +1913,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)ahci_handle_port_interrupt (ap, port_mmio, status);spin_unlock (ap->lock); -VPRINTK ("EXIT\n" ); -return IRQ_HANDLED ; }
@@ -1933,9 +1929,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) ap = host->ports[i];if (ap) {ahci_port_intr (ap); -VPRINTK ("port %u\n" , i); }else { -VPRINTK ("port %u (no irq)\n" , i);if (ata_ratelimit ())dev_warn (host->dev,"interrupt on disabled port %u\n" , i);
@@ -1956,8 +1950,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)void __iomem *mmio;u32 irq_stat, irq_masked; -VPRINTK ("ENTER\n" ); - hpriv = host->private_data; mmio = hpriv->mmio;
@@ -1985,8 +1977,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)spin_unlock (&host->lock); -VPRINTK ("EXIT\n" ); -return IRQ_RETVAL (rc); }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 10/183 ata: libahci: clear pending interrupt status
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Szuying Chen <[email protected]>
[ Upstream commit 737dd811a3dbfd7edd4ad2ba5152e93d99074f83 ]
When a CRC error occurs, the HBA asserts an interrupt to indicate an interface fatal error (PxIS.IFS). The ISR clears PxIE and PxIS, then does error recovery. If the adapter receives another SDB FIS with an error (PxIS.TFES) from the device before the start of the EH recovery process, the interrupt signaling the new SDB cannot be serviced as PxIE was cleared already. This in turn results in the HBA inability to issue any command during the error recovery process after setting PxCMD.ST to 1 because PxIS.TFES is still set.
According to AHCI 1.3.1 specifications section 6.2.2, fatal errors notified by setting PxIS.HBFS, PxIS.HBDS, PxIS.IFS or PxIS.TFES will cause the HBA to enter the ERR:Fatal state. In this state, the HBA shall not issue any new commands.
To avoid this situation, introduce the function ahci_port_clear_pending_irq() to clear pending interrupts before executing a COMRESET. This follows the AHCI 1.3.1 - section 6.2.2.2 specification.
--- drivers/ata/libahci.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-)
drivers/ata/libahci.c +23 -12
@@ -1200,6 +1200,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)return sprintf (buf,"%d\n" , emp->blink_policy); } +static void ahci_port_clear_pending_irq (struct ata_port *ap) +{ +struct ahci_host_priv *hpriv = ap->host->private_data; +void __iomem *port_mmio =ahci_port_base (ap); +u32 tmp; + +/* clear SError */ + tmp =readl (port_mmio +PORT_SCR_ERR ); +dev_dbg (ap->host->dev,"PORT_SCR_ERR 0x%x\n" , tmp); +writel (tmp, port_mmio +PORT_SCR_ERR ); + +/* clear port IRQ */ + tmp =readl (port_mmio +PORT_IRQ_STAT ); +dev_dbg (ap->host->dev,"PORT_IRQ_STAT 0x%x\n" , tmp); +if (tmp) +writel (tmp, port_mmio +PORT_IRQ_STAT ); + +writel (1 << ap->port_no, hpriv->mmio +HOST_IRQ_STAT ); +} +static void ahci_port_init (struct device *dev,struct ata_port *ap,int port_no,void __iomem *mmio,void __iomem *port_mmio)
@@ -1214,18 +1234,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,if (rc)dev_warn (dev,"%s (%d)\n" , emsg, rc); -/* clear SError */ - tmp =readl (port_mmio +PORT_SCR_ERR ); -dev_dbg (dev,"PORT_SCR_ERR 0x%x\n" , tmp); -writel (tmp, port_mmio +PORT_SCR_ERR ); - -/* clear port IRQ */ - tmp =readl (port_mmio +PORT_IRQ_STAT ); -dev_dbg (dev,"PORT_IRQ_STAT 0x%x\n" , tmp); -if (tmp) -writel (tmp, port_mmio +PORT_IRQ_STAT ); - -writel (1 << port_no, mmio +HOST_IRQ_STAT ); +ahci_port_clear_pending_irq (ap);/* mark esata ports */ tmp =readl (port_mmio +PORT_CMD );
@@ -1555,6 +1564,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class, tf.status =ATA_BUSY ;ata_tf_to_fis (&tf,0 ,0 , d2h_fis); +ahci_port_clear_pending_irq (ap); + rc =sata_link_hardreset (link, timing, deadline, online, ahci_check_ready);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 11/183 ext4: scope ret locally in ext4_try_to_trim_range()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Lukas Bulwahn <[email protected]>
[ Upstream commit afcc4e32f606dbfb47aa7309172c89174b86e74c ]
As commit 6920b3913235 ("ext4: add new helper interface ext4_try_to_trim_range()") moves some code into the separate function ext4_try_to_trim_range(), the use of the variable ret within that function is more limited and can be adjusted as well.
Scope the use of the variable ret locally and drop dead assignments.
No functional change.
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
--- fs/ext4/mballoc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
fs/ext4/mballoc.c +2 -3
@@ -6441,7 +6441,6 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group)) {ext4_grpblk_t next, count, free_count;void *bitmap; -int ret =0 ; bitmap = e4b->bd_bitmap; start = (e4b->bd_info->bb_first_free > start) ?
@@ -6456,10 +6455,10 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group)) next =mb_find_next_bit (bitmap, max +1 , start);if ((next - start) >= minblocks) { - ret =ext4_trim_extent (sb, start, next - start, e4b); +int ret =ext4_trim_extent (sb, start, next - start, e4b); +if (ret && ret != -EOPNOTSUPP )break ; - ret =0 ; count += next - start; } free_count += next - start;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 12/183 ext4: change s_last_trim_minblks type to unsigned long
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Lukas Czerner <[email protected]>
[ Upstream commit 2327fb2e23416cfb2795ccca2f77d4d65925be99 ]
There is no good reason for the s_last_trim_minblks to be atomic. There is no data integrity needed and there is no real danger in setting and reading it in a racy manner. Change it to be unsigned long, the same type as s_clusters_per_group which is the maximum that's allowed.
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
--- fs/ext4/ext4.h | 2 +- fs/ext4/mballoc.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
fs/ext4/ext4.h +1 -1
@@ -1656,7 +1656,7 @@ struct ext4_sb_info {struct task_struct *s_mmp_tsk;/* record the last minlen when FITRIM is called. */ -atomic_t s_last_trim_minblks; +unsigned long s_last_trim_minblks;/* Reference to checksum algorithm driver via cryptoapi */ struct crypto_shash *s_chksum_driver;
fs/ext4/mballoc.c +2 -2
@@ -6516,7 +6516,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,ext4_lock_group (sb, group);if (!EXT4_MB_GRP_WAS_TRIMMED (e4b.bd_info) || - minblocks <atomic_read (&EXT4_SB (sb)->s_last_trim_minblks)) { + minblocks <EXT4_SB (sb)->s_last_trim_minblks) { ret =ext4_try_to_trim_range (sb, &e4b, start, max, minblocks);if (ret >=0 && set_trimmed)EXT4_MB_GRP_SET_TRIMMED (e4b.bd_info);
@@ -6632,7 +6632,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) }if (!ret) -atomic_set (&EXT4_SB (sb)->s_last_trim_minblks, minlen); +EXT4_SB (sb)->s_last_trim_minblks = minlen; out: range->len =EXT4_C2B (EXT4_SB (sb), trimmed) << sb->s_blocksize_bits;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 13/183 ext4: replace the traditional ternary conditional operator with with max()/min()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kemeng Shi <[email protected]>
[ Upstream commit de8bf0e5ee7482585450357c6d4eddec8efc5cb7 ]
Replace the traditional ternary conditional operator with with max()/min()
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
--- fs/ext4/mballoc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
fs/ext4/mballoc.c +2 -4
@@ -6443,8 +6443,7 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group))void *bitmap; bitmap = e4b->bd_bitmap; - start = (e4b->bd_info->bb_first_free > start) ? - e4b->bd_info->bb_first_free : start; + start =max (e4b->bd_info->bb_first_free, start); count =0 ; free_count =0 ;
@@ -6661,8 +6660,7 @@ ext4_mballoc_query_range(ext4_lock_group (sb, group); - start = (e4b.bd_info->bb_first_free > start) ? - e4b.bd_info->bb_first_free : start; + start =max (e4b.bd_info->bb_first_free, start);if (end >=EXT4_CLUSTERS_PER_GROUP (sb)) end =EXT4_CLUSTERS_PER_GROUP (sb) -1 ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 14/183 ext4: move setting of trimmed bit into ext4_try_to_trim_range()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jan Kara <[email protected]>
[ Upstream commit 45e4ab320c9b5fa67b1fc3b6a9b381cfcc0c8488 ]
Currently we set the group's trimmed bit in ext4_trim_all_free() based on return value of ext4_try_to_trim_range(). However when we will want to abort trimming because of suspend attempt, we want to return success from ext4_try_to_trim_range() but not set the trimmed bit. Instead implementing awkward propagation of this information, just move setting of trimmed bit into ext4_try_to_trim_range() when the whole group is trimmed.
--- fs/ext4/mballoc.c | 46 +++++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 21 deletions(-)
fs/ext4/mballoc.c +25 -21
@@ -6433,6 +6433,16 @@ __acquires(bitlock)return ret; } +static ext4_grpblk_t ext4_last_grp_cluster (struct super_block *sb, +ext4_group_t grp) +{ +if (grp <ext4_get_groups_count (sb)) +return EXT4_CLUSTERS_PER_GROUP (sb) -1 ; +return (ext4_blocks_count (EXT4_SB (sb)->s_es) - +ext4_group_first_block_no (sb, grp) -1 ) >> +EXT4_CLUSTER_BITS (sb); +} +static int ext4_try_to_trim_range (struct super_block *sb,struct ext4_buddy *e4b,ext4_grpblk_t start,ext4_grpblk_t max,ext4_grpblk_t minblocks)
@@ -6440,9 +6450,12 @@ __acquires(ext4_group_lock_ptr(sb, e4b->bd_group)) __releases(ext4_group_lock_ptr(sb, e4b->bd_group)) {ext4_grpblk_t next, count, free_count; +bool set_trimmed = false;void *bitmap; bitmap = e4b->bd_bitmap; +if (start ==0 && max >=ext4_last_grp_cluster (sb, e4b->bd_group)) + set_trimmed = true; start =max (e4b->bd_info->bb_first_free, start); count =0 ; free_count =0 ;
@@ -6457,16 +6470,14 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group))int ret =ext4_trim_extent (sb, start, next - start, e4b);if (ret && ret != -EOPNOTSUPP ) -break ; +return count; count += next - start; } free_count += next - start; start = next +1 ; -if (fatal_signal_pending (current)) { - count = -ERESTARTSYS ; -break ; - } +if (fatal_signal_pending (current)) +return -ERESTARTSYS ;if (need_resched ()) {ext4_unlock_group (sb, e4b->bd_group);
@@ -6478,6 +6489,9 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group))break ; } +if (set_trimmed) +EXT4_MB_GRP_SET_TRIMMED (e4b->bd_info); +return count; }
@@ -6488,7 +6502,6 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group))* @start: first group block to examine * @max: last group block to examine * @minblocks: minimum extent block count -* @set_trimmed: set the trimmed flag if at least one block is trimmed * * ext4_trim_all_free walks through group's block bitmap searching for free * extents. When the free extent is found, mark it as used in group buddy
@@ -6498,7 +6511,7 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group))static ext4_grpblk_t ext4_trim_all_free (struct super_block *sb,ext4_group_t group,ext4_grpblk_t start,ext4_grpblk_t max, -ext4_grpblk_t minblocks,bool set_trimmed) +ext4_grpblk_t minblocks) {struct ext4_buddy e4b;int ret;
@@ -6515,13 +6528,10 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,ext4_lock_group (sb, group);if (!EXT4_MB_GRP_WAS_TRIMMED (e4b.bd_info) || - minblocks <EXT4_SB (sb)->s_last_trim_minblks) { + minblocks <EXT4_SB (sb)->s_last_trim_minblks) ret =ext4_try_to_trim_range (sb, &e4b, start, max, minblocks); -if (ret >=0 && set_trimmed) -EXT4_MB_GRP_SET_TRIMMED (e4b.bd_info); - }else { +else ret =0 ; - }ext4_unlock_group (sb, group);ext4_mb_unload_buddy (&e4b);
@@ -6554,7 +6564,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)ext4_fsblk_t first_data_blk =le32_to_cpu (EXT4_SB (sb)->s_es->s_first_data_block);ext4_fsblk_t max_blks =ext4_blocks_count (EXT4_SB (sb)->s_es); -bool whole_group, eof = false;int ret =0 ; start = range->start >> sb->s_blocksize_bits;
@@ -6573,10 +6582,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)if (minlen >EXT4_CLUSTERS_PER_GROUP (sb)) goto out; } -if (end >= max_blks -1 ) { +if (end >= max_blks -1 ) end = max_blks -1 ; - eof = true; - }if (end <= first_data_blk) goto out;if (start < first_data_blk)
@@ -6590,7 +6597,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)/* end now represents the last cluster to discard in this group */ end =EXT4_CLUSTERS_PER_GROUP (sb) -1 ; - whole_group = true;for (group = first_group; group <= last_group; group++) { grp =ext4_get_group_info (sb, group);
@@ -6609,13 +6615,11 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)* change it for the last group, note that last_cluster is * already computed earlier by ext4_get_group_no_and_offset() */ -if (group == last_group) { +if (group == last_group) end = last_cluster; - whole_group = eof ? true : end ==EXT4_CLUSTERS_PER_GROUP (sb) -1 ; - }if (grp->bb_free >= minlen) { cnt =ext4_trim_all_free (sb, group, first_cluster, - end, minlen, whole_group); + end, minlen);if (cnt <0 ) { ret = cnt;break ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 15/183 ext4: do not let fstrim block system suspend
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jan Kara <[email protected]>
[ Upstream commit 5229a658f6453362fbb9da6bf96872ef25a7097e ]
Len Brown has reported that system suspend sometimes fail due to inability to freeze a task working in ext4_trim_fs() for one minute. Trimming a large filesystem on a disk that slowly processes discard requests can indeed take a long time. Since discard is just an advisory call, it is perfectly fine to interrupt it at any time and the return number of discarded blocks until that moment. Do that when we detect the task is being frozen.
References: https://bugzilla.kernel.org/show_bug.cgi?id=216322
--- fs/ext4/mballoc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
fs/ext4/mballoc.c +10 -2
@@ -16,6 +16,7 @@#include <linux/slab.h> #include <linux/nospec.h> #include <linux/backing-dev.h> +#include <linux/freezer.h> #include <trace/events/ext4.h> /*
@@ -6443,6 +6444,11 @@ static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb,EXT4_CLUSTER_BITS (sb); } +static bool ext4_trim_interrupted (void ) +{ +return fatal_signal_pending (current) ||freezing (current); +} +static int ext4_try_to_trim_range (struct super_block *sb,struct ext4_buddy *e4b,ext4_grpblk_t start,ext4_grpblk_t max,ext4_grpblk_t minblocks)
@@ -6476,8 +6482,8 @@ __releases(ext4_group_lock_ptr(sb, e4b->bd_group)) free_count += next - start; start = next +1 ; -if (fatal_signal_pending (current)) -return -ERESTARTSYS ; +if (ext4_trim_interrupted ()) +return count;if (need_resched ()) {ext4_unlock_group (sb, e4b->bd_group);
@@ -6599,6 +6605,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) end =EXT4_CLUSTERS_PER_GROUP (sb) -1 ;for (group = first_group; group <= last_group; group++) { +if (ext4_trim_interrupted ()) +break ; grp =ext4_get_group_info (sb, group);if (!grp)continue ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 16/183 tracing: Have event inject files inc the trace array ref count
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Steven Rostedt (Google) <[email protected]>
[ Upstream commit e5c624f027ac74f97e97c8f36c69228ac9f1102d ]
The event inject files add events for a specific trace array. For an instance, if the file is opened and the instance is deleted, reading or writing to the file will cause a use after free.
Up the ref count of the trace_array when a event inject file is opened.
--- kernel/trace/trace_events_inject.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
kernel/trace/trace_events_inject.c +2 -1
@@ -321,7 +321,8 @@ event_inject_read(struct file *file, char __user *buf, size_t size, }const struct file_operations event_inject_fops = { - .open = tracing_open_generic, + .open = tracing_open_file_tr, .read = event_inject_read, .write = event_inject_write, + .release = tracing_release_file_tr, };
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 17/183 netfilter: nf_tables: dont skip expired elements during walk
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
commit 24138933b97b055d486e8064b4a1721702442a9b upstream.
There is an asymmetry between commit/abort and preparation phase if the following conditions are met:
1. set is a verdict map ("1.2.3.4 : jump foo")
2. timeouts are enabled
In this case, following sequence is problematic:
1. element E in set S refers to chain C
2. userspace requests removal of set S
3. kernel does a set walk to decrement chain->use count for all elements from preparation phase
4. kernel does another set walk to remove elements from the commit phase (or another walk to do a chain->use increment for all elements from abort phase)
If E has already expired in 1), it will be ignored during list walk, so its use count won't have been changed.
Then, when set is culled, ->destroy callback will zap the element via nf_tables_set_elem_destroy(), but this function is only safe for elements that have been deactivated earlier from the preparation phase:
lack of earlier deactivate removes the element but leaks the chain use count, which results in a WARN splat when the chain gets removed later, plus a leak of the nft_chain structure.
Update pipapo_get() not to skip expired elements, otherwise flush command reports bogus ENOENT errors.
--- net/netfilter/nf_tables_api.c | 4 ++++ net/netfilter/nft_set_hash.c | 2 -- net/netfilter/nft_set_pipapo.c | 18 ++++++++++++------ net/netfilter/nft_set_rbtree.c | 2 -- 4 files changed, 16 insertions(+), 10 deletions(-)
net/netfilter/nf_tables_api.c +4 -0
@@ -5289,8 +5289,12 @@ static int nf_tables_dump_setelem(const struct nft_ctx *ctx,const struct nft_set_iter *iter, struct nft_set_elem *elem) { + const struct nft_set_ext *ext = nft_set_elem_ext(set, elem->priv);struct nft_set_dump_args *args; +if (nft_set_elem_expired (ext)) +return 0 ; + args = container_of(iter, struct nft_set_dump_args, iter);return nf_tables_fill_setelem (args->skb, set, elem); }
net/netfilter/nft_set_hash.c +0 -2
@@ -278,8 +278,6 @@ static void nft_rhash_walk(const struct nft_ctx *ctx, struct nft_set *set,if (iter->count < iter->skip) goto cont; -if (nft_set_elem_expired (&he->ext)) - goto cont;if (!nft_set_elem_active (&he->ext, iter->genmask)) goto cont;
net/netfilter/nft_set_pipapo.c +12 -6
@@ -566,8 +566,7 @@ static struct nft_pipapo_elem *pipapo_get(const struct net *net, goto out;if (last) { -if (nft_set_elem_expired (&f->mt[b].e->ext) || - (genmask && +if ((genmask && !nft_set_elem_active (&f->mt[b].e->ext, genmask))) goto next_match;
@@ -601,8 +600,17 @@ static struct nft_pipapo_elem *pipapo_get(const struct net *net,static void *nft_pipapo_get (const struct net *net,const struct nft_set *set,const struct nft_set_elem *elem,unsigned int flags) { -return pipapo_get (net, set, (const u8 *)elem->key.val.data, -nft_genmask_cur (net)); +struct nft_pipapo_elem *ret; + + ret =pipapo_get (net, set, (const u8 *)elem->key.val.data, +nft_genmask_cur (net)); +if (IS_ERR (ret)) +return ret; + +if (nft_set_elem_expired (&ret->ext)) +return ERR_PTR (-ENOENT ); + +return ret; }/**
@@ -2024,8 +2032,6 @@ static void nft_pipapo_walk(const struct nft_ctx *ctx, struct nft_set *set, goto cont; e = f->mt[r].e; -if (nft_set_elem_expired (&e->ext)) - goto cont; elem.priv = e;
net/netfilter/nft_set_rbtree.c +0 -2
@@ -552,8 +552,6 @@ static void nft_rbtree_walk(const struct nft_ctx *ctx,if (iter->count < iter->skip) goto cont; -if (nft_set_elem_expired (&rbe->ext)) - goto cont;if (!nft_set_elem_active (&rbe->ext, iter->genmask)) goto cont;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 18/183 netfilter: nf_tables: GC transaction API to avoid race with control plane
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 5f68718b34a531a556f2f50300ead2862278da26 upstream.
The set types rhashtable and rbtree use a GC worker to reclaim memory.
Quoted 1 line
From system work queue, in periodic intervals, a scan of the table is
done.
The major caveat here is that the nft transaction mutex is not held. This causes a race between control plane and GC when they attempt to delete the same element.
We cannot grab the netlink mutex from the work queue, because the control plane has to wait for the GC work queue in case the set is to be removed, so we get following deadlock:
cpu 1 cpu2
GC work transaction comes in , lock nft mutex
`acquire nft mutex // BLOCKS
transaction asks to remove the set set destruction calls cancel_work_sync()
cancel_work_sync will now block forever, because it is waiting for the mutex the caller already owns.
This patch adds a new API that deals with garbage collection in two steps:
1) Lockless GC of expired elements sets on the NFT_SET_ELEM_DEAD_BIT so they are not visible via lookup. Annotate current GC sequence in the GC transaction. Enqueue GC transaction work as soon as it is full. If ruleset is updated, then GC transaction is aborted and retried later.
2) GC work grabs the mutex. If GC sequence has changed then this GC transaction lost race with control plane, abort it as it contains stale references to objects and let GC try again later. If the ruleset is intact, then this GC transaction deactivates and removes the elements and it uses call_rcu() to destroy elements.
Note that no elements are removed from GC lockless path, the _DEAD bit is set and pointers are collected. GC catchall does not remove the elements anymore too. There is a new set->dead flag that is set on to abort the GC transaction to deal with set->ops->destroy() path which removes the remaining elements in the set from commit_release, where no mutex is held.
To deal with GC when mutex is held, which allows safe deactivate and removal, add sync GC API which releases the set element object via call_rcu(). This is used by rbtree and pipapo backends which also perform garbage collection from control plane path.
Since element removal from sets can happen from control plane and element garbage collection/timeout, it is necessary to keep the set structure alive until all elements have been deactivated and destroyed.
We cannot do a cancel_work_sync or flush_work in nft_set_destroy because its called with the transaction mutex held, but the aforementioned async work queue might be blocked on the very mutex that nft_set_destroy() callchain is sitting on.
This gives us the choice of ABBA deadlock or UaF.
To avoid both, add set->refs refcount_t member. The GC API can then increment the set refcount and release it once the elements have been free'd.
Set backends are adapted to use the GC transaction API in a follow up patch entitled:
("netfilter: nf_tables: use gc transaction API in set backends")
This is joint work with Florian Westphal.
--- include/net/netfilter/nf_tables.h | 64 +++++++- net/netfilter/nf_tables_api.c | 248 ++++++++++++++++++++++++++++-- 2 files changed, 300 insertions(+), 12 deletions(-)
include/net/netfilter/nf_tables.h +63 -1
@@ -477,6 +477,7 @@ struct nft_set_elem_expr {* * @list: table set list node * @bindings: list of set bindings +* @refs: internal refcounting for async set destruction * @table: table this set belongs to * @net: netnamespace this set belongs to * @name: name of the set
@@ -506,6 +507,7 @@ struct nft_set_elem_expr {struct nft_set {struct list_head list;struct list_head bindings; +refcount_t refs;struct nft_table *table;possible_net_t net;char *name;
@@ -527,7 +529,8 @@ struct nft_set {struct list_head pending_update;/* runtime data below here */ const struct nft_set_ops *ops____cacheline_aligned ; - u16 flags:14, + u16 flags:13, + dead:1, genmask:2;u8 klen;u8 dlen;
@@ -1525,6 +1528,32 @@ static inline void nft_set_elem_clear_busy(struct nft_set_ext *ext)clear_bit (NFT_SET_ELEM_BUSY_BIT , word); } +#define NFT_SET_ELEM_DEAD_MASK (1 << 3) + +#if defined(__LITTLE_ENDIAN_BITFIELD) +#define NFT_SET_ELEM_DEAD_BIT 3 +#elif defined(__BIG_ENDIAN_BITFIELD) +#define NFT_SET_ELEM_DEAD_BIT (BITS_PER_LONG - BITS_PER_BYTE + 3) +#else +#error +#endif + +static inline void nft_set_elem_dead (struct nft_set_ext *ext) +{ +unsigned long *word = (unsigned long *)ext; + +BUILD_BUG_ON (offsetof(struct nft_set_ext , genmask) !=0 ); +set_bit (NFT_SET_ELEM_DEAD_BIT , word); +} + +static inline int nft_set_elem_is_dead (const struct nft_set_ext *ext) +{ +unsigned long *word = (unsigned long *)ext; + +BUILD_BUG_ON (offsetof(struct nft_set_ext , genmask) !=0 ); +return test_bit (NFT_SET_ELEM_DEAD_BIT , word); +} +/** * struct nft_trans - nf_tables object update in transaction *
@@ -1656,6 +1685,38 @@ struct nft_trans_flowtable {#define nft_trans_flowtable_flags (trans) \ (((struct nft_trans_flowtable *)trans->data)->flags) +#define NFT_TRANS_GC_BATCHCOUNT 256 + +struct nft_trans_gc { +struct list_head list; +struct net *net; +struct nft_set *set; +u32 seq; +u8 count; +void *priv[NFT_TRANS_GC_BATCHCOUNT ]; +struct rcu_head rcu; +}; + +struct nft_trans_gc *nft_trans_gc_alloc (struct nft_set *set, +unsigned int gc_seq,gfp_t gfp); +void nft_trans_gc_destroy (struct nft_trans_gc *trans); + +struct nft_trans_gc *nft_trans_gc_queue_async (struct nft_trans_gc *gc, +unsigned int gc_seq,gfp_t gfp); +void nft_trans_gc_queue_async_done (struct nft_trans_gc *gc); + +struct nft_trans_gc *nft_trans_gc_queue_sync (struct nft_trans_gc *gc,gfp_t gfp); +void nft_trans_gc_queue_sync_done (struct nft_trans_gc *trans); + +void nft_trans_gc_elem_add (struct nft_trans_gc *gc,void *priv); + +struct nft_trans_gc *nft_trans_gc_catchall (struct nft_trans_gc *gc, +unsigned int gc_seq); + +void nft_setelem_data_deactivate (const struct net *net, +const struct nft_set *set, +struct nft_set_elem *elem); +int __init nft_chain_filter_init (void );void nft_chain_filter_fini (void );
@@ -1683,6 +1744,7 @@ struct nftables_pernet {u64 table_handle;unsigned int base_seq;u8 validate_state; +unsigned int gc_seq; };extern unsigned int nf_tables_net_id;
net/netfilter/nf_tables_api.c +237 -11
353 lines not on this page · raw message
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 19/183 netfilter: nf_tables: adapt set backend to use GC transaction API
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit f6c383b8c31a93752a52697f8430a71dcbc46adf upstream.
Use the GC transaction API to replace the old and buggy gc API and the busy mark approach.
No set elements are removed from async garbage collection anymore, instead the _DEAD bit is set on so the set element is not visible from lookup path anymore. Async GC enqueues transaction work that might be aborted and retried later.
rbtree and pipapo set backends does not set on the _DEAD bit from the sync GC path since this runs in control plane path where mutex is held. In this case, set elements are deactivated, removed and then released via RCU callback, sync GC never fails.
--- net/netfilter/nf_tables_api.c | 7 +- net/netfilter/nft_set_hash.c | 77 +++++++++++------- net/netfilter/nft_set_pipapo.c | 48 ++++++++--- net/netfilter/nft_set_rbtree.c | 144 ++++++++++++++++++++------------- 4 files changed, 173 insertions(+), 103 deletions(-)
net/netfilter/nf_tables_api.c +2 -5
@@ -6008,7 +6008,6 @@ static void nft_setelem_activate(struct net *net, struct nft_set *set,if (nft_setelem_is_catchall (set, elem)) {nft_set_elem_change_active (net, set, ext); -nft_set_elem_clear_busy (ext); }else { set->ops->activate (net, set, elem); }
@@ -6023,8 +6022,7 @@ static int nft_setelem_catchall_deactivate(const struct net *net,list_for_each_entry (catchall, &set->catchall_list, list) { ext =nft_set_elem_ext (set, catchall->elem); -if (!nft_is_active (net, ext) || -nft_set_elem_mark_busy (ext)) +if (!nft_is_active (net, ext))continue ;kfree (elem->priv);
@@ -6725,8 +6723,7 @@ static int nft_set_catchall_flush(const struct nft_ctx *ctx,list_for_each_entry_rcu (catchall, &set->catchall_list, list) { ext =nft_set_elem_ext (set, catchall->elem); -if (!nft_set_elem_active (ext, genmask) || -nft_set_elem_mark_busy (ext)) +if (!nft_set_elem_active (ext, genmask))continue ; elem.priv = catchall->elem;
net/netfilter/nft_set_hash.c +48 -29
140 lines not on this page · raw message
net/netfilter/nft_set_pipapo.c +36 -12
83 lines not on this page · raw message
net/netfilter/nft_set_rbtree.c +87 -57
232 lines not on this page · raw message
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 20/183 netfilter: nft_set_hash: mark set element as dead when deleting from packet path
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
upstream c92db3030492b8ad1d0faace7a93bbcf53850d0c commit.
Set on the NFT_SET_ELEM_DEAD_BIT flag on this element, instead of performing element removal which might race with an ongoing transaction. Enable gc when dynamic flag is set on since dynset deletion requires garbage collection after this patch.
--- net/netfilter/nft_set_hash.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
net/netfilter/nft_set_hash.c +4 -2
@@ -249,7 +249,9 @@ static bool nft_rhash_delete(const struct nft_set *set,if (he ==NULL )return false; -return rhashtable_remove_fast (&priv->ht, &he->node, nft_rhash_params) ==0 ; +nft_set_elem_dead (&he->ext); + +return true; } static void nft_rhash_walk(const struct nft_ctx *ctx, struct nft_set *set,
@@ -412,7 +414,7 @@ static int nft_rhash_init(const struct nft_set *set,return err;INIT_DEFERRABLE_WORK (&priv->gc_work, nft_rhash_gc); -if (set->flags &NFT_SET_TIMEOUT ) +if (set->flags & (NFT_SET_TIMEOUT |NFT_SET_EVAL ))nft_rhash_gc_init (set);return 0 ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 21/183 netfilter: nf_tables: remove busy mark and gc batch API
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit a2dd0233cbc4d8a0abb5f64487487ffc9265beb5 upstream.
Ditch it, it has been replace it by the GC transaction API and it has no clients anymore.
--- include/net/netfilter/nf_tables.h | 98 +------------------------------ net/netfilter/nf_tables_api.c | 48 +-------------- 2 files changed, 4 insertions(+), 142 deletions(-)
include/net/netfilter/nf_tables.h +3 -95
@@ -564,7 +564,6 @@ struct nft_set *nft_set_lookup_global(const struct net *net,struct nft_set_ext *nft_set_catchall_lookup (const struct net *net,const struct nft_set *set); -void *nft_set_catchall_gc (const struct nft_set *set);static inline unsigned long nft_set_gc_interval (const struct nft_set *set) {
@@ -779,62 +778,6 @@ void nft_set_elem_destroy(const struct nft_set *set, void *elem,void nf_tables_set_elem_destroy (const struct nft_ctx *ctx,const struct nft_set *set,void *elem); -/** -* struct nft_set_gc_batch_head - nf_tables set garbage collection batch -* -* @rcu: rcu head -* @set: set the elements belong to -* @cnt: count of elements -*/ -struct nft_set_gc_batch_head { -struct rcu_head rcu; -const struct nft_set *set; -unsigned int cnt; -}; - -#define NFT_SET_GC_BATCH_SIZE ((PAGE_SIZE - \ - sizeof(struct nft_set_gc_batch_head)) / \ - sizeof(void *)) - -/** -* struct nft_set_gc_batch - nf_tables set garbage collection batch -* -* @head: GC batch head -* @elems: garbage collection elements -*/ -struct nft_set_gc_batch { -struct nft_set_gc_batch_head head; -void *elems[NFT_SET_GC_BATCH_SIZE ]; -}; - -struct nft_set_gc_batch *nft_set_gc_batch_alloc (const struct nft_set *set, -gfp_t gfp); -void nft_set_gc_batch_release (struct rcu_head *rcu); - -static inline void nft_set_gc_batch_complete (struct nft_set_gc_batch *gcb) -{ -if (gcb !=NULL ) -call_rcu (&gcb->head.rcu, nft_set_gc_batch_release); -} - -static inline struct nft_set_gc_batch * -nft_set_gc_batch_check (const struct nft_set *set,struct nft_set_gc_batch *gcb, -gfp_t gfp) -{ -if (gcb !=NULL ) { -if (gcb->head.cnt +1 <ARRAY_SIZE (gcb->elems)) -return gcb; -nft_set_gc_batch_complete (gcb); - } -return nft_set_gc_batch_alloc (set, gfp); -} - -static inline void nft_set_gc_batch_add (struct nft_set_gc_batch *gcb, -void *elem) -{ - gcb->elems[gcb->head.cnt++] = elem; -} -struct nft_expr_ops ;/** * struct nft_expr_type - nf_tables expression type
@@ -1493,47 +1436,12 @@ static inline void nft_set_elem_change_active(const struct net *net,#endif /* IS_ENABLED(CONFIG_NF_TABLES) */ -/* -* We use a free bit in the genmask field to indicate the element -* is busy, meaning it is currently being processed either by -* the netlink API or GC. -* -* Even though the genmask is only a single byte wide, this works -* because the extension structure if fully constant once initialized, -* so there are no non-atomic write accesses unless it is already -* marked busy. -*/ -#define NFT_SET_ELEM_BUSY_MASK (1 << 2) - -#if defined(__LITTLE_ENDIAN_BITFIELD) -#define NFT_SET_ELEM_BUSY_BIT 2 -#elif defined(__BIG_ENDIAN_BITFIELD) -#define NFT_SET_ELEM_BUSY_BIT (BITS_PER_LONG - BITS_PER_BYTE + 2) -#else -#error -#endif - -static inline int nft_set_elem_mark_busy (struct nft_set_ext *ext) -{ -unsigned long *word = (unsigned long *)ext; - -BUILD_BUG_ON (offsetof(struct nft_set_ext , genmask) !=0 ); -return test_and_set_bit (NFT_SET_ELEM_BUSY_BIT , word); -} - -static inline void nft_set_elem_clear_busy (struct nft_set_ext *ext) -{ -unsigned long *word = (unsigned long *)ext; - -clear_bit (NFT_SET_ELEM_BUSY_BIT , word); -} - -#define NFT_SET_ELEM_DEAD_MASK (1 << 3) +#define NFT_SET_ELEM_DEAD_MASK (1 << 2)#if defined(__LITTLE_ENDIAN_BITFIELD) -#define NFT_SET_ELEM_DEAD_BIT 3 +#define NFT_SET_ELEM_DEAD_BIT 2#elif defined(__BIG_ENDIAN_BITFIELD) -#define NFT_SET_ELEM_DEAD_BIT (BITS_PER_LONG - BITS_PER_BYTE + 3) +#define NFT_SET_ELEM_DEAD_BIT (BITS_PER_LONG - BITS_PER_BYTE + 2)#else #error #endif
net/netfilter/nf_tables_api.c +1 -47
66 lines not on this page · raw message
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 22/183 netfilter: nf_tables: dont fail inserts if duplicate has expired
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
commit 7845914f45f066497ac75b30c50dbc735e84e884 upstream.
nftables selftests fail:run-tests.sh testcases/sets/0044interval_overlap_0
Expected: 0-2 . 0-3, got:
W: [FAILED] ./testcases/sets/0044interval_overlap_0: got 1
Insertion must ignore duplicate but expired entries.
Moreover, there is a strange asymmetry in nft_pipapo_activate:
It refetches the current element, whereas the other ->activate callbacks (bitmap, hash, rhash, rbtree) use elem->priv.
Same for .remove: other set implementations take elem->priv, nft_pipapo_remove fetches elem->priv, then does a relookup, remove this.
I suspect this was the reason for the change that prompted the removal of the expired check in pipapo_get() in the first place, but skipping exired elements there makes no sense to me, this helper is used for normal get requests, insertions (duplicate check) and deactivate callback.
In first two cases expired elements must be skipped.
For ->deactivate(), this gets called for DELSETELEM, so it seems to me that expired elements should be skipped as well, i.e. delete request should fail with -ENOENT error.
--- net/netfilter/nft_set_pipapo.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-)
net/netfilter/nft_set_pipapo.c +4 -19
@@ -566,6 +566,8 @@ static struct nft_pipapo_elem *pipapo_get(const struct net *net, goto out;if (last) { +if (nft_set_elem_expired (&f->mt[b].e->ext)) + goto next_match;if ((genmask && !nft_set_elem_active (&f->mt[b].e->ext, genmask))) goto next_match;
@@ -600,17 +602,8 @@ static struct nft_pipapo_elem *pipapo_get(const struct net *net,static void *nft_pipapo_get (const struct net *net,const struct nft_set *set,const struct nft_set_elem *elem,unsigned int flags) { -struct nft_pipapo_elem *ret; - - ret =pipapo_get (net, set, (const u8 *)elem->key.val.data, +return pipapo_get (net, set, (const u8 *)elem->key.val.data,nft_genmask_cur (net)); -if (IS_ERR (ret)) -return ret; - -if (nft_set_elem_expired (&ret->ext)) -return ERR_PTR (-ENOENT ); - -return ret; }/**
@@ -1751,11 +1744,7 @@ static void nft_pipapo_activate(const struct net *net,const struct nft_set *set, const struct nft_set_elem *elem) { - struct nft_pipapo_elem *e; - - e =pipapo_get (net, set, (const u8 *)elem->key.val.data,0 ); -if (IS_ERR (e)) -return ; + struct nft_pipapo_elem *e = elem->priv;nft_set_elem_change_active (net, set, &e->ext); }
@@ -1969,10 +1958,6 @@ static void nft_pipapo_remove(const struct net *net, const struct nft_set *set, data = (const u8 *)nft_set_ext_key (&e->ext); - e =pipapo_get (net, set, data,0 ); -if (IS_ERR (e)) -return ; -while ((rules_f0 =pipapo_rules_same_key (m->f, first_rule))) {union nft_pipapo_map_bucket rulemap[NFT_PIPAPO_MAX_FIELDS ];const u8 *match_start, *match_end;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 23/183 netfilter: nf_tables: fix GC transaction races with netns and netlink event exit path
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 6a33d8b73dfac0a41f3877894b38082bd0c9a5bc upstream.
Netlink event path is missing a synchronization point with GC transactions. Add GC sequence number update to netns release path and netlink event path, any GC transaction losing race will be discarded.
--- net/netfilter/nf_tables_api.c | 36 +++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-)
net/netfilter/nf_tables_api.c +32 -4
@@ -9207,6 +9207,22 @@ static void nft_set_commit_update(struct list_head *set_update_list) } } +static unsigned int nft_gc_seq_begin (struct nftables_pernet *nft_net) +{ +unsigned int gc_seq; + +/* Bump gc counter, it becomes odd, this is the busy mark. */ + gc_seq =READ_ONCE (nft_net->gc_seq); +WRITE_ONCE (nft_net->gc_seq, ++gc_seq); + +return gc_seq; +} + +static void nft_gc_seq_end (struct nftables_pernet *nft_net,unsigned int gc_seq) +{ +WRITE_ONCE (nft_net->gc_seq, ++gc_seq); +} +static int nf_tables_commit (struct net *net,struct sk_buff *skb) {struct nftables_pernet *nft_net =nft_pernet (net);
@@ -9292,9 +9308,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb)WRITE_ONCE (nft_net->base_seq, base_seq); -/* Bump gc counter, it becomes odd, this is the busy mark. */ - gc_seq =READ_ONCE (nft_net->gc_seq); -WRITE_ONCE (nft_net->gc_seq, ++gc_seq); + gc_seq =nft_gc_seq_begin (nft_net);/* step 3. Start new generation, rules_gen_X now in use. */ net->nft.gencursor =nft_gencursor_next (net);
@@ -9485,7 +9499,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb)nf_tables_gen_notify (net, skb,NFT_MSG_NEWGEN );nf_tables_commit_audit_log (&adl, nft_net->base_seq); -WRITE_ONCE (nft_net->gc_seq, ++gc_seq); +nft_gc_seq_end (nft_net, gc_seq);nf_tables_commit_release (net);return 0 ;
@@ -10468,6 +10482,7 @@ static int nft_rcv_nl_event(struct notifier_block *this, unsigned long event,struct net *net = n->net;unsigned int deleted;bool restart = false; +unsigned int gc_seq;if (event !=NETLINK_URELEASE || n->protocol !=NETLINK_NETFILTER )return NOTIFY_DONE ;
@@ -10475,6 +10490,9 @@ static int nft_rcv_nl_event(struct notifier_block *this, unsigned long event, nft_net =nft_pernet (net); deleted =0 ;mutex_lock (&nft_net->commit_mutex); + + gc_seq =nft_gc_seq_begin (nft_net); +if (!list_empty (&nf_tables_destroy_list))nf_tables_trans_destroy_flush_work (); again:
@@ -10497,6 +10515,8 @@ static int nft_rcv_nl_event(struct notifier_block *this, unsigned long event,if (restart) goto again; } +nft_gc_seq_end (nft_net, gc_seq); +mutex_unlock (&nft_net->commit_mutex);return NOTIFY_DONE ;
@@ -10535,12 +10555,20 @@ static void __net_exit nf_tables_pre_exit_net(struct net *net) static void __net_exit nf_tables_exit_net(struct net *net) {struct nftables_pernet *nft_net =nft_pernet (net); +unsigned int gc_seq;mutex_lock (&nft_net->commit_mutex); + + gc_seq =nft_gc_seq_begin (nft_net); +if (!list_empty (&nft_net->commit_list) || !list_empty (&nft_net->module_list))__nf_tables_abort (net,NFNL_ABORT_NONE ); +__nft_release_tables (net); + +nft_gc_seq_end (nft_net, gc_seq); +mutex_unlock (&nft_net->commit_mutex);WARN_ON_ONCE (!list_empty (&nft_net->tables));WARN_ON_ONCE (!list_empty (&nft_net->module_list));
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 24/183 netfilter: nf_tables: GC transaction race with netns dismantle
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 02c6c24402bf1c1e986899c14ba22a10b510916b upstream.
Use maybe_get_net() since GC workqueue might race with netns exit path.
--- net/netfilter/nf_tables_api.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
net/netfilter/nf_tables_api.c +6 -1
@@ -8949,9 +8949,14 @@ struct nft_trans_gc *nft_trans_gc_alloc(struct nft_set *set,if (!trans)return NULL ; + trans->net =maybe_get_net (net); +if (!trans->net) { +kfree (trans); +return NULL ; + } +refcount_inc (&set->refs); trans->set = set; - trans->net =get_net (net); trans->seq = gc_seq;return trans;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 25/183 netfilter: nf_tables: GC transaction race with abort path
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 720344340fb9be2765bbaab7b292ece0a4570eae upstream.
Abort path is missing a synchronization point with GC transactions. Add GC sequence number hence any GC transaction losing race will be discarded.
--- net/netfilter/nf_tables_api.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
net/netfilter/nf_tables_api.c +6 -1
@@ -9763,7 +9763,12 @@ static int nf_tables_abort(struct net *net, struct sk_buff *skb, enum nfnl_abort_action action) {struct nftables_pernet *nft_net =nft_pernet (net); -int ret =__nf_tables_abort (net, action); +unsigned int gc_seq; +int ret; + + gc_seq =nft_gc_seq_begin (nft_net); + ret =__nf_tables_abort (net, action); +nft_gc_seq_end (nft_net, gc_seq);mutex_unlock (&nft_net->commit_mutex);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 26/183 netfilter: nf_tables: use correct lock to protect gc_list
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 8357bc946a2abc2a10ca40e5a2105d2b4c57515e upstream.
Use nf_tables_gc_list_lock spinlock, not nf_tables_destroy_list_lock to protect the gc_list.
--- net/netfilter/nf_tables_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
net/netfilter/nf_tables_api.c +2 -2
@@ -8925,9 +8925,9 @@ static void nft_trans_gc_work(struct work_struct *work)struct nft_trans_gc *trans, *next;LIST_HEAD (trans_gc_list); -spin_lock (&nf_tables_destroy_list_lock); +spin_lock (&nf_tables_gc_list_lock);list_splice_init (&nf_tables_gc_list, &trans_gc_list); -spin_unlock (&nf_tables_destroy_list_lock); +spin_unlock (&nf_tables_gc_list_lock);list_for_each_entry_safe (trans, next, &trans_gc_list, list) {list_del (&trans->list);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 27/183 netfilter: nf_tables: defer gc run if previous batch is still pending
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
commit 8e51830e29e12670b4c10df070a4ea4c9593e961 upstream.
Don't queue more gc work, else we may queue the same elements multiple times.
If an element is flagged as dead, this can mean that either the previous gc request was invalidated/discarded by a transaction or that the previous request is still pending in the system work queue.
The latter will happen if the gc interval is set to a very low value, e.g. 1ms, and system work queue is backlogged.
The sets refcount is 1 if no previous gc requeusts are queued, so add a helper for this and skip gc run if old requests are pending.
Add a helper for this and skip the gc run in this case.
--- include/net/netfilter/nf_tables.h | 5 +++++ net/netfilter/nft_set_hash.c | 3 +++ net/netfilter/nft_set_rbtree.c | 3 +++ 3 files changed, 11 insertions(+)
include/net/netfilter/nf_tables.h +5 -0
@@ -551,6 +551,11 @@ static inline void *nft_set_priv(const struct nft_set *set)return (void *)set->data; } +static inline bool nft_set_gc_is_pending (const struct nft_set *s) +{ +return refcount_read (&s->refs) !=1 ; +} +static inline struct nft_set *nft_set_container_of (const void *priv) {return (void *)priv - offsetof(struct nft_set , data);
net/netfilter/nft_set_hash.c +3 -0
@@ -326,6 +326,9 @@ static void nft_rhash_gc(struct work_struct *work) nft_net =nft_pernet (net); gc_seq =READ_ONCE (nft_net->gc_seq); +if (nft_set_gc_is_pending (set)) + goto done; + gc =nft_trans_gc_alloc (set, gc_seq,GFP_KERNEL );if (!gc) goto done;
net/netfilter/nft_set_rbtree.c +3 -0
@@ -611,6 +611,9 @@ static void nft_rbtree_gc(struct work_struct *work) nft_net =nft_pernet (net); gc_seq =READ_ONCE (nft_net->gc_seq); +if (nft_set_gc_is_pending (set)) + goto done; + gc =nft_trans_gc_alloc (set, gc_seq,GFP_KERNEL );if (!gc) goto done;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 28/183 netfilter: nft_set_rbtree: skip sync GC for new elements in this transaction
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 2ee52ae94baabf7ee09cf2a8d854b990dac5d0e4 upstream.
New elements in this transaction might expired before such transaction ends. Skip sync GC for such elements otherwise commit path might walk over an already released object. Once transaction is finished, async GC will collect such expired element.
--- net/netfilter/nft_set_rbtree.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
net/netfilter/nft_set_rbtree.c +6 -2
@@ -312,6 +312,7 @@ static int __nft_rbtree_insert(const struct net *net, const struct nft_set *set,struct nft_rbtree_elem *rbe, *rbe_le =NULL , *rbe_ge =NULL ;struct rb_node *node, *next, *parent, **p, *first =NULL ;struct nft_rbtree *priv =nft_set_priv (set); +u8 cur_genmask =nft_genmask_cur (net);u8 genmask =nft_genmask_next (net);int d, err;
@@ -357,8 +358,11 @@ static int __nft_rbtree_insert(const struct net *net, const struct nft_set *set,if (!nft_set_elem_active (&rbe->ext, genmask))continue ; -/* perform garbage collection to avoid bogus overlap reports. */ -if (nft_set_elem_expired (&rbe->ext)) { +/* perform garbage collection to avoid bogus overlap reports +* but skip new elements in this transaction. +*/ +if (nft_set_elem_expired (&rbe->ext) && +nft_set_elem_active (&rbe->ext, cur_genmask)) { err =nft_rbtree_gc_elem (set, priv, rbe, genmask);if (err <0 )return err;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 29/183 netfilter: nft_set_rbtree: use read spinlock to avoid datapath contention
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 96b33300fba880ec0eafcf3d82486f3463b4b6da upstream.
rbtree GC does not modify the datastructure, instead it collects expired elements and it enqueues a GC transaction. Use a read spinlock instead to avoid data contention while GC worker is running.
--- net/netfilter/nft_set_rbtree.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
net/netfilter/nft_set_rbtree.c +2 -4
@@ -622,8 +622,7 @@ static void nft_rbtree_gc(struct work_struct *work)if (!gc) goto done; -write_lock_bh (&priv->lock); -write_seqcount_begin (&priv->count); +read_lock_bh (&priv->lock);for (node =rb_first (&priv->root); node !=NULL ; node =rb_next (node)) {/* Ruleset has been updated, try later. */
@@ -673,8 +672,7 @@ static void nft_rbtree_gc(struct work_struct *work) gc =nft_trans_gc_catchall (gc, gc_seq); try_later: -write_seqcount_end (&priv->count); -write_unlock_bh (&priv->lock); +read_unlock_bh (&priv->lock);if (gc)nft_trans_gc_queue_async_done (gc);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 30/183 netfilter: nft_set_pipapo: call nft_trans_gc_queue_sync() in catchall GC
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 4a9e12ea7e70223555ec010bec9f711089ce96f6 upstream.
pipapo needs to enqueue GC transactions for catchall elements through nft_trans_gc_queue_sync(). Add nft_trans_gc_catchall_sync() and nft_trans_gc_catchall_async() to handle GC transaction queueing accordingly.
--- include/net/netfilter/nf_tables.h | 5 +++-- net/netfilter/nf_tables_api.c | 22 +++++++++++++++++++--- net/netfilter/nft_set_hash.c | 2 +- net/netfilter/nft_set_pipapo.c | 2 +- net/netfilter/nft_set_rbtree.c | 2 +- 5 files changed, 25 insertions(+), 8 deletions(-)
include/net/netfilter/nf_tables.h +3 -2
@@ -1623,8 +1623,9 @@ void nft_trans_gc_queue_sync_done(struct nft_trans_gc *trans);void nft_trans_gc_elem_add (struct nft_trans_gc *gc,void *priv); -struct nft_trans_gc *nft_trans_gc_catchall (struct nft_trans_gc *gc, -unsigned int gc_seq); +struct nft_trans_gc *nft_trans_gc_catchall_async (struct nft_trans_gc *gc, +unsigned int gc_seq); +struct nft_trans_gc *nft_trans_gc_catchall_sync (struct nft_trans_gc *gc); void nft_setelem_data_deactivate(const struct net *net, const struct nft_set *set,
net/netfilter/nf_tables_api.c +19 -3
@@ -9027,8 +9027,9 @@ void nft_trans_gc_queue_sync_done(struct nft_trans_gc *trans)call_rcu (&trans->rcu, nft_trans_gc_trans_free); } -struct nft_trans_gc *nft_trans_gc_catchall (struct nft_trans_gc *gc, -unsigned int gc_seq) +static struct nft_trans_gc *nft_trans_gc_catchall (struct nft_trans_gc *gc, +unsigned int gc_seq, +bool sync) {struct nft_set_elem_catchall *catchall;const struct nft_set *set = gc->set;
@@ -9044,7 +9045,11 @@ struct nft_trans_gc *nft_trans_gc_catchall(struct nft_trans_gc *gc,nft_set_elem_dead (ext); dead_elem: - gc =nft_trans_gc_queue_async (gc, gc_seq,GFP_ATOMIC ); +if (sync) + gc =nft_trans_gc_queue_sync (gc,GFP_ATOMIC ); +else + gc =nft_trans_gc_queue_async (gc, gc_seq,GFP_ATOMIC ); +if (!gc)return NULL ;
@@ -9054,6 +9059,17 @@ struct nft_trans_gc *nft_trans_gc_catchall(struct nft_trans_gc *gc,return gc; } +struct nft_trans_gc *nft_trans_gc_catchall_async (struct nft_trans_gc *gc, +unsigned int gc_seq) +{ +return nft_trans_gc_catchall (gc, gc_seq, false); +} + +struct nft_trans_gc *nft_trans_gc_catchall_sync (struct nft_trans_gc *gc) +{ +return nft_trans_gc_catchall (gc,0 , true); +} +static void nf_tables_module_autoload_cleanup (struct net *net) {struct nftables_pernet *nft_net =nft_pernet (net);
net/netfilter/nft_set_hash.c +1 -1
@@ -372,7 +372,7 @@ static void nft_rhash_gc(struct work_struct *work)nft_trans_gc_elem_add (gc, he); } - gc =nft_trans_gc_catchall (gc, gc_seq); + gc =nft_trans_gc_catchall_async (gc, gc_seq); try_later:/* catchall list iteration requires rcu read side lock. */
net/netfilter/nft_set_pipapo.c +1 -1
@@ -1611,7 +1611,7 @@ static void pipapo_gc(const struct nft_set *_set, struct nft_pipapo_match *m) } } - gc =nft_trans_gc_catchall (gc,0 ); + gc =nft_trans_gc_catchall_sync (gc);if (gc) {nft_trans_gc_queue_sync_done (gc); priv->last_gc = jiffies;
net/netfilter/nft_set_rbtree.c +1 -1
@@ -669,7 +669,7 @@ static void nft_rbtree_gc(struct work_struct *work)nft_trans_gc_elem_add (gc, rbe); } - gc =nft_trans_gc_catchall (gc, gc_seq); + gc =nft_trans_gc_catchall_async (gc, gc_seq); try_later:read_unlock_bh (&priv->lock);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 31/183 netfilter: nft_set_pipapo: stop GC iteration if GC transaction allocation fails
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit 6d365eabce3c018a80f6e0379b17df2abb17405e upstream.
nft_trans_gc_queue_sync() enqueues the GC transaction and it allocates a new one. If this allocation fails, then stop this GC sync run and retry later.
--- net/netfilter/nft_set_pipapo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
net/netfilter/nft_set_pipapo.c +1 -1
@@ -1597,7 +1597,7 @@ static void pipapo_gc(const struct nft_set *_set, struct nft_pipapo_match *m) gc =nft_trans_gc_queue_sync (gc,GFP_ATOMIC );if (!gc) -break ; +return ;nft_pipapo_gc_deactivate (net, set, e);pipapo_drop (m, rulemap);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 32/183 netfilter: nft_set_hash: try later when GC hits EAGAIN on iteration
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
commit b079155faae94e9b3ab9337e82100a914ebb4e8d upstream.
Skip GC run if iterator rewinds to the beginning with EAGAIN, otherwise GC might collect the same element more than once.
--- net/netfilter/nft_set_hash.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
net/netfilter/nft_set_hash.c +3 -6
@@ -338,12 +338,9 @@ static void nft_rhash_gc(struct work_struct *work)while ((he =rhashtable_walk_next (&hti))) {if (IS_ERR (he)) { -if (PTR_ERR (he) != -EAGAIN ) { -nft_trans_gc_destroy (gc); - gc =NULL ; - goto try_later; - } -continue ; +nft_trans_gc_destroy (gc); + gc =NULL ; + goto try_later; }/* Ruleset has been updated, try later. */
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 33/183 netfilter: nf_tables: fix memleak when more than 255 elements expired
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
commit cf5000a7787cbc10341091d37245a42c119d26c5 upstream.
When more than 255 elements expired we're supposed to switch to a new gc container structure.
This never happens: u8 type will wrap before reaching the boundary and nft_trans_gc_space() always returns true.
This means we recycle the initial gc container structure and lose track of the elements that came before.
While at it, don't deref 'gc' after we've passed it to call_rcu.
--- include/net/netfilter/nf_tables.h | 2 +- net/netfilter/nf_tables_api.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-)
include/net/netfilter/nf_tables.h +1 -1
@@ -1605,7 +1605,7 @@ struct nft_trans_gc {struct net *net;struct nft_set *set;u32 seq; -u8 count; +u16 count;void *priv[NFT_TRANS_GC_BATCHCOUNT ];struct rcu_head rcu; };
net/netfilter/nf_tables_api.c +8 -2
@@ -8984,12 +8984,15 @@ static int nft_trans_gc_space(struct nft_trans_gc *trans)struct nft_trans_gc *nft_trans_gc_queue_async (struct nft_trans_gc *gc,unsigned int gc_seq,gfp_t gfp) { +struct nft_set *set; +if (nft_trans_gc_space (gc))return gc; + set = gc->set;nft_trans_gc_queue_work (gc); -return nft_trans_gc_alloc (gc->set, gc_seq, gfp); +return nft_trans_gc_alloc (set, gc_seq, gfp); }void nft_trans_gc_queue_async_done (struct nft_trans_gc *trans)
@@ -9004,15 +9007,18 @@ void nft_trans_gc_queue_async_done(struct nft_trans_gc *trans)struct nft_trans_gc *nft_trans_gc_queue_sync (struct nft_trans_gc *gc,gfp_t gfp) { +struct nft_set *set; +if (WARN_ON_ONCE (!lockdep_commit_lock_is_held (gc->net)))return NULL ;if (nft_trans_gc_space (gc))return gc; + set = gc->set;call_rcu (&gc->rcu, nft_trans_gc_trans_free); -return nft_trans_gc_alloc (gc->set,0 , gfp); +return nft_trans_gc_alloc (set,0 , gfp); }void nft_trans_gc_queue_sync_done (struct nft_trans_gc *trans)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 34/183 ASoC: meson: spdifin: start hw on dai probe
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jerome Brunet <[email protected]>
[ Upstream commit aedf323b66b2b875137422ecb7d2525179759076 ]
For spdif input to report the locked rate correctly, even when no capture is running, the HW and reference clock must be started as soon as the dai is probed.
--- sound/soc/meson/axg-spdifin.c | 49 ++++++++++++----------------------- 1 file changed, 17 insertions(+), 32 deletions(-)
sound/soc/meson/axg-spdifin.c +17 -32
@@ -112,34 +112,6 @@ static int axg_spdifin_prepare(struct snd_pcm_substream *substream,return 0 ; } -static int axg_spdifin_startup (struct snd_pcm_substream *substream, -struct snd_soc_dai *dai) -{ -struct axg_spdifin *priv =snd_soc_dai_get_drvdata (dai); -int ret; - - ret =clk_prepare_enable (priv->refclk); -if (ret) { -dev_err (dai->dev, -"failed to enable spdifin reference clock\n" ); -return ret; - } - -regmap_update_bits (priv->map,SPDIFIN_CTRL0 ,SPDIFIN_CTRL0_EN , -SPDIFIN_CTRL0_EN ); - -return 0 ; -} - -static void axg_spdifin_shutdown (struct snd_pcm_substream *substream, -struct snd_soc_dai *dai) -{ -struct axg_spdifin *priv =snd_soc_dai_get_drvdata (dai); - -regmap_update_bits (priv->map,SPDIFIN_CTRL0 ,SPDIFIN_CTRL0_EN ,0 ); -clk_disable_unprepare (priv->refclk); -} - static void axg_spdifin_write_mode_param(struct regmap *map, int mode, unsigned int val, unsigned int num_per_reg,
@@ -251,25 +223,38 @@ static int axg_spdifin_dai_probe(struct snd_soc_dai *dai) ret =axg_spdifin_sample_mode_config (dai, priv);if (ret) {dev_err (dai->dev,"mode configuration failed\n" ); -clk_disable_unprepare (priv->pclk); -return ret; + goto pclk_err; } + ret =clk_prepare_enable (priv->refclk); +if (ret) { +dev_err (dai->dev, +"failed to enable spdifin reference clock\n" ); + goto pclk_err; + } + +regmap_update_bits (priv->map,SPDIFIN_CTRL0 ,SPDIFIN_CTRL0_EN , +SPDIFIN_CTRL0_EN ); +return 0 ; + +pclk_err: +clk_disable_unprepare (priv->pclk); +return ret; }static int axg_spdifin_dai_remove (struct snd_soc_dai *dai) {struct axg_spdifin *priv =snd_soc_dai_get_drvdata (dai); +regmap_update_bits (priv->map,SPDIFIN_CTRL0 ,SPDIFIN_CTRL0_EN ,0 ); +clk_disable_unprepare (priv->refclk);clk_disable_unprepare (priv->pclk);return 0 ; }static const struct snd_soc_dai_ops axg_spdifin_ops = { .prepare = axg_spdifin_prepare, - .startup = axg_spdifin_startup, - .shutdown = axg_spdifin_shutdown, }; static int axg_spdifin_iec958_info(struct snd_kcontrol *kcontrol,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 35/183 netfilter: nf_tables: disallow element removal on anonymous sets
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Pablo Neira Ayuso <[email protected]>
[ Upstream commit 23a3bfd4ba7acd36abf52b78605f61b21bdac216 ]
Anonymous sets need to be populated once at creation and then they are bound to rule since 938154b93be8 ("netfilter: nf_tables: reject unbound anonymous set before commit phase"), otherwise transaction reports EINVAL.
Userspace does not need to delete elements of anonymous sets that are not yet bound, reject this with EOPNOTSUPP.
Quoted 1 line
From flush command path, skip anonymous sets, they are expected to be
bound already. Otherwise, EINVAL is hit at the end of this transaction for unbound sets.
--- net/netfilter/nf_tables_api.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
net/netfilter/nf_tables_api.c +5 -4
@@ -1358,8 +1358,7 @@ static int nft_flush_table(struct nft_ctx *ctx)if (!nft_is_active_next (ctx->net, set))continue ; -if (nft_set_is_anonymous (set) && - !list_empty (&set->bindings)) +if (nft_set_is_anonymous (set))continue ; err =nft_delset (ctx, set);
@@ -6752,8 +6751,10 @@ static int nf_tables_delsetelem(struct sk_buff *skb,if (IS_ERR (set))return PTR_ERR (set); -if (!list_empty (&set->bindings) && - (set->flags & (NFT_SET_CONSTANT |NFT_SET_ANONYMOUS ))) +if (nft_set_is_anonymous (set)) +return -EOPNOTSUPP ; + +if (!list_empty (&set->bindings) && (set->flags &NFT_SET_CONSTANT ))return -EBUSY ;nft_ctx_init (&ctx, net, skb, info->nlh, family, table,NULL , nla);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 36/183 bpf: Avoid deadlock when using queue and stack maps from NMI
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Toke Høiland-Jørgensen <[email protected]>
[ Upstream commit a34a9f1a19afe9c60ca0ea61dfeee63a1c2baac8 ]
Sysbot discovered that the queue and stack maps can deadlock if they are being used from a BPF program that can be called from NMI context (such as one that is attached to a perf HW counter event). To fix this, add an in_nmi() check and use raw_spin_trylock() in NMI context, erroring out if grabbing the lock fails.
--- kernel/bpf/queue_stack_maps.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-)
kernel/bpf/queue_stack_maps.c +18 -3
@@ -103,7 +103,12 @@ static int __queue_map_get(struct bpf_map *map, void *value, bool delete)int err =0 ;void *ptr; -raw_spin_lock_irqsave (&qs->lock, flags); +if (in_nmi ()) { +if (!raw_spin_trylock_irqsave (&qs->lock, flags)) +return -EBUSY ; + }else { +raw_spin_lock_irqsave (&qs->lock, flags); + }if (queue_stack_map_is_empty (qs)) {memset (value,0 , qs->map.value_size);
@@ -133,7 +138,12 @@ static int __stack_map_get(struct bpf_map *map, void *value, bool delete)void *ptr;u32 index; -raw_spin_lock_irqsave (&qs->lock, flags); +if (in_nmi ()) { +if (!raw_spin_trylock_irqsave (&qs->lock, flags)) +return -EBUSY ; + }else { +raw_spin_lock_irqsave (&qs->lock, flags); + }if (queue_stack_map_is_empty (qs)) {memset (value,0 , qs->map.value_size);
@@ -198,7 +208,12 @@ static int queue_stack_map_push_elem(struct bpf_map *map, void *value,if (flags &BPF_NOEXIST || flags >BPF_EXIST )return -EINVAL ; -raw_spin_lock_irqsave (&qs->lock, irq_flags); +if (in_nmi ()) { +if (!raw_spin_trylock_irqsave (&qs->lock, irq_flags)) +return -EBUSY ; + }else { +raw_spin_lock_irqsave (&qs->lock, irq_flags); + }if (queue_stack_map_is_full (qs)) {if (!replace) {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 37/183 selftests: tls: swap the TX and RX sockets in some tests
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sabrina Dubroca <[email protected]>
[ Upstream commit c326ca98446e0ae4fee43a40acf79412b74cfedb ]
tls.sendmsg_large and tls.sendmsg_multiple are trying to send through the self->cfd socket (only configured with TLS_RX) and to receive through the self->fd socket (only configured with TLS_TX), so they're not using kTLS at all. Swap the sockets.
--- tools/testing/selftests/net/tls.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
tools/testing/selftests/net/tls.c +4 -4
@@ -441,11 +441,11 @@ TEST_F(tls, sendmsg_large) msg.msg_iov = &vec; msg.msg_iovlen =1 ; -EXPECT_EQ (sendmsg (self->cfd, &msg,0 ), send_len); +EXPECT_EQ (sendmsg (self->fd, &msg,0 ), send_len); }while (recvs++ < sends) { -EXPECT_NE (recv (self->fd, mem, send_len,0 ),-1 ); +EXPECT_NE (recv (self->cfd, mem, send_len,0 ),-1 ); }free (mem);
@@ -474,9 +474,9 @@ TEST_F(tls, sendmsg_multiple) msg.msg_iov = vec; msg.msg_iovlen = iov_len; -EXPECT_EQ (sendmsg (self->cfd, &msg,0 ), total_len); +EXPECT_EQ (sendmsg (self->fd, &msg,0 ), total_len); buf =malloc (total_len); -EXPECT_NE (recv (self->fd, buf, total_len,0 ),-1 ); +EXPECT_NE (recv (self->cfd, buf, total_len,0 ),-1 );for (i =0 ; i < iov_len; i++) { EXPECT_EQ(memcmp(test_strs[i], buf + len_cmp, strlen(test_strs[i])),
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 38/183 net/core: Fix ETH_P_1588 flow dissector
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sasha Neftin <[email protected]>
[ Upstream commit 75ad80ed88a182ab2ad5513e448cf07b403af5c3 ]
When a PTP ethernet raw frame with a size of more than 256 bytes followed by a 0xff pattern is sent to __skb_flow_dissect, nhoff value calculation is wrong. For example: hdr->message_length takes the wrong value (0xffff) and it does not replicate real header length. In this case, 'nhoff' value was overridden and the PTP header was badly dissected. This leads to a kernel crash.
net/core: flow_dissector
net/core flow dissector nhoff = 0x0000000e net/core flow dissector hdr->message_length = 0x0000ffff net/core flow dissector nhoff = 0x0001000d (u16 overflow)
...
skb linear: 00000000: 00 a0 c9 00 00 00 00 a0 c9 00 00 00 88 skb frag: 00000000: f7 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Using the size of the ptp_header struct will allow the corrected calculation of the nhoff value.
net/core flow dissector nhoff = 0x0000000e
net/core flow dissector nhoff = 0x00000030 (sizeof ptp_header)
...
skb linear: 00000000: 00 a0 c9 00 00 00 00 a0 c9 00 00 00 88 f7 ff ff skb linear: 00000010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff skb linear: 00000020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff skb frag: 00000000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Kernel trace:
[ 74.984279] ------------[ cut here ]------------ [ 74.989471] kernel BUG at include/linux/skbuff.h:2440! [ 74.995237] invalid opcode: 0000 [#1] PREEMPT SMP NOPTI [ 75.001098] CPU: 4 PID: 0 Comm: swapper/4 Tainted: G U 5.15.85-intel-ese-standard-lts #1 [ 75.011629] Hardware name: Intel Corporation A-Island (CPU:AlderLake)/A-Island (ID:06), BIOS SB_ADLP.01.01.00.01.03.008.D-6A9D9E73-dirty Mar 30 2023 [ 75.026507] RIP: 0010:eth_type_trans+0xd0/0x130 [ 75.031594] Code: 03 88 47 78 eb c7 8b 47 68 2b 47 6c 48 8b 97 c0 00 00 00 83 f8 01 7e 1b 48 85 d2 74 06 66 83 3a ff 74 09 b8 00 04 00 00 eb ab <0f> 0b b8 00 01 00 00 eb a2 48 85 ff 74 eb 48 8d 54 24 06 31 f6 b9 [ 75.052612] RSP: 0018:ffff9948c0228de0 EFLAGS: 00010297 [ 75.058473] RAX: 00000000000003f2 RBX: ffff8e47047dc300 RCX: 0000000000001003 [ 75.066462] RDX: ffff8e4e8c9ea040 RSI: ffff8e4704e0a000 RDI: ffff8e47047dc300 [ 75.074458] RBP: ffff8e4704e2acc0 R08: 00000000000003f3 R09: 0000000000000800 [ 75.082466] R10: 000000000000000d R11: ffff9948c0228dec R12: ffff8e4715e4e010 [ 75.090461] R13: ffff9948c0545018 R14: 0000000000000001 R15: 0000000000000800 [ 75.098464] FS: 0000000000000000(0000) GS:ffff8e4e8fb00000(0000) knlGS:0000000000000000 [ 75.107530] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 75.113982] CR2: 00007f5eb35934a0 CR3: 0000000150e0a002 CR4: 0000000000770ee0 [ 75.121980] PKRU: 55555554 [ 75.125035] Call Trace: [ 75.127792] <IRQ> [ 75.130063] ? eth_get_headlen+0xa4/0xc0 [ 75.134472] igc_process_skb_fields+0xcd/0x150 [ 75.139461] igc_poll+0xc80/0x17b0 [ 75.143272] __napi_poll+0x27/0x170 [ 75.147192] net_rx_action+0x234/0x280 [ 75.151409] __do_softirq+0xef/0x2f4 [ 75.155424] irq_exit_rcu+0xc7/0x110 [ 75.159432] common_interrupt+0xb8/0xd0 [ 75.163748] </IRQ> [ 75.166112] <TASK> [ 75.168473] asm_common_interrupt+0x22/0x40 [ 75.173175] RIP: 0010:cpuidle_enter_state+0xe2/0x350 [ 75.178749] Code: 85 c0 0f 8f 04 02 00 00 31 ff e8 39 6c 67 ff 45 84 ff 74 12 9c 58 f6 c4 02 0f 85 50 02 00 00 31 ff e8 52 b0 6d ff fb 45 85 f6 <0f> 88 b1 00 00 00 49 63 ce 4c 2b 2c 24 48 89 c8 48 6b d1 68 48 c1 [ 75.199757] RSP: 0018:ffff9948c013bea8 EFLAGS: 00000202 [ 75.205614] RAX: ffff8e4e8fb00000 RBX: ffffb948bfd23900 RCX: 000000000000001f [ 75.213619] RDX: 0000000000000004 RSI: ffffffff94206161 RDI: ffffffff94212e20 [ 75.221620] RBP: 0000000000000004 R08: 000000117568973a R09: 0000000000000001 [ 75.229622] R10: 000000000000afc8 R11: ffff8e4e8fb29ce4 R12: ffffffff945ae980 [ 75.237628] R13: 000000117568973a R14: 0000000000000004 R15: 0000000000000000 [ 75.245635] ? cpuidle_enter_state+0xc7/0x350 [ 75.250518] cpuidle_enter+0x29/0x40 [ 75.254539] do_idle+0x1d9/0x260 [ 75.258166] cpu_startup_entry+0x19/0x20 [ 75.262582] secondary_startup_64_no_verify+0xc2/0xcb [ 75.268259] </TASK> [ 75.270721] Modules linked in: 8021q snd_sof_pci_intel_tgl snd_sof_intel_hda_common tpm_crb snd_soc_hdac_hda snd_sof_intel_hda snd_hda_ext_core snd_sof_pci snd_sof snd_sof_xtensa_dsp snd_soc_acpi_intel_match snd_soc_acpi snd_soc_core snd_compress iTCO_wdt ac97_bus intel_pmc_bxt mei_hdcp iTCO_vendor_support snd_hda_codec_hdmi pmt_telemetry intel_pmc_core pmt_class snd_hda_intel x86_pkg_temp_thermal snd_intel_dspcfg snd_hda_codec snd_hda_core kvm_intel snd_pcm snd_timer kvm snd mei_me soundcore tpm_tis irqbypass i2c_i801 mei tpm_tis_core pcspkr intel_rapl_msr tpm i2c_smbus intel_pmt thermal sch_fq_codel uio uhid i915 drm_buddy video drm_display_helper drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm fuse configfs [ 75.342736] ---[ end trace 3785f9f360400e3a ]--- [ 75.347913] RIP: 0010:eth_type_trans+0xd0/0x130 [ 75.352984] Code: 03 88 47 78 eb c7 8b 47 68 2b 47 6c 48 8b 97 c0 00 00 00 83 f8 01 7e 1b 48 85 d2 74 06 66 83 3a ff 74 09 b8 00 04 00 00 eb ab <0f> 0b b8 00 01 00 00 eb a2 48 85 ff 74 eb 48 8d 54 24 06 31 f6 b9 [ 75.373994] RSP: 0018:ffff9948c0228de0 EFLAGS: 00010297 [ 75.379860] RAX: 00000000000003f2 RBX: ffff8e47047dc300 RCX: 0000000000001003 [ 75.387856] RDX: ffff8e4e8c9ea040 RSI: ffff8e4704e0a000 RDI: ffff8e47047dc300 [ 75.395864] RBP: ffff8e4704e2acc0 R08: 00000000000003f3 R09: 0000000000000800 [ 75.403857] R10: 000000000000000d R11: ffff9948c0228dec R12: ffff8e4715e4e010 [ 75.411863] R13: ffff9948c0545018 R14: 0000000000000001 R15: 0000000000000800 [ 75.419875] FS: 0000000000000000(0000) GS:ffff8e4e8fb00000(0000) knlGS:0000000000000000 [ 75.428946] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 75.435403] CR2: 00007f5eb35934a0 CR3: 0000000150e0a002 CR4: 0000000000770ee0 [ 75.443410] PKRU: 55555554 [ 75.446477] Kernel panic - not syncing: Fatal exception in interrupt [ 75.453738] Kernel Offset: 0x11c00000 from 0xffffffff81000000 (relocation range: 0xffffffff80000000-0xffffffffbfffffff) [ 75.465794] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]---
--- net/core/flow_dissector.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
net/core/flow_dissector.c +1 -1
@@ -1278,7 +1278,7 @@ bool __skb_flow_dissect(const struct net *net,break ; } - nhoff +=ntohs (hdr->message_length); + nhoff +=sizeof (struct ptp_header ); fdret =FLOW_DISSECT_RET_OUT_GOOD ;break ; }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 39/183 ASoC: imx-audmix: Fix return error with devm_clk_get()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Shengjiu Wang <[email protected]>
[ Upstream commit b19a5733de255cabba5feecabf6e900638b582d1 ]
The devm_clk_get() can return -EPROBE_DEFER error, modify the error code to be -EINVAL is not correct, which cause the -EPROBE_DEFER error is not correctly handled.
This patch is to fix the return error code.
--- sound/soc/fsl/imx-audmix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
sound/soc/fsl/imx-audmix.c +1 -1
@@ -320,7 +320,7 @@ static int imx_audmix_probe(struct platform_device *pdev)if (IS_ERR (priv->cpu_mclk)) { ret =PTR_ERR (priv->cpu_mclk);dev_err (&cpu_pdev->dev,"failed to get DAI mclk1: %d\n" , ret); -return -EINVAL ; +return ret; } priv->audmix_pdev = audmix_pdev;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 40/183 iavf: do not process adminq tasks when __IAVF_IN_REMOVE_TASK is set
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Radoslaw Tyl <[email protected]>
[ Upstream commit c8de44b577eb540e8bfea55afe1d0904bb571b7a ]
Prevent schedule operations for adminq during device remove and when __IAVF_IN_REMOVE_TASK flag is set. Currently, the iavf_down function adds operations for adminq that shouldn't be processed when the device is in the __IAVF_REMOVE state.
Reproduction:
echo 4 > /sys/bus/pci/devices/0000:17:00.0/sriov_numvfs ip link set dev ens1f0 vf 0 trust on
ip link set dev ens1f0 vf 1 trust on
ip link set dev ens1f0 vf 2 trust on
ip link set dev ens1f0 vf 3 trust on
ip link set dev ens1f0 vf 0 mac 00:22:33:44:55:66
ip link set dev ens1f0 vf 1 mac 00:22:33:44:55:67
ip link set dev ens1f0 vf 2 mac 00:22:33:44:55:68
ip link set dev ens1f0 vf 3 mac 00:22:33:44:55:69
echo 0000:17:02.0 > /sys/bus/pci/devices/0000\:17\:02.0/driver/unbind echo 0000:17:02.1 > /sys/bus/pci/devices/0000\:17\:02.1/driver/unbind echo 0000:17:02.2 > /sys/bus/pci/devices/0000\:17\:02.2/driver/unbind echo 0000:17:02.3 > /sys/bus/pci/devices/0000\:17\:02.3/driver/unbind sleep 10
echo 0000:17:02.0 > /sys/bus/pci/drivers/iavf/bind
echo 0000:17:02.1 > /sys/bus/pci/drivers/iavf/bind
echo 0000:17:02.2 > /sys/bus/pci/drivers/iavf/bind
echo 0000:17:02.3 > /sys/bus/pci/drivers/iavf/bind
modprobe vfio-pci
echo 8086 154c > /sys/bus/pci/drivers/vfio-pci/new_id
qemu-system-x86_64 -accel kvm -m 4096 -cpu host \
-drive file=centos9.qcow2,if=none,id=virtio-disk0 \
-device virtio-blk-pci,drive=virtio-disk0,bootindex=0 -smp 4 \
-device vfio-pci,host=17:02.0 -net none \
-device vfio-pci,host=17:02.1 -net none \
-device vfio-pci,host=17:02.2 -net none \
-device vfio-pci,host=17:02.3 -net none \
-daemonize -vnc :5
Current result:
There is a probability that the mac of VF in guest is inconsistent with it in host
Expected result:
When passthrough NIC VF to guest, the VF in guest should always get the same mac as it in host.
--- drivers/net/ethernet/intel/iavf/iavf_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/net/ethernet/intel/iavf/iavf_main.c +2 -1
@@ -1142,7 +1142,8 @@ void iavf_down(struct iavf_adapter *adapter)iavf_clear_fdir_filters (adapter);iavf_clear_adv_rss_conf (adapter); -if (!(adapter->flags &IAVF_FLAG_PF_COMMS_FAILED )) { +if (!(adapter->flags &IAVF_FLAG_PF_COMMS_FAILED ) && + !(test_bit (__IAVF_IN_REMOVE_TASK, &adapter->crit_section))) {/* cancel any current operation */ adapter->current_op =VIRTCHNL_OP_UNKNOWN ;/* Schedule operations to close down the HW. Don't wait
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 41/183 i40e: Add VF VLAN pruning
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Mateusz Palczewski <[email protected]>
[ Upstream commit c87c938f62d8f1f7c24620859d67f2e3eca23afc ]
VFs by default are able to see all tagged traffic regardless of trust and VLAN filters configured.
Add new private flag vf-vlan-pruning that allows changing of default VF behavior for tagged traffic. When the flag is turned on untrusted VF will only be able to receive untagged traffic or traffic with VLAN tags it has created interfaces for
The flag is off by default and can only be changed if
there are no VFs spawned on the PF. This flag will only be effective when no PVID is set on VF and VF is not trusted.
Add new function that computes the correct VLAN ID for VF VLAN filters based on trust, PVID, vf-vlan-prune-disable flag and current VLAN ID.
Testing Hints:
Test 1: vf-vlan-pruning == off
==============================
1. Set the private flag
Quoted 1 line
ethtool --set-priv-flag eth0 vf-vlan-pruning off (default setting)
2. Use scapy to send any VLAN tagged traffic and make sure the VF receives all VLAN tagged traffic that matches its destination MAC filters (unicast, multicast, and broadcast).
Test 2: vf-vlan-pruning == on
==============================
1. Set the private flag
Quoted 1 line
ethtool --set-priv-flag eth0 vf-vlan-pruning on
2. Use scapy to send any VLAN tagged traffic and make sure the VF does not receive any VLAN tagged traffic that matches its destination MAC filters (unicast, multicast, and broadcast).
3. Add a VLAN filter on the VF netdev
Quoted 1 line
ip link add link eth0v0 name vlan10 type vlan id 10
4. Bring the VLAN netdev up
Quoted 1 line
ip link set vlan10 up
4. Use scapy to send traffic with VLAN 10, VLAN 11 (anything not VLAN 10), and untagged traffic. Make sure the VF only receives VLAN 10 and untagged traffic when the link partner is sending.
Test 3: vf-vlan-pruning == off && VF is in a port VLAN
==============================
1. Set the private flag
Quoted 1 line
ethtool --set-priv-flag eth0 vf-vlan-pruning off (default setting)
2. Create a VF
Quoted 1 line
echo 1 >
sriov_numvfs
3. Put the VF in a port VLAN
Quoted 1 line
ip link set eth0 vf 0 vlan 10
4. Use scapy to send traffic with VLAN 10 and VLAN 11 (anything not VLAN
10) and make sure the VF only receives untagged traffic when the link partner is sending VLAN 10 tagged traffic as the VLAN tag is expected to be stripped by HW for port VLANs and not visible to the VF.
Test 4: Change vf-vlan-pruning while VFs are created
==============================
echo 0 > sriov_numvfs
ethtool --set-priv-flag eth0 vf-vlan-pruning off
echo 1 > sriov_numvfs
ethtool --set-priv-flag eth0 vf-vlan-pruning on (expect failure)
Stable-dep-of: d0d362ffa33d ("i40e: Fix VF VLAN offloading when port VLAN is configured")
--- drivers/net/ethernet/intel/i40e/i40e.h | 1 + .../net/ethernet/intel/i40e/i40e_ethtool.c | 9 ++ drivers/net/ethernet/intel/i40e/i40e_main.c | 135 +++++++++++++++++- .../ethernet/intel/i40e/i40e_virtchnl_pf.c | 8 +- 4 files changed, 147 insertions(+), 6 deletions(-)
drivers/net/ethernet/intel/i40e/i40e.h +1 -0
@@ -566,6 +566,7 @@ struct i40e_pf {#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)#define I40E_FLAG_RS_FEC BIT(25)#define I40E_FLAG_BASE_R_FEC BIT(26) +#define I40E_FLAG_VF_VLAN_PRUNING BIT(27)/* TOTAL_PORT_SHUTDOWN * Allows to physically disable the link on the NIC's port. * If enabled, (after link down request from the OS)
drivers/net/ethernet/intel/i40e/i40e_ethtool.c +9 -0
@@ -451,6 +451,8 @@ static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {I40E_PRIV_FLAG ("disable-fw-lldp" ,I40E_FLAG_DISABLE_FW_LLDP ,0 ),I40E_PRIV_FLAG ("rs-fec" ,I40E_FLAG_RS_FEC ,0 ),I40E_PRIV_FLAG ("base-r-fec" ,I40E_FLAG_BASE_R_FEC ,0 ), +I40E_PRIV_FLAG ("vf-vlan-pruning" , + I40E_FLAG_VF_VLAN_PRUNING, 0), };#define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)
@@ -5293,6 +5295,13 @@ static int i40e_set_priv_flags(struct net_device *dev, u32 flags)return -EOPNOTSUPP ; } +if ((changed_flags &I40E_FLAG_VF_VLAN_PRUNING ) && + pf->num_alloc_vfs) { +dev_warn (&pf->pdev->dev, +"Changing vf-vlan-pruning flag while VF(s) are active is not supported\n" ); +return -EOPNOTSUPP ; + } +if ((changed_flags & new_flags &I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED ) && (new_flags &I40E_FLAG_MFP_ENABLED ))
drivers/net/ethernet/intel/i40e/i40e_main.c +130 -5
154 lines not on this page · raw message
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +7 -1
@@ -4372,6 +4372,7 @@ int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,/* duplicate request, so just return success */ goto error_pvid; +i40e_vlan_stripping_enable (vsi);i40e_vc_reset_vf (vf, true);/* During reset the VF got a new VSI, so refresh a pointer. */ vsi = pf->vsi[vf->lan_vsi_idx];
@@ -4387,7 +4388,7 @@ int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,* MAC addresses deleted. */ if ((!(vlan_id || qos) || - vlanprio !=le16_to_cpu (vsi->info.pvid)) && + vlanprio !=le16_to_cpu (vsi->info.pvid)) && vsi->info.pvid) { ret =i40e_add_vlan_all_mac (vsi,I40E_VLAN_ANY );if (ret) {
@@ -4750,6 +4751,11 @@ int i40e_ndo_set_vf_trust(struct net_device *netdev, int vf_id, bool setting) goto out; vf->trusted = setting; + +/* request PF to sync mac/vlan filters for the VF */ +set_bit (__I40E_MACVLAN_SYNC_PENDING, pf->state); + pf->vsi[vf->lan_vsi_idx]->flags |=I40E_VSI_FLAG_FILTER_CHANGED ; +i40e_vc_reset_vf (vf, true);dev_info (&pf->pdev->dev,"VF %u is now %strusted\n" , vf_id, setting ?"" :"un" );
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 42/183 i40e: Fix VF VLAN offloading when port VLAN is configured
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ivan Vecera <[email protected]>
[ Upstream commit d0d362ffa33da4acdcf7aee2116ceef8c8fef658 ]
If port VLAN is configured on a VF then any other VLANs on top of this VF are broken.
During i40e_ndo_set_vf_port_vlan() call the i40e driver reset the VF and iavf driver asks PF (using VIRTCHNL_OP_GET_VF_RESOURCES) for VF capabilities but this reset occurs too early, prior setting of vf->info.pvid field and because this field can be zero during i40e_vc_get_vf_resources_msg() then VIRTCHNL_VF_OFFLOAD_VLAN capability is reported to iavf driver.
This is wrong because iavf driver should not report VLAN offloading capability when port VLAN is configured as i40e does not support QinQ offloading.
Fix the issue by moving VF reset after setting of vf->port_vlan_id field.
Without this patch:
$ echo 1 > /sys/class/net/enp2s0f0/device/sriov_numvfs $ ip link set enp2s0f0 vf 0 vlan 3 $ ip link set enp2s0f0v0 up $ ip link add link enp2s0f0v0 name vlan4 type vlan id 4 $ ip link set vlan4 up ... $ ethtool -k enp2s0f0v0 | grep vlan-offload rx-vlan-offload: on tx-vlan-offload: on $ dmesg -l err | grep iavf [1292500.742914] iavf 0000:02:02.0: Failed to add VLAN filter, error IAVF_ERR_INVALID_QP_ID
With this patch:
$ echo 1 > /sys/class/net/enp2s0f0/device/sriov_numvfs $ ip link set enp2s0f0 vf 0 vlan 3 $ ip link set enp2s0f0v0 up $ ip link add link enp2s0f0v0 name vlan4 type vlan id 4 $ ip link set vlan4 up ... $ ethtool -k enp2s0f0v0 | grep vlan-offload rx-vlan-offload: off [requested on] tx-vlan-offload: off [requested on] $ dmesg -l err | grep iavf
--- drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +5 -3
@@ -4373,9 +4373,7 @@ int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id, goto error_pvid;i40e_vlan_stripping_enable (vsi); -i40e_vc_reset_vf (vf, true); -/* During reset the VF got a new VSI, so refresh a pointer. */ - vsi = pf->vsi[vf->lan_vsi_idx]; +/* Locked once because multiple functions below iterate list */ spin_lock_bh (&vsi->mac_filter_hash_lock);
@@ -4461,6 +4459,10 @@ int i40e_ndo_set_vf_port_vlan(struct net_device *netdev, int vf_id,*/ vf->port_vlan_id =le16_to_cpu (vsi->info.pvid); +i40e_vc_reset_vf (vf, true); +/* During reset the VF got a new VSI, so refresh a pointer. */ + vsi = pf->vsi[vf->lan_vsi_idx]; + ret =i40e_config_vf_promiscuous_mode (vf, vsi->id, allmulti, alluni);if (ret) {dev_err (&pf->pdev->dev,"Unable to config vf promiscuous mode\n" );
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 43/183 ionic: fix 16bit math issue when PAGE_SIZE >= 64KB
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: David Christensen <[email protected]>
[ Upstream commit 8f6b846b0a86c3cbae8a25b772651cfc2270ad0a ]
The ionic device supports a maximum buffer length of 16 bits (see ionic_rxq_desc or ionic_rxq_sg_elem). When adding new buffers to the receive rings, the function ionic_rx_fill() uses 16bit math when calculating the number of pages to allocate for an RX descriptor, given the interface's MTU setting. If the system PAGE_SIZE >= 64KB, and the buf_info->page_offset is 0, the remain_len value will never decrement from the original MTU value and the frag_len value will always be 0, causing additional pages to be allocated as scatter- gather elements unnecessarily.
A similar math issue exists in ionic_rx_frags(), but no failures have been observed here since a 64KB page should not normally require any scatter-gather elements at any legal Ethernet MTU size.
--- drivers/net/ethernet/pensando/ionic/ionic_dev.h | 1 + drivers/net/ethernet/pensando/ionic/ionic_txrx.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-)
drivers/net/ethernet/pensando/ionic/ionic_dev.h +1 -0
@@ -174,6 +174,7 @@ typedef void (*ionic_desc_cb)(struct ionic_queue *q,struct ionic_desc_info *desc_info, struct ionic_cq_info *cq_info, void *cb_arg); +#define IONIC_MAX_BUF_LEN ((u16)-1)#define IONIC_PAGE_SIZE PAGE_SIZE#define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2)#define IONIC_PAGE_GFP_MASK (GFP_ATOMIC | __GFP_NOWARN |\
drivers/net/ethernet/pensando/ionic/ionic_txrx.c +7 -3
@@ -151,7 +151,8 @@ static struct sk_buff *ionic_rx_frags(struct ionic_queue *q,return NULL ; } - frag_len =min_t (u16, len,IONIC_PAGE_SIZE - buf_info->page_offset); + frag_len =min_t (u16, len,min_t (u32,IONIC_MAX_BUF_LEN , +IONIC_PAGE_SIZE - buf_info->page_offset)); len -= frag_len; dma_sync_single_for_cpu(dev,
@@ -388,7 +389,8 @@ void ionic_rx_fill(struct ionic_queue *q)/* fill main descriptor - buf[0] */ desc->addr =cpu_to_le64 (buf_info->dma_addr + buf_info->page_offset); - frag_len =min_t (u16, len,IONIC_PAGE_SIZE - buf_info->page_offset); + frag_len =min_t (u16, len,min_t (u32,IONIC_MAX_BUF_LEN , +IONIC_PAGE_SIZE - buf_info->page_offset)); desc->len =cpu_to_le16 (frag_len); remain_len -= frag_len; buf_info++;
@@ -407,7 +409,9 @@ void ionic_rx_fill(struct ionic_queue *q) } sg_elem->addr =cpu_to_le64 (buf_info->dma_addr + buf_info->page_offset); - frag_len =min_t (u16, remain_len,IONIC_PAGE_SIZE - buf_info->page_offset); + frag_len =min_t (u16, remain_len,min_t (u32,IONIC_MAX_BUF_LEN , +IONIC_PAGE_SIZE - + buf_info->page_offset)); sg_elem->len =cpu_to_le16 (frag_len); remain_len -= frag_len; buf_info++;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 44/183 igc: Fix infinite initialization loop with early XDP redirect
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Vinicius Costa Gomes <[email protected]>
[ Upstream commit cb47b1f679c4d83a5fa5f1852e472f844e41a3da ]
When an XDP redirect happens before the link is ready, that transmission will not finish and will timeout, causing an adapter reset. If the redirects do not stop, the adapter will not stop resetting.
Wait for the driver to signal that there's a carrier before allowing transmissions to proceed.
Previous code was relying that when __IGC_DOWN is cleared, the NIC is ready to transmit as all the queues are ready, what happens is that the carrier presence will only be signaled later, after the watchdog workqueue has a chance to run. And during this interval (between clearing __IGC_DOWN and the watchdog running) if any transmission happens the timeout is emitted (detected by igc_tx_timeout()) which causes the reset, with the potential for the infinite loop.
--- drivers/net/ethernet/intel/igc/igc_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/net/ethernet/intel/igc/igc_main.c +1 -1
@@ -6271,7 +6271,7 @@ static int igc_xdp_xmit(struct net_device *dev, int num_frames,struct igc_ring *ring;int i, drops; -if (unlikely (test_bit (__IGC_DOWN, &adapter->state))) +if (unlikely (!netif_carrier_ok (dev)))return -ENETDOWN ;if (unlikely (flags & ~XDP_XMIT_FLAGS_MASK ))
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 45/183 ipv4: fix null-deref in ipv4_link_failure
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kyle Zeng <[email protected]>
[ Upstream commit 0113d9c9d1ccc07f5a3710dac4aa24b6d711278c ]
Currently, we assume the skb is associated with a device before calling __ip_options_compile, which is not always the case if it is re-routed by ipvs.
When skb->dev is NULL, dev_net(skb->dev) will become null-dereference. This patch adds a check for the edge case and switch to use the net_device from the rtable when skb->dev is NULL.
--- net/ipv4/route.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
net/ipv4/route.c +3 -1
@@ -1220,6 +1220,7 @@ EXPORT_INDIRECT_CALLABLE(ipv4_dst_check);static void ipv4_send_dest_unreach (struct sk_buff *skb) { +struct net_device *dev;struct ip_options opt;int res;
@@ -1237,7 +1238,8 @@ static void ipv4_send_dest_unreach(struct sk_buff *skb) opt.optlen =ip_hdr (skb)->ihl *4 -sizeof (struct iphdr );rcu_read_lock (); - res =__ip_options_compile (dev_net (skb->dev), &opt, skb,NULL ); + dev = skb->dev ? skb->dev :skb_rtable (skb)->dst.dev; + res =__ip_options_compile (dev_net (dev), &opt, skb,NULL );rcu_read_unlock ();if (res)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 46/183 powerpc/perf/hv-24x7: Update domain value check
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Kajol Jain <[email protected]>
[ Upstream commit 4ff3ba4db5943cac1045e3e4a3c0463ea10f6930 ]
Valid domain value is in range 1 to HV_PERF_DOMAIN_MAX. Current code has check for domain value greater than or equal to HV_PERF_DOMAIN_MAX. But the check for domain value 0 is missing.
Fix this issue by adding check for domain value 0.
Before:
# ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1 Using CPUID 00800200 Control descriptor is not initialized Error: The sys_perf_event_open() syscall returned with 5 (Input/output error) for event (hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/). /bin/dmesg | grep -i perf may provide additional information.
Result from dmesg:
[ 37.819387] hv-24x7: hcall failed: [0 0x60040000 0x100 0] => ret 0xfffffffffffffffc (-4) detail=0x2000000 failing ix=0
After:
# ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1 Using CPUID 00800200 Control descriptor is not initialized Warning: hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ event is not supported by the kernel. failed to read counter hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/
--- arch/powerpc/perf/hv-24x7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/powerpc/perf/hv-24x7.c +1 -1
@@ -1431,7 +1431,7 @@ static int h_24x7_event_init(struct perf_event *event) } domain =event_get_domain (event); -if (domain >=HV_PERF_DOMAIN_MAX ) { +if (domain ==0 || domain >=HV_PERF_DOMAIN_MAX ) {pr_devel ("invalid domain %d\n" , domain);return -EINVAL ; }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 47/183 dccp: fix dccp_v4_err()/dccp_v6_err() again
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Eric Dumazet <[email protected]>
[ Upstream commit 6af289746a636f71f4c0535a9801774118486c7a ]
dh->dccph_x is the 9th byte (offset 8) in "struct dccp_hdr", not in the "byte 7" as Jann claimed.
We need to make sure the ICMP messages are big enough, using more standard ways (no more assumptions).
syzbot reported:
BUG: KMSAN: uninit-value in pskb_may_pull_reason include/linux/skbuff.h:2667 [inline] BUG: KMSAN: uninit-value in pskb_may_pull include/linux/skbuff.h:2681 [inline] BUG: KMSAN: uninit-value in dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94 pskb_may_pull_reason include/linux/skbuff.h:2667 [inline] pskb_may_pull include/linux/skbuff.h:2681 [inline] dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94 icmpv6_notify+0x4c7/0x880 net/ipv6/icmp.c:867 icmpv6_rcv+0x19d5/0x30d0 ip6_protocol_deliver_rcu+0xda6/0x2a60 net/ipv6/ip6_input.c:438 ip6_input_finish net/ipv6/ip6_input.c:483 [inline] NF_HOOK include/linux/netfilter.h:304 [inline] ip6_input+0x15d/0x430 net/ipv6/ip6_input.c:492 ip6_mc_input+0xa7e/0xc80 net/ipv6/ip6_input.c:586 dst_input include/net/dst.h:468 [inline] ip6_rcv_finish+0x5db/0x870 net/ipv6/ip6_input.c:79 NF_HOOK include/linux/netfilter.h:304 [inline] ipv6_rcv+0xda/0x390 net/ipv6/ip6_input.c:310 __netif_receive_skb_one_core net/core/dev.c:5523 [inline] __netif_receive_skb+0x1a6/0x5a0 net/core/dev.c:5637 netif_receive_skb_internal net/core/dev.c:5723 [inline] netif_receive_skb+0x58/0x660 net/core/dev.c:5782 tun_rx_batched+0x83b/0x920 tun_get_user+0x564c/0x6940 drivers/net/tun.c:2002 tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048 call_write_iter include/linux/fs.h:1985 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x8ef/0x15c0 fs/read_write.c:584 ksys_write+0x20f/0x4c0 fs/read_write.c:637 __do_sys_write fs/read_write.c:649 [inline] __se_sys_write fs/read_write.c:646 [inline] __x64_sys_write+0x93/0xd0 fs/read_write.c:646 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd
Uninit was created at:
slab_post_alloc_hook+0x12f/0xb70 mm/slab.h:767 slab_alloc_node mm/slub.c:3478 [inline] kmem_cache_alloc_node+0x577/0xa80 mm/slub.c:3523 kmalloc_reserve+0x13d/0x4a0 net/core/skbuff.c:559 __alloc_skb+0x318/0x740 net/core/skbuff.c:650 alloc_skb include/linux/skbuff.h:1286 [inline] alloc_skb_with_frags+0xc8/0xbd0 net/core/skbuff.c:6313 sock_alloc_send_pskb+0xa80/0xbf0 net/core/sock.c:2795 tun_alloc_skb drivers/net/tun.c:1531 [inline] tun_get_user+0x23cf/0x6940 drivers/net/tun.c:1846 tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048 call_write_iter include/linux/fs.h:1985 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x8ef/0x15c0 fs/read_write.c:584 ksys_write+0x20f/0x4c0 fs/read_write.c:637 __do_sys_write fs/read_write.c:649 [inline] __se_sys_write fs/read_write.c:646 [inline] __x64_sys_write+0x93/0xd0 fs/read_write.c:646 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd CPU: 0 PID: 4995 Comm: syz-executor153 Not tainted 6.6.0-rc1-syzkaller-00014-ga747acc0b752 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 08/04/2023
--- net/dccp/ipv4.c | 9 ++------- net/dccp/ipv6.c | 9 ++------- 2 files changed, 4 insertions(+), 14 deletions(-)
net/dccp/ipv4.c +2 -7
@@ -250,13 +250,8 @@ static int dccp_v4_err(struct sk_buff *skb, u32 info)int err;struct net *net =dev_net (skb->dev); -/* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, -* which is in byte 7 of the dccp header. -* Our caller (icmp_socket_deliver()) already pulled 8 bytes for us. -* -* Later on, we want to access the sequence number fields, which are -* beyond 8 bytes, so we have to pskb_may_pull() ourselves. -*/ +if (!pskb_may_pull (skb, offset +sizeof (*dh))) +return -EINVAL ; dh = (struct dccp_hdr *)(skb->data + offset);if (!pskb_may_pull (skb, offset +__dccp_basic_hdr_len (dh)))return -EINVAL ;
net/dccp/ipv6.c +2 -7
@@ -83,13 +83,8 @@ static int dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,__u64 seq;struct net *net =dev_net (skb->dev); -/* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, -* which is in byte 7 of the dccp header. -* Our caller (icmpv6_notify()) already pulled 8 bytes for us. -* -* Later on, we want to access the sequence number fields, which are -* beyond 8 bytes, so we have to pskb_may_pull() ourselves. -*/ +if (!pskb_may_pull (skb, offset +sizeof (*dh))) +return -EINVAL ; dh = (struct dccp_hdr *)(skb->data + offset);if (!pskb_may_pull (skb, offset +__dccp_basic_hdr_len (dh)))return -EINVAL ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 48/183 platform/x86: intel_scu_ipc: Check status after timeout in busy_loop()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Stephen Boyd <[email protected]>
[ Upstream commit e0b4ab3bb92bda8d12f55842614362989d5b2cb3 ]
It's possible for the polling loop in busy_loop() to get scheduled away for a long time.
status = ipc_read_status(scu); // status = IPC_STATUS_BUSY <long time scheduled away>
if (!(status & IPC_STATUS_BUSY))
If this happens, then the status bit could change while the task is scheduled away and this function would never read the status again after timing out. Instead, the function will return -ETIMEDOUT when it's possible that scheduling didn't work out and the status bit was cleared. Bit polling code should always check the bit being polled one more time after the timeout in case this happens.
Fix this by reading the status once more after the while loop breaks. The readl_poll_timeout() macro implements all of this, and it is shorter, so use that macro here to consolidate code and fix this.
There were some concerns with using readl_poll_timeout() because it uses timekeeping, and timekeeping isn't running early on or during the late stages of system suspend or early stages of system resume, but an audit of the code concluded that this code isn't called during those times so it is safe to use the macro.
--- drivers/platform/x86/intel_scu_ipc.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-)
drivers/platform/x86/intel_scu_ipc.c +8 -11
@@ -19,6 +19,7 @@#include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/slab.h>
@@ -232,19 +233,15 @@ static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)/* Wait till scu status is busy */ static inline int busy_loop (struct intel_scu_ipc_dev *scu) { -unsigned long end = jiffies +IPC_TIMEOUT ; - -do { -u32 status; - - status =ipc_read_status (scu); -if (!(status &IPC_STATUS_BUSY )) -return (status &IPC_STATUS_ERR ) ? -EIO :0 ; +u8 status; +int err; -usleep_range (50 ,100 ); - }while (time_before (jiffies, end)); + err =readx_poll_timeout (ipc_read_status, scu, status, !(status &IPC_STATUS_BUSY ), +100 ,jiffies_to_usecs (IPC_TIMEOUT )); +if (err) +return err; -return -ETIMEDOUT ; +return (status &IPC_STATUS_ERR ) ? -EIO :0 ; }/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 49/183 platform/x86: intel_scu_ipc: Check status upon timeout in ipc_wait_for_interrupt()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Stephen Boyd <[email protected]>
[ Upstream commit 427fada620733e6474d783ae6037a66eae42bf8c ]
It's possible for the completion in ipc_wait_for_interrupt() to timeout, simply because the interrupt was delayed in being processed. A timeout in itself is not an error. This driver should check the status register upon a timeout to ensure that scheduling or interrupt processing delays don't affect the outcome of the IPC return value.
CPU0 SCU
---- ---
ipc_wait_for_interrupt()
wait_for_completion_timeout(&scu->cmd_complete)
[TIMEOUT] status[IPC_STATUS_BUSY]=0
Fix this problem by reading the status bit in all cases, regardless of the timeout. If the completion times out, we'll assume the problem was that the IPC_STATUS_BUSY bit was still set, but if the status bit is cleared in the meantime we know that we hit some scheduling delay and we should just check the error bit.
--- drivers/platform/x86/intel_scu_ipc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/platform/x86/intel_scu_ipc.c +4 -2
@@ -249,10 +249,12 @@ static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu) {int status; -if (!wait_for_completion_timeout (&scu->cmd_complete,IPC_TIMEOUT )) -return -ETIMEDOUT ; +wait_for_completion_timeout (&scu->cmd_complete,IPC_TIMEOUT ); status =ipc_read_status (scu); +if (status &IPC_STATUS_BUSY ) +return -ETIMEDOUT ; +if (status &IPC_STATUS_ERR )return -EIO ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 50/183 platform/x86: intel_scu_ipc: Dont override scu in intel_scu_ipc_dev_simple_command()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Stephen Boyd <[email protected]>
[ Upstream commit efce78584e583226e9a1f6cb2fb555d6ff47c3e7 ]
Andy discovered this bug during patch review. The 'scu' argument to this function shouldn't be overridden by the function itself. It doesn't make any sense. Looking at the commit history, we see that commit f57fa18583f5 ("platform/x86: intel_scu_ipc: Introduce new SCU IPC API") removed the setting of the scu to ipcdev in other functions, but not this one. That was an oversight. Remove this line so that we stop overriding the scu instance that is used by this function.
--- drivers/platform/x86/intel_scu_ipc.c | 1 - 1 file changed, 1 deletion(-)
drivers/platform/x86/intel_scu_ipc.c +0 -1
@@ -444,7 +444,6 @@ int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,mutex_unlock (&ipclock);return -ENODEV ; } - scu = ipcdev; cmdval = sub <<12 | cmd;ipc_command (scu, cmdval); err =intel_scu_ipc_check_status (scu);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 51/183 platform/x86: intel_scu_ipc: Fail IPC send if still busy
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Stephen Boyd <[email protected]>
[ Upstream commit 85e654c9f722853a595fa941dca60c157b707b86 ]
It's possible for interrupts to get significantly delayed to the point that callers of intel_scu_ipc_dev_command() and friends can call the function once, hit a timeout, and call it again while the interrupt still hasn't been processed. This driver will get seriously confused if the interrupt is finally processed after the second IPC has been sent with ipc_command(). It won't know which IPC has been completed. This could be quite disastrous if calling code assumes something has happened upon return from intel_scu_ipc_dev_simple_command() when it actually hasn't.
Let's avoid this scenario by simply returning -EBUSY in this case. Hopefully higher layers will know to back off or fail gracefully when this happens. It's all highly unlikely anyway, but it's better to be correct here as we have no way to know which IPC the status register is telling us about if we send a second IPC while the previous IPC is still processing.
--- drivers/platform/x86/intel_scu_ipc.c | 40 +++++++++++++++++++--------- 1 file changed, 28 insertions(+), 12 deletions(-)
drivers/platform/x86/intel_scu_ipc.c +28 -12
@@ -266,6 +266,24 @@ static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)return scu->irq >0 ?ipc_wait_for_interrupt (scu) :busy_loop (scu); } +static struct intel_scu_ipc_dev *intel_scu_ipc_get (struct intel_scu_ipc_dev *scu) +{ +u8 status; + +if (!scu) + scu = ipcdev; +if (!scu) +return ERR_PTR (-ENODEV ); + + status =ipc_read_status (scu); +if (status &IPC_STATUS_BUSY ) { +dev_dbg (&scu->dev,"device is busy\n" ); +return ERR_PTR (-EBUSY ); + } + +return scu; +} +/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ static int pwr_reg_rdwr (struct intel_scu_ipc_dev *scu,u16 *addr,u8 *data,u32 count,u32 op,u32 id)
@@ -279,11 +297,10 @@ static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,memset (cbuf,0 ,sizeof (cbuf));mutex_lock (&ipclock); -if (!scu) - scu = ipcdev; -if (!scu) { + scu =intel_scu_ipc_get (scu); +if (IS_ERR (scu)) {mutex_unlock (&ipclock); -return -ENODEV ; +return PTR_ERR (scu); }for (nc =0 ; nc < count; nc++, offset +=2 ) {
@@ -438,12 +455,12 @@ int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,int err;mutex_lock (&ipclock); -if (!scu) - scu = ipcdev; -if (!scu) { + scu =intel_scu_ipc_get (scu); +if (IS_ERR (scu)) {mutex_unlock (&ipclock); -return -ENODEV ; +return PTR_ERR (scu); } + cmdval = sub <<12 | cmd;ipc_command (scu, cmdval); err =intel_scu_ipc_check_status (scu);
@@ -483,11 +500,10 @@ int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,return -EINVAL ;mutex_lock (&ipclock); -if (!scu) - scu = ipcdev; -if (!scu) { + scu =intel_scu_ipc_get (scu); +if (IS_ERR (scu)) {mutex_unlock (&ipclock); -return -ENODEV ; +return PTR_ERR (scu); }memcpy (inbuf, in, inlen);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 52/183 x86/srso: Fix srso_show_state() side effect
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Josh Poimboeuf <[email protected]>
[ Upstream commit a8cf700c17d9ca6cb8ee7dc5c9330dbac3948237 ]
Reading the 'spec_rstack_overflow' sysfs file can trigger an unnecessary MSR write, and possibly even a (handled) exception if the microcode hasn't been updated.
Avoid all that by just checking X86_FEATURE_IBPB_BRTYPE instead, which gets set by srso_select_mitigation() if the updated microcode exists.
--- arch/x86/kernel/cpu/bugs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/x86/kernel/cpu/bugs.c +1 -1
@@ -2692,7 +2692,7 @@ static ssize_t srso_show_state(char *buf)return sysfs_emit (buf,"%s%s\n" , srso_strings[srso_mitigation], - (cpu_has_ibpb_brtype_microcode () ?"" :", no microcode" )); +boot_cpu_has (X86_FEATURE_IBPB_BRTYPE ) ?"" :", no microcode" ); } static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 53/183 x86/srso: Fix SBPB enablement for spec_rstack_overflow=off
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Josh Poimboeuf <[email protected]>
[ Upstream commit 01b057b2f4cc2d905a0bd92195657dbd9a7005ab ]
If the user has requested no SRSO mitigation, other mitigations can use the lighter-weight SBPB instead of IBPB.
--- arch/x86/kernel/cpu/bugs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/x86/kernel/cpu/bugs.c +1 -1
@@ -2414,7 +2414,7 @@ static void __init srso_select_mitigation(void)switch (srso_cmd) {case SRSO_CMD_OFF : -return ; + goto pred_cmd;case SRSO_CMD_MICROCODE :if (has_microcode) {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 54/183 net: hns3: fix GRE checksum offload issue
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jie Wang <[email protected]>
[ Upstream commit f9f651261130cdcb7adc9a3e365b356bc2749ab3 ]
The device_version V3 hardware can't offload the checksum for IP in GRE packets, but can do it for NvGRE. So default to disable the checksum and GSO offload for GRE, but keep the ability to enable it when only using NvGRE.
--- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +9 -0
@@ -3156,6 +3156,15 @@ static void hns3_set_default_feature(struct net_device *netdev) NETIF_F_HW_TC); netdev->hw_enc_features |= netdev->vlan_features |NETIF_F_TSO_MANGLEID ; + +/* The device_version V3 hardware can't offload the checksum for IP in +* GRE packets, but can do it for NvGRE. So default to disable the +* checksum and GSO offload for GRE. +*/ +if (ae_dev->dev_version >HNAE3_DEVICE_VERSION_V2 ) { + netdev->features &= ~NETIF_F_GSO_GRE ; + netdev->features &= ~NETIF_F_GSO_GRE_CSUM ; + } } static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 55/183 net: hns3: only enable unicast promisc when mac table full
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jian Shen <[email protected]>
[ Upstream commit f2ed304922a55690529bcca59678dd92d7466ce8 ]
Currently, the driver will enable unicast promisc for the function once configure mac address fail. It's unreasonable when the failure is caused by using same mac address with other functions. So only enable unicast promisc when mac table full.
--- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +1 -1
@@ -8967,7 +8967,7 @@ static void hclge_update_overflow_flags(struct hclge_vport *vport,if (mac_type ==HCLGE_MAC_ADDR_UC ) {if (is_all_added) vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE ; -else +else if (hclge_is_umv_space_full (vport, true)) vport->overflow_promisc_flags |=HNAE3_OVERFLOW_UPE ; }else {if (is_all_added)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 56/183 net: hns3: fix fail to delete tc flower rules during reset issue
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jijie Shao <[email protected]>
[ Upstream commit 1a7be66e4685b8541546222c305cce9710718a88 ]
Firmware does not respond driver commands during reset Therefore, rule will fail to delete while the firmware is resetting
So, if failed to delete rule, set rule state to TO_DEL, and the rule will be deleted when periodic task being scheduled.
--- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +6 -0
@@ -7546,6 +7546,12 @@ static int hclge_del_cls_flower(struct hnae3_handle *handle, ret =hclge_fd_tcam_config (hdev,HCLGE_FD_STAGE_1 , true, rule->location,NULL , false);if (ret) { +/* if tcam config fail, set rule state to TO_DEL, +* so the rule will be deleted when periodic +* task being scheduled. +*/ +hclge_update_fd_list (hdev,HCLGE_FD_TO_DEL , rule->location,NULL ); +set_bit (HCLGE_STATE_FD_TBL_CHANGED , &hdev->state);spin_unlock_bh (&hdev->fd_rule_lock);return ret; }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 57/183 net: hns3: add 5ms delay before clear firmware reset irq source
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jie Wang <[email protected]>
[ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ]
Currently the reset process in hns3 and firmware watchdog init process is asynchronous. we think firmware watchdog initialization is completed before hns3 clear the firmware interrupt source. However, firmware initialization may not complete early.
so we add delay before hns3 clear firmware interrupt source and 5 ms delay is enough to avoid second firmware reset interrupt.
--- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +5 -0
@@ -3391,9 +3391,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)static void hclge_clear_event_cause (struct hclge_dev *hdev,u32 event_type,u32 regclr) { +#define HCLGE_IMP_RESET_DELAY 5 +switch (event_type) {case HCLGE_VECTOR0_EVENT_PTP :case HCLGE_VECTOR0_EVENT_RST : +if (regclr ==BIT (HCLGE_VECTOR0_IMPRESET_INT_B )) +mdelay (HCLGE_IMP_RESET_DELAY ); +hclge_write_dev (&hdev->hw,HCLGE_MISC_RESET_STS_REG , regclr);break ;case HCLGE_VECTOR0_EVENT_MBX :
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 58/183 net: bridge: use DEV_STATS_INC()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Eric Dumazet <[email protected]>
[ Upstream commit 44bdb313da57322c9b3c108eb66981c6ec6509f4 ]
syzbot/KCSAN reported data-races in br_handle_frame_finish() [1] This function can run from multiple cpus without mutual exclusion.
Adopt SMP safe DEV_STATS_INC() to update dev->stats fields.
Handles updates to dev->stats.tx_dropped while we are at it.
[1]
BUG: KCSAN: data-race in br_handle_frame_finish / br_handle_frame_finish
read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 1:
br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189 br_nf_hook_thresh+0x1ed/0x220 br_nf_pre_routing_finish_ipv6+0x50f/0x540 NF_HOOK include/linux/netfilter.h:304 [inline] br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178 br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508 nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline] nf_hook_bridge_pre net/bridge/br_input.c:272 [inline] br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417 __netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417 __netif_receive_skb_one_core net/core/dev.c:5521 [inline] __netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637 process_backlog+0x21f/0x380 net/core/dev.c:5965 __napi_poll+0x60/0x3b0 net/core/dev.c:6527 napi_poll net/core/dev.c:6594 [inline] net_rx_action+0x32b/0x750 net/core/dev.c:6727 __do_softirq+0xc1/0x265 kernel/softirq.c:553 run_ksoftirqd+0x17/0x20 kernel/softirq.c:921 smpboot_thread_fn+0x30a/0x4a0 kernel/smpboot.c:164 kthread+0x1d7/0x210 kernel/kthread.c:388 ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304
read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 0:
br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189 br_nf_hook_thresh+0x1ed/0x220 br_nf_pre_routing_finish_ipv6+0x50f/0x540 NF_HOOK include/linux/netfilter.h:304 [inline] br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178 br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508 nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline] nf_hook_bridge_pre net/bridge/br_input.c:272 [inline] br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417 __netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417 __netif_receive_skb_one_core net/core/dev.c:5521 [inline] __netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637 process_backlog+0x21f/0x380 net/core/dev.c:5965 __napi_poll+0x60/0x3b0 net/core/dev.c:6527 napi_poll net/core/dev.c:6594 [inline] net_rx_action+0x32b/0x750 net/core/dev.c:6727 __do_softirq+0xc1/0x265 kernel/softirq.c:553 do_softirq+0x5e/0x90 kernel/softirq.c:454 __local_bh_enable_ip+0x64/0x70 kernel/softirq.c:381 __raw_spin_unlock_bh include/linux/spinlock_api_smp.h:167 [inline] _raw_spin_unlock_bh+0x36/0x40 kernel/locking/spinlock.c:210 spin_unlock_bh include/linux/spinlock.h:396 [inline] batadv_tt_local_purge+0x1a8/0x1f0 net/batman-adv/translation-table.c:1356 batadv_tt_purge+0x2b/0x630 net/batman-adv/translation-table.c:3560 process_one_work kernel/workqueue.c:2630 [inline] process_scheduled_works+0x5b8/0xa30 kernel/workqueue.c:2703 worker_thread+0x525/0x730 kernel/workqueue.c:2784 kthread+0x1d7/0x210 kernel/kthread.c:388 ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304
value changed: 0x00000000000d7190 -> 0x00000000000d7191
Reported by Kernel Concurrency Sanitizer on:
CPU: 0 PID: 14848 Comm: kworker/u4:11 Not tainted 6.6.0-rc1-syzkaller-00236-gad8a69f361b9 #0
--- net/bridge/br_forward.c | 4 ++-- net/bridge/br_input.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)
net/bridge/br_forward.c +2 -2
@@ -124,7 +124,7 @@ static int deliver_clone(const struct net_bridge_port *prev, skb =skb_clone (skb,GFP_ATOMIC );if (!skb) { - dev->stats.tx_dropped++; +DEV_STATS_INC (dev, tx_dropped);return -ENOMEM ; }
@@ -263,7 +263,7 @@ static void maybe_deliver_addr(struct net_bridge_port *p, struct sk_buff *skb, skb =skb_copy (skb,GFP_ATOMIC );if (!skb) { - dev->stats.tx_dropped++; +DEV_STATS_INC (dev, tx_dropped);return ; }
net/bridge/br_input.c +2 -2
@@ -146,12 +146,12 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skbif ((mdst && mdst->host_joined) ||br_multicast_is_router (brmctx, skb)) { local_rcv = true; - br->dev->stats.multicast++; +DEV_STATS_INC (br->dev, multicast); } mcast_hit = true; }else { local_rcv = true; - br->dev->stats.multicast++; +DEV_STATS_INC (br->dev, multicast); }break ;case BR_PKT_UNICAST :
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 59/183 team: fix null-ptr-deref when team device type is changed
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ziyang Xuan <[email protected]>
[ Upstream commit 492032760127251e5540a5716a70996bacf2a3fd ]
Get a null-ptr-deref bug as follows with reproducer [1].
BUG: kernel NULL pointer dereference, address: 0000000000000228 ... RIP: 0010:vlan_dev_hard_header+0x35/0x140 [8021q] ... Call Trace: <TASK> ? __die+0x24/0x70 ? page_fault_oops+0x82/0x150 ? exc_page_fault+0x69/0x150 ? asm_exc_page_fault+0x26/0x30 ? vlan_dev_hard_header+0x35/0x140 [8021q] ? vlan_dev_hard_header+0x8e/0x140 [8021q] neigh_connected_output+0xb2/0x100 ip6_finish_output2+0x1cb/0x520 ? nf_hook_slow+0x43/0xc0 ? ip6_mtu+0x46/0x80 ip6_finish_output+0x2a/0xb0 mld_sendpack+0x18f/0x250 mld_ifc_work+0x39/0x160 process_one_work+0x1e6/0x3f0 worker_thread+0x4d/0x2f0 ? __pfx_worker_thread+0x10/0x10 kthread+0xe5/0x120 ? __pfx_kthread+0x10/0x10 ret_from_fork+0x34/0x50 ? __pfx_kthread+0x10/0x10 ret_from_fork_asm+0x1b/0x30
[1]
$ teamd -t team0 -d -c '{"runner": {"name": "loadbalance"}}'
$ ip link add name t-dummy type dummy
$ ip link add link t-dummy name t-dummy.100 type vlan id 100
$ ip link add name t-nlmon type nlmon
$ ip link set t-nlmon master team0
$ ip link set t-nlmon nomaster
$ ip link set t-dummy up
$ ip link set team0 up
$ ip link set t-dummy.100 down
$ ip link set t-dummy.100 master team0When enslave a vlan device to team device and team device type is changed from non-ether to ether, header_ops of team device is changed to vlan_header_ops. That is incorrect and will trigger null-ptr-deref for vlan->real_dev in vlan_dev_hard_header() because team device is not a vlan device.
Cache eth_header_ops in team_setup(), then assign cached header_ops to header_ops of team net device when its type is changed from non-ether to ether to fix the bug.
--- drivers/net/team/team.c | 10 +++++++++- include/linux/if_team.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)
drivers/net/team/team.c +9 -1
@@ -2122,7 +2122,12 @@ static const struct ethtool_ops team_ethtool_ops = {static void team_setup_by_port (struct net_device *dev,struct net_device *port_dev) { - dev->header_ops = port_dev->header_ops; +struct team *team =netdev_priv (dev); + +if (port_dev->type ==ARPHRD_ETHER ) + dev->header_ops = team->header_ops_cache; +else + dev->header_ops = port_dev->header_ops; dev->type = port_dev->type; dev->hard_header_len = port_dev->hard_header_len; dev->needed_headroom = port_dev->needed_headroom;
@@ -2169,8 +2174,11 @@ static int team_dev_type_check_change(struct net_device *dev,static void team_setup (struct net_device *dev) { +struct team *team =netdev_priv (dev); +ether_setup (dev); dev->max_mtu =ETH_MAX_MTU ; + team->header_ops_cache = dev->header_ops; dev->netdev_ops = &team_netdev_ops; dev->ethtool_ops = &team_ethtool_ops;
include/linux/if_team.h +2 -0
@@ -189,6 +189,8 @@ struct team {struct net_device *dev;/* associated netdevice */ struct team_pcpu_stats __percpu *pcpu_stats; +const struct header_ops *header_ops_cache; +struct mutex lock;/* used for overall locking, e.g. port lists write */ /*
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 60/183 net: rds: Fix possible NULL-pointer dereference
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Artem Chernyshev <[email protected]>
[ Upstream commit f1d95df0f31048f1c59092648997686e3f7d9478 ]
In rds_rdma_cm_event_handler_cmn() check, if conn pointer exists before dereferencing it as rdma_set_service_type() argument
Found by Linux Verification Center (linuxtesting.org) with SVACE.
--- net/rds/rdma_transport.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
net/rds/rdma_transport.c +7 -5
@@ -86,11 +86,13 @@ static int rds_rdma_cm_event_handler_cmn(struct rdma_cm_id *cm_id,break ;case RDMA_CM_EVENT_ADDR_RESOLVED : -rdma_set_service_type (cm_id, conn->c_tos); -rdma_set_min_rnr_timer (cm_id,IB_RNR_TIMER_000_32 ); -/* XXX do we need to clean up if this fails? */ - ret =rdma_resolve_route (cm_id, -RDS_RDMA_RESOLVE_TIMEOUT_MS ); +if (conn) { +rdma_set_service_type (cm_id, conn->c_tos); +rdma_set_min_rnr_timer (cm_id,IB_RNR_TIMER_000_32 ); +/* XXX do we need to clean up if this fails? */ + ret =rdma_resolve_route (cm_id, +RDS_RDMA_RESOLVE_TIMEOUT_MS ); + }break ;case RDMA_CM_EVENT_ROUTE_RESOLVED :
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 61/183 netfilter: nf_tables: disable toggling dormant table state more than once
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
[ Upstream commit c9bd26513b3a11b3adb3c2ed8a31a01a87173ff1 ]
nft -f -<<EOF
add table ip t
add table ip t { flags dormant; }
add chain ip t c { type filter hook input priority 0; } add table ip t
EOF
Triggers a splat from nf core on next table delete because we lose track of right hook register state:
WARNING: CPU: 2 PID: 1597 at net/netfilter/core.c:501 __nf_unregister_net_hook RIP: 0010:__nf_unregister_net_hook+0x41b/0x570 nf_unregister_net_hook+0xb4/0xf0 __nf_tables_unregister_hook+0x160/0x1d0
[..]
The above should have table in *active* state, but in fact no hooks were registered.
Reject on/off/on games rather than attempting to fix this.
--- net/netfilter/nf_tables_api.c | 4 ++++ 1 file changed, 4 insertions(+)
net/netfilter/nf_tables_api.c +4 -0
@@ -1159,6 +1159,10 @@ static int nf_tables_updtable(struct nft_ctx *ctx) flags & NFT_TABLE_F_OWNER))return -EOPNOTSUPP ; +/* No dormant off/on/off/on games in single transaction */ +if (ctx->table->flags & __NFT_TABLE_F_UPDATE) +return -EINVAL ; + trans =nft_trans_alloc (ctx,NFT_MSG_NEWTABLE ,sizeof (struct nft_trans_table ));if (trans ==NULL )
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 62/183 netfilter: ipset: Fix race between IPSET_CMD_CREATE and IPSET_CMD_SWAP
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jozsef Kadlecsik <[email protected]>
[ Upstream commit 7433b6d2afd512d04398c73aa984d1e285be125b ]
Kyle Zeng reported that there is a race between IPSET_CMD_ADD and IPSET_CMD_SWAP in netfilter/ip_set, which can lead to the invocation of __ip_set_put on a wrong set, triggering the BUG_ON(set->ref == 0); check in it.
The race is caused by using the wrong reference counter, i.e. the ref counter instead of ref_netlink.
--- net/netfilter/ipset/ip_set_core.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
net/netfilter/ipset/ip_set_core.c +10 -2
@@ -682,6 +682,14 @@ __ip_set_put(struct ip_set *set)/* set->ref can be swapped out by ip_set_swap, netlink events (like dump) need * a separate reference counter */ +static void +__ip_set_get_netlink (struct ip_set *set) +{ +write_lock_bh (&ip_set_ref_lock); + set->ref_netlink++; +write_unlock_bh (&ip_set_ref_lock); +} +static void __ip_set_put_netlink (struct ip_set *set) {
@@ -1695,11 +1703,11 @@ call_ad(struct net *net, struct sock *ctnl, struct sk_buff *skb, do { if (retried) { - __ip_set_get(set); + __ip_set_get_netlink(set); nfnl_unlock(NFNL_SUBSYS_IPSET); cond_resched(); nfnl_lock(NFNL_SUBSYS_IPSET); - __ip_set_put(set); + __ip_set_put_netlink(set); } ip_set_lock(set);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 63/183 locking/seqlock: Do the lockdep annotation before locking in do_write_seqcount_begin_nested()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sebastian Andrzej Siewior <[email protected]>
[ Upstream commit 41b43b6c6e30a832c790b010a06772e793bca193 ]
It was brought up by Tetsuo that the following sequence:
write_seqlock_irqsave()
printk_deferred_enter()
could lead to a deadlock if the lockdep annotation within write_seqlock_irqsave() triggers.
The problem is that the sequence counter is incremented before the lockdep annotation is performed. The lockdep splat would then attempt to invoke printk() but the reader side, of the same seqcount, could have a tty_port::lock acquired waiting for the sequence number to become even again.
The other lockdep annotations come before the actual locking because "we want to see the locking error before it happens". There is no reason why seqcount should be different here.
Do the lockdep annotation first then perform the locking operation (the sequence increment).
--- include/linux/seqlock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
include/linux/seqlock.h +1 -1
@@ -516,8 +516,8 @@ do { \static inline void do_write_seqcount_begin_nested (seqcount_t *s,int subclass) { -do_raw_write_seqcount_begin (s);seqcount_acquire (&s->dep_map, subclass,0 , _RET_IP_); +do_raw_write_seqcount_begin (s); }/**
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 64/183 net: ena: Flush XDP packets on error.
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sebastian Andrzej Siewior <[email protected]>
[ Upstream commit 6f411fb5ca9419090bee6a0a46425e0a5060b734 ]
xdp_do_flush() should be invoked before leaving the NAPI poll function after a XDP-redirect. This is not the case if the driver leaves via the error path (after having a redirect in one of its previous iterations).
Invoke xdp_do_flush() also in the error path.
--- drivers/net/ethernet/amazon/ena/ena_netdev.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/net/ethernet/amazon/ena/ena_netdev.c +3 -0
@@ -1788,6 +1788,9 @@ static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,return work_done; error: +if (xdp_flags &ENA_XDP_REDIRECT ) +xdp_do_flush (); + adapter =netdev_priv (rx_ring->netdev);if (rc == -ENOSPC ) {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 65/183 bnxt_en: Flush XDP for bnxt_poll_nitroa0()s NAPI
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Sebastian Andrzej Siewior <[email protected]>
[ Upstream commit edc0140cc3b7b91874ebe70eb7d2a851e8817ccc ]
bnxt_poll_nitroa0() invokes bnxt_rx_pkt() which can run a XDP program which in turn can return XDP_REDIRECT. bnxt_rx_pkt() is also used by __bnxt_poll_work() which flushes (xdp_do_flush()) the packets after each round. bnxt_poll_nitroa0() lacks this feature. xdp_do_flush() should be invoked before leaving the NAPI callback.
Invoke xdp_do_flush() after a redirect in bnxt_poll_nitroa0() NAPI.
--- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/net/ethernet/broadcom/bnxt/bnxt.c +5 -0
@@ -2520,6 +2520,7 @@ static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)struct rx_cmp_ext *rxcmp1;u32 cp_cons, tmp_raw_cons;u32 raw_cons = cpr->cp_raw_cons; +bool flush_xdp = false;u32 rx_pkts =0 ;u8 event =0 ;
@@ -2554,6 +2555,8 @@ static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget) rx_pkts++; else if (rc == -EBUSY) /* partial completion */ break; +if (event &BNXT_REDIRECT_EVENT ) + flush_xdp = true; }else if (unlikely (TX_CMP_TYPE (txcmp) ==CMPL_BASE_TYPE_HWRM_DONE )) {bnxt_hwrm_handler (bp, txcmp);
@@ -2573,6 +2576,8 @@ static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)if (event &BNXT_AGG_EVENT )bnxt_db_write (bp, &rxr->rx_agg_db, rxr->rx_agg_prod); +if (flush_xdp) +xdp_do_flush ();if (!bnxt_has_work (bp, cpr) && rx_pkts < budget) {napi_complete_done (napi, rx_pkts);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 66/183 igc: Expose tx-usecs coalesce setting to user
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Muhammad Husaini Zulkifli <[email protected]>
[ Upstream commit 1703b2e0de653b459ca6230be32ce7f2ea0ae7ee ]
When users attempt to obtain the coalesce setting using the ethtool command, current code always returns 0 for tx-usecs. This is because I225/6 always uses a queue pair setting, hence tx_coalesce_usecs does not return a value during the igc_ethtool_get_coalesce() callback process. The pair queue condition checking in igc_ethtool_get_coalesce() is removed by this patch so that the user gets information of the value of tx-usecs.
Even if i225/6 is using queue pair setting, there is no harm in notifying the user of the tx-usecs. The implementation of the current code may have previously been a copy of the legacy code i210. Since I225 has the queue pair setting enabled, tx-usecs will always adhere to the user-set rx-usecs value. An error message will appear when the user attempts to set the tx-usecs value for the input parameters because, by default, they should only set the rx-usecs value.
This patch also adds the helper function to get the previous rx coalesce value similar to tx coalesce.
How to test:
User can get the coalesce value using ethtool command.
Example command:
Get: ethtool -c <interface>
Previous output:
rx-usecs: 3
rx-frames: n/a
rx-usecs-irq: n/a
rx-frames-irq: n/a
tx-usecs: 0
tx-frames: n/a
tx-usecs-irq: n/a
tx-frames-irq: n/a
New output:
rx-usecs: 3
rx-frames: n/a
rx-usecs-irq: n/a
rx-frames-irq: n/a
tx-usecs: 3
tx-frames: n/a
tx-usecs-irq: n/a
tx-frames-irq: n/a
--- drivers/net/ethernet/intel/igc/igc_ethtool.c | 31 ++++++++++++-------- 1 file changed, 19 insertions(+), 12 deletions(-)
drivers/net/ethernet/intel/igc/igc_ethtool.c +19 -12
@@ -861,6 +861,18 @@ static void igc_ethtool_get_stats(struct net_device *netdev,spin_unlock (&adapter->stats64_lock); } +static int igc_ethtool_get_previous_rx_coalesce (struct igc_adapter *adapter) +{ +return (adapter->rx_itr_setting <=3 ) ? + adapter->rx_itr_setting : adapter->rx_itr_setting >>2 ; +} + +static int igc_ethtool_get_previous_tx_coalesce (struct igc_adapter *adapter) +{ +return (adapter->tx_itr_setting <=3 ) ? + adapter->tx_itr_setting : adapter->tx_itr_setting >>2 ; +} + static int igc_ethtool_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ec, struct kernel_ethtool_coalesce *kernel_coal,
@@ -868,17 +880,8 @@ static int igc_ethtool_get_coalesce(struct net_device *netdev, {struct igc_adapter *adapter =netdev_priv (netdev); -if (adapter->rx_itr_setting <=3 ) - ec->rx_coalesce_usecs = adapter->rx_itr_setting; -else - ec->rx_coalesce_usecs = adapter->rx_itr_setting >>2 ; - -if (!(adapter->flags &IGC_FLAG_QUEUE_PAIRS )) { -if (adapter->tx_itr_setting <=3 ) - ec->tx_coalesce_usecs = adapter->tx_itr_setting; -else - ec->tx_coalesce_usecs = adapter->tx_itr_setting >>2 ; - } + ec->rx_coalesce_usecs =igc_ethtool_get_previous_rx_coalesce (adapter); + ec->tx_coalesce_usecs =igc_ethtool_get_previous_tx_coalesce (adapter);return 0 ; }
@@ -903,8 +906,12 @@ static int igc_ethtool_set_coalesce(struct net_device *netdev, ec->tx_coalesce_usecs == 2)return -EINVAL ; -if ((adapter->flags &IGC_FLAG_QUEUE_PAIRS ) && ec->tx_coalesce_usecs) +if ((adapter->flags &IGC_FLAG_QUEUE_PAIRS ) && + ec->tx_coalesce_usecs !=igc_ethtool_get_previous_tx_coalesce (adapter)) { +NL_SET_ERR_MSG_MOD (extack, +"Queue Pair mode enabled, both Rx and Tx coalescing controlled by rx-usecs" );return -EINVAL ; + }/* If ITR is disabled, disable DMAC */ if (ec->rx_coalesce_usecs ==0 ) {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 67/183 Fix up backport of 136191703038 ("interconnect: Teach lockdep about icc_bw_lock order")
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
Add a missing include to fix the following build error:
drivers/interconnect/core.c: In function 'icc_init':drivers/interconnect/core.c:1148:9: error: implicit declaration of function 'fs_reclaim_acquire' [-Werror=implicit-function-declaration]
1148 | fs_reclaim_acquire(GFP_KERNEL);
| ^~~~~~~~~~~~~~~~~~
drivers/interconnect/core.c:1150:9: error: implicit declaration of function 'fs_reclaim_release' [-Werror=implicit-function-declaration]
1150 | fs_reclaim_release(GFP_KERNEL);
| ^~~~~~~~~~~~~~~~~~--- drivers/interconnect/core.c | 1 + 1 file changed, 1 insertion(+)
drivers/interconnect/core.c +1 -0
@@ -13,6 +13,7 @@#include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/list.h> +#include <linux/sched/mm.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/slab.h>
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 68/183 gpio: tb10x: Fix an error handling path in tb10x_gpio_probe()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christophe JAILLET <[email protected]>
[ Upstream commit b547b5e52a0587e6b25ea520bf2f9e03d00cbcb6 ]
If an error occurs after a successful irq_domain_add_linear() call, it should be undone by a corresponding irq_domain_remove(), as already done in the remove function.
--- drivers/gpio/gpio-tb10x.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
drivers/gpio/gpio-tb10x.c +5 -1
@@ -195,7 +195,7 @@ static int tb10x_gpio_probe(struct platform_device *pdev) handle_edge_irq,IRQ_NOREQUEST ,IRQ_NOPROBE , IRQ_GC_INIT_MASK_CACHE);if (ret) -return ret; + goto err_remove_domain; gc = tb10x_gpio->domain->gc->gc[0 ]; gc->reg_base = tb10x_gpio->base;
@@ -209,6 +209,10 @@ static int tb10x_gpio_probe(struct platform_device *pdev) }return 0 ; + +err_remove_domain: +irq_domain_remove (tb10x_gpio->domain); +return ret; }static int tb10x_gpio_remove (struct platform_device *pdev)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 69/183 i2c: mux: demux-pinctrl: check the return value of devm_kstrdup()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Xiaoke Wang <[email protected]>
[ Upstream commit 7c0195fa9a9e263df204963f88a22b21688ffb66 ]
devm_kstrdup() returns pointer to allocated string on success, NULL on failure. So it is better to check the return value of it.
--- drivers/i2c/muxes/i2c-demux-pinctrl.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/i2c/muxes/i2c-demux-pinctrl.c +4 -0
@@ -243,6 +243,10 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev) props[i].name =devm_kstrdup (&pdev->dev,"status" ,GFP_KERNEL ); props[i].value =devm_kstrdup (&pdev->dev,"ok" ,GFP_KERNEL ); +if (!props[i].name || !props[i].value) { + err = -ENOMEM ; + goto err_rollback; + } props[i].length =3 ;of_changeset_init (&priv->chan[i].chgset);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 70/183 i2c: mux: gpio: Replace custom acpi_get_local_address()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Andy Shevchenko <[email protected]>
[ Upstream commit 379920f5c013c49e0a740634972faf77e26d4ac3 ]
Recently ACPI gained the acpi_get_local_address() API which may be used instead of home grown i2c_mux_gpio_get_acpi_adr().
Stable-dep-of: db6aee6083a5 ("i2c: mux: gpio: Add missing fwnode_handle_put()")
--- drivers/i2c/muxes/i2c-mux-gpio.c | 43 ++------------------------------ 1 file changed, 2 insertions(+), 41 deletions(-)
drivers/i2c/muxes/i2c-mux-gpio.c +2 -41
@@ -49,45 +49,6 @@ static int i2c_mux_gpio_deselect(struct i2c_mux_core *muxc, u32 chan)return 0 ; } -#ifdef CONFIG_ACPI - -static int i2c_mux_gpio_get_acpi_adr (struct device *dev, -struct fwnode_handle *fwdev, -unsigned int *adr) - -{ -unsigned long long adr64; -acpi_status status; - - status =acpi_evaluate_integer (ACPI_HANDLE_FWNODE (fwdev), -METHOD_NAME__ADR , -NULL , &adr64); - -if (!ACPI_SUCCESS (status)) { -dev_err (dev,"Cannot get address\n" ); -return -EINVAL ; - } - - *adr = adr64; -if (*adr != adr64) { -dev_err (dev,"Address out of range\n" ); -return -ERANGE ; - } - -return 0 ; -} - -#else - -static int i2c_mux_gpio_get_acpi_adr (struct device *dev, -struct fwnode_handle *fwdev, -unsigned int *adr) -{ -return -EINVAL ; -} - -#endif -static int i2c_mux_gpio_probe_fw (struct gpiomux *mux,struct platform_device *pdev) {
@@ -141,9 +102,9 @@ static int i2c_mux_gpio_probe_fw(struct gpiomux *mux,fwnode_property_read_u32 (child,"reg" , values + i); }else if (is_acpi_node (child)) { - rc =i2c_mux_gpio_get_acpi_adr (dev, child, values + i); + rc =acpi_get_local_address (ACPI_HANDLE_FWNODE (child), values + i);if (rc) -return rc; +return dev_err_probe (dev, rc,"Cannot get address\n" ); } i++;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 71/183 i2c: mux: gpio: Add missing fwnode_handle_put()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Liang He <[email protected]>
[ Upstream commit db6aee6083a56ac4a6cd1b08fff7938072bcd0a3 ]
In i2c_mux_gpio_probe_fw(), we should add fwnode_handle_put() when break out of the iteration device_for_each_child_node() as it will automatically increase and decrease the refcounter.
--- drivers/i2c/muxes/i2c-mux-gpio.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/i2c/muxes/i2c-mux-gpio.c +3 -1
@@ -103,8 +103,10 @@ static int i2c_mux_gpio_probe_fw(struct gpiomux *mux, }else if (is_acpi_node (child)) { rc =acpi_get_local_address (ACPI_HANDLE_FWNODE (child), values + i); -if (rc) +if (rc) { +fwnode_handle_put (child);return dev_err_probe (dev, rc,"Cannot get address\n" ); + } } i++;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 72/183 xfs: bound maximum wait time for inodegc work
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dave Chinner <[email protected]>
[ Upstream commit 7cf2b0f9611b9971d663e1fc3206eeda3b902922 ]
Currently inodegc work can sit queued on the per-cpu queue until the workqueue is either flushed of the queue reaches a depth that triggers work queuing (and later throttling). This means that we could queue work that waits for a long time for some other event to trigger flushing.
Hence instead of just queueing work at a specific depth, use a delayed work that queues the work at a bound time. We can still schedule the work immediately at a given depth, but we no long need to worry about leaving a number of items on the list that won't get processed until external events prevail.
--- fs/xfs/xfs_icache.c | 36 ++++++++++++++++++++++-------------- fs/xfs/xfs_mount.h | 2 +- fs/xfs/xfs_super.c | 2 +- 3 files changed, 24 insertions(+), 16 deletions(-)
fs/xfs/xfs_icache.c +22 -14
@@ -458,7 +458,7 @@ xfs_inodegc_queue_all(for_each_online_cpu (cpu) { gc =per_cpu_ptr (mp->m_inodegc, cpu);if (!llist_empty (&gc->list)) -queue_work_on (cpu, mp->m_inodegc_wq, &gc->work); +mod_delayed_work_on (cpu, mp->m_inodegc_wq, &gc->work,0 ); } }
@@ -1851,8 +1851,8 @@ voidxfs_inodegc_worker ( struct work_struct *work) { - struct xfs_inodegc *gc = container_of(work, struct xfs_inodegc, - work); +struct xfs_inodegc *gc =container_of (to_delayed_work (work), + struct xfs_inodegc, work);struct llist_node *node =llist_del_all (&gc->list);struct xfs_inode *ip, *n;
@@ -2021,6 +2021,7 @@ xfs_inodegc_queue(struct xfs_inodegc *gc;int items;unsigned int shrinker_hits; +unsigned long queue_delay =1 ;trace_xfs_inode_set_need_inactive (ip);spin_lock (&ip->i_flags_lock);
@@ -2032,19 +2033,26 @@ xfs_inodegc_queue( items =READ_ONCE (gc->items);WRITE_ONCE (gc->items, items +1 ); shrinker_hits =READ_ONCE (gc->shrinker_hits); -put_cpu_ptr (gc); -if (!xfs_is_inodegc_enabled (mp)) +/* +* We queue the work while holding the current CPU so that the work +* is scheduled to run on this CPU. +*/ +if (!xfs_is_inodegc_enabled (mp)) { +put_cpu_ptr (gc);return ; - -if (xfs_inodegc_want_queue_work (ip, items)) { -trace_xfs_inodegc_queue (mp, __return_address); -queue_work (mp->m_inodegc_wq, &gc->work); } +if (xfs_inodegc_want_queue_work (ip, items)) + queue_delay =0 ; + +trace_xfs_inodegc_queue (mp, __return_address); +mod_delayed_work (mp->m_inodegc_wq, &gc->work, queue_delay); +put_cpu_ptr (gc); +if (xfs_inodegc_want_flush_work (ip, items, shrinker_hits)) {trace_xfs_inodegc_throttle (mp, __return_address); -flush_work (&gc->work); +flush_delayed_work (&gc->work); } }
@@ -2061,7 +2069,7 @@ xfs_inodegc_cpu_dead(unsigned int count =0 ; dead_gc =per_cpu_ptr (mp->m_inodegc, dead_cpu); -cancel_work_sync (&dead_gc->work); +cancel_delayed_work_sync (&dead_gc->work);if (llist_empty (&dead_gc->list))return ;
@@ -2080,12 +2088,12 @@ xfs_inodegc_cpu_dead(llist_add_batch (first, last, &gc->list); count +=READ_ONCE (gc->items);WRITE_ONCE (gc->items, count); -put_cpu_ptr (gc);if (xfs_is_inodegc_enabled (mp)) {trace_xfs_inodegc_queue (mp, __return_address); -queue_work (mp->m_inodegc_wq, &gc->work); +mod_delayed_work (mp->m_inodegc_wq, &gc->work,0 ); } +put_cpu_ptr (gc); }/*
@@ -2180,7 +2188,7 @@ xfs_inodegc_shrinker_scan(unsigned int h =READ_ONCE (gc->shrinker_hits);WRITE_ONCE (gc->shrinker_hits, h +1 ); -queue_work_on (cpu, mp->m_inodegc_wq, &gc->work); +mod_delayed_work_on (cpu, mp->m_inodegc_wq, &gc->work,0 ); no_items = false; } }
fs/xfs/xfs_mount.h +1 -1
@@ -61,7 +61,7 @@ struct xfs_error_cfg {*/ struct xfs_inodegc {struct llist_head list; -struct work_struct work; +struct delayed_work work;/* approximate count of inodes in the list */ unsigned int items;
fs/xfs/xfs_super.c +1 -1
@@ -1061,7 +1061,7 @@ xfs_inodegc_init_percpu( gc =per_cpu_ptr (mp->m_inodegc, cpu);init_llist_head (&gc->list); gc->items =0 ; -INIT_WORK (&gc->work, xfs_inodegc_worker); +INIT_DELAYED_WORK (&gc->work, xfs_inodegc_worker); }return 0 ; }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 73/183 xfs: introduce xfs_inodegc_push()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dave Chinner <[email protected]>
[ Upstream commit 5e672cd69f0a534a445df4372141fd0d1d00901d ]
The current blocking mechanism for pushing the inodegc queue out to disk can result in systems becoming unusable when there is a long running inodegc operation. This is because the statfs() implementation currently issues a blocking flush of the inodegc queue and a significant number of common system utilities will call statfs() to discover something about the underlying filesystem.
This can result in userspace operations getting stuck on inodegc progress, and when trying to remove a heavily reflinked file on slow storage with a full journal, this can result in delays measuring in hours.
Avoid this problem by adding "push" function that expedites the flushing of the inodegc queue, but doesn't wait for it to complete.
Convert xfs_fs_statfs() and xfs_qm_scall_getquota() to use this mechanism so they don't block but still ensure that queued operations are expedited.
--- fs/xfs/xfs_icache.c | 20 +++++++++++++++----- fs/xfs/xfs_icache.h | 1 + fs/xfs/xfs_qm_syscalls.c | 9 ++++++--- fs/xfs/xfs_super.c | 7 +++++-- fs/xfs/xfs_trace.h | 1 + 5 files changed, 28 insertions(+), 10 deletions(-)
fs/xfs/xfs_icache.c +15 -5
@@ -1872,19 +1872,29 @@ xfs_inodegc_worker( }/* -* Force all currently queued inode inactivation work to run immediately and -* wait for the work to finish. +* Expedite all pending inodegc work to run immediately. This does not wait for +* completion of the work. */ void -xfs_inodegc_flush ( +xfs_inodegc_push (struct xfs_mount *mp) {if (!xfs_is_inodegc_enabled (mp))return ; +trace_xfs_inodegc_push (mp, __return_address); +xfs_inodegc_queue_all (mp); +} +/* +* Force all currently queued inode inactivation work to run immediately and +* wait for the work to finish. +*/ +void +xfs_inodegc_flush ( +struct xfs_mount *mp) +{ +xfs_inodegc_push (mp);trace_xfs_inodegc_flush (mp, __return_address); - -xfs_inodegc_queue_all (mp);flush_workqueue (mp->m_inodegc_wq); }
fs/xfs/xfs_icache.h +1 -0
@@ -76,6 +76,7 @@ void xfs_blockgc_stop(struct xfs_mount *mp);void xfs_blockgc_start (struct xfs_mount *mp);void xfs_inodegc_worker (struct work_struct *work); +void xfs_inodegc_push (struct xfs_mount *mp);void xfs_inodegc_flush (struct xfs_mount *mp);void xfs_inodegc_stop (struct xfs_mount *mp);void xfs_inodegc_start (struct xfs_mount *mp);
fs/xfs/xfs_qm_syscalls.c +6 -3
@@ -481,9 +481,12 @@ xfs_qm_scall_getquota(struct xfs_dquot *dqp;int error; -/* Flush inodegc work at the start of a quota reporting scan. */ +/* +* Expedite pending inodegc work at the start of a quota reporting +* scan but don't block waiting for it to complete. +*/ if (id ==0 ) -xfs_inodegc_flush (mp); +xfs_inodegc_push (mp);/* * Try to get the dquot. We don't want it allocated on disk, so don't
@@ -525,7 +528,7 @@ xfs_qm_scall_getquota_next(/* Flush inodegc work at the start of a quota reporting scan. */ if (*id ==0 ) -xfs_inodegc_flush (mp); +xfs_inodegc_push (mp); error =xfs_qm_dqget_next (mp, *id, type, &dqp);if (error)
fs/xfs/xfs_super.c +5 -2
@@ -795,8 +795,11 @@ xfs_fs_statfs(xfs_extlen_t lsize;int64_t ffree; -/* Wait for whatever inactivations are in progress. */ -xfs_inodegc_flush (mp); +/* +* Expedite background inodegc but don't wait. We do not want to block +* here waiting hours for a billion extent file to be truncated. +*/ +xfs_inodegc_push (mp); statp->f_type =XFS_SUPER_MAGIC ; statp->f_namelen =MAXNAMELEN -1 ;
fs/xfs/xfs_trace.h +1 -0
@@ -240,6 +240,7 @@ DEFINE_EVENT(xfs_fs_class, name, \ TP_PROTO(struct xfs_mount *mp, void *caller_ip), \ TP_ARGS(mp, caller_ip)) DEFINE_FS_EVENT(xfs_inodegc_flush); +DEFINE_FS_EVENT (xfs_inodegc_push);DEFINE_FS_EVENT (xfs_inodegc_start);DEFINE_FS_EVENT (xfs_inodegc_stop);DEFINE_FS_EVENT (xfs_inodegc_queue);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 74/183 xfs: explicitly specify cpu when forcing inodegc delayed work to run immediately
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Darrick J. Wong <[email protected]>
[ Upstream commit 03e0add80f4cf3f7393edb574eeb3a89a1db7758 ]
I've been noticing odd racing behavior in the inodegc code that could only be explained by one cpu adding an inode to its inactivation llist at the same time that another cpu is processing that cpu's llist. Preemption is disabled between get/put_cpu_ptr, so the only explanation is scheduler mayhem. I inserted the following debug code into xfs_inodegc_worker (see the next patch):
ASSERT(gc->cpu == smp_processor_id());
This assertion tripped during overnight tests on the arm64 machines, but curiously not on x86_64. I think we haven't observed any resource leaks here because the lockfree list code can handle simultaneous llist_add and llist_del_all functions operating on the same list. However, the whole point of having percpu inodegc lists is to take advantage of warm memory caches by inactivating inodes on the last processor to touch the inode.
The incorrect scheduling seems to occur after an inodegc worker is subjected to mod_delayed_work(). This wraps mod_delayed_work_on with WORK_CPU_UNBOUND specified as the cpu number. Unbound allows for scheduling on any cpu, not necessarily the same one that scheduled the work.
Because preemption is disabled for as long as we have the gc pointer, I think it's safe to use current_cpu() (aka smp_processor_id) to queue the delayed work item on the correct cpu.
--- fs/xfs/xfs_icache.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
fs/xfs/xfs_icache.c +4 -2
@@ -2057,7 +2057,8 @@ xfs_inodegc_queue( queue_delay =0 ;trace_xfs_inodegc_queue (mp, __return_address); -mod_delayed_work (mp->m_inodegc_wq, &gc->work, queue_delay); +mod_delayed_work_on (current_cpu (), mp->m_inodegc_wq, &gc->work, + queue_delay);put_cpu_ptr (gc);if (xfs_inodegc_want_flush_work (ip, items, shrinker_hits)) {
@@ -2101,7 +2102,8 @@ xfs_inodegc_cpu_dead(if (xfs_is_inodegc_enabled (mp)) {trace_xfs_inodegc_queue (mp, __return_address); -mod_delayed_work (mp->m_inodegc_wq, &gc->work,0 ); +mod_delayed_work_on (current_cpu (), mp->m_inodegc_wq, &gc->work, +0 ); }put_cpu_ptr (gc); }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 75/183 xfs: check that per-cpu inodegc workers actually run on that cpu
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Darrick J. Wong <[email protected]>
[ Upstream commit b37c4c8339cd394ea6b8b415026603320a185651 ]
Now that we've allegedly worked out the problem of the per-cpu inodegc workers being scheduled on the wrong cpu, let's put in a debugging knob to let us know if a worker ever gets mis-scheduled again.
--- fs/xfs/xfs_icache.c | 2 ++ fs/xfs/xfs_mount.h | 3 +++ fs/xfs/xfs_super.c | 3 +++ 3 files changed, 8 insertions(+)
fs/xfs/xfs_icache.c +2 -0
@@ -1856,6 +1856,8 @@ xfs_inodegc_worker(struct llist_node *node =llist_del_all (&gc->list);struct xfs_inode *ip, *n; +ASSERT (gc->cpu ==smp_processor_id ()); +WRITE_ONCE (gc->items,0 );if (!node)
fs/xfs/xfs_mount.h +3 -0
@@ -66,6 +66,9 @@ struct xfs_inodegc {/* approximate count of inodes in the list */ unsigned int items;unsigned int shrinker_hits; +#if defined(DEBUG ) || defined(XFS_WARN ) +unsigned int cpu; +#endif };/*
fs/xfs/xfs_super.c +3 -0
@@ -1062,6 +1062,9 @@ xfs_inodegc_init_percpu(for_each_possible_cpu (cpu) { gc =per_cpu_ptr (mp->m_inodegc, cpu); +#if defined(DEBUG ) || defined(XFS_WARN ) + gc->cpu = cpu; +#endif init_llist_head (&gc->list); gc->items =0 ;INIT_DELAYED_WORK (&gc->work, xfs_inodegc_worker);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 76/183 xfs: disable reaping in fscounters scrub
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Darrick J. Wong <[email protected]>
[ Upstream commit 2d5f38a31980d7090f5bf91021488dc61a0ba8ee ]
The fscounters scrub code doesn't work properly because it cannot quiesce updates to the percpu counters in the filesystem, hence it returns false corruption reports. This has been fixed properly in one of the online repair patchsets that are under review by replacing the xchk_disable_reaping calls with an exclusive filesystem freeze. Disabling background gc isn't sufficient to fix the problem.
In other words, scrub doesn't need to call xfs_inodegc_stop, which is just as well since it wasn't correct to allow scrub to call xfs_inodegc_start when something else could be calling xfs_inodegc_stop (e.g. trying to freeze the filesystem).
Neuter the scrubber for now, and remove the xchk_*_reaping functions.
--- fs/xfs/scrub/common.c | 25 ------------------------- fs/xfs/scrub/common.h | 2 -- fs/xfs/scrub/fscounters.c | 13 ++++++------- fs/xfs/scrub/scrub.c | 2 -- fs/xfs/scrub/scrub.h | 1 - 5 files changed, 6 insertions(+), 37 deletions(-)
fs/xfs/scrub/common.c +0 -25
@@ -864,28 +864,3 @@ xchk_ilock_inverted(return -EDEADLOCK ; } -/* Pause background reaping of resources. */ -void -xchk_stop_reaping ( -struct xfs_scrub *sc) -{ - sc->flags |=XCHK_REAPING_DISABLED ; -xfs_blockgc_stop (sc->mp); -xfs_inodegc_stop (sc->mp); -} - -/* Restart background reaping of resources. */ -void -xchk_start_reaping ( -struct xfs_scrub *sc) -{ -/* -* Readonly filesystems do not perform inactivation or speculative -* preallocation, so there's no need to restart the workers. -*/ -if (!xfs_is_readonly (sc->mp)) { -xfs_inodegc_start (sc->mp); -xfs_blockgc_start (sc->mp); - } - sc->flags &= ~XCHK_REAPING_DISABLED ; -}
fs/xfs/scrub/common.h +0 -2
@@ -148,7 +148,5 @@ static inline bool xchk_skip_xref(struct xfs_scrub_metadata *sm)int xchk_metadata_inode_forks (struct xfs_scrub *sc);int xchk_ilock_inverted (struct xfs_inode *ip,uint lock_mode); -void xchk_stop_reaping (struct xfs_scrub *sc); -void xchk_start_reaping (struct xfs_scrub *sc);#endif /* __XFS_SCRUB_COMMON_H__ */
fs/xfs/scrub/fscounters.c +6 -7
@@ -128,13 +128,6 @@ xchk_setup_fscounters(if (error)return error; -/* -* Pause background reclaim while we're scrubbing to reduce the -* likelihood of background perturbations to the counters throwing off -* our calculations. -*/ -xchk_stop_reaping (sc); -return xchk_trans_alloc (sc,0 ); }
@@ -353,6 +346,12 @@ xchk_fscounters(if (fdblocks > mp->m_sb.sb_dblocks)xchk_set_corrupt (sc); +/* +* XXX: We can't quiesce percpu counter updates, so exit early. +* This can be re-enabled when we gain exclusive freeze functionality. +*/ +return 0 ; +/* * If ifree exceeds icount by more than the minimum variance then * something's probably wrong with the counters.
fs/xfs/scrub/scrub.c +0 -2
@@ -171,8 +171,6 @@ xchk_teardown( }if (sc->sm->sm_flags &XFS_SCRUB_IFLAG_REPAIR )mnt_drop_write_file (sc->file); -if (sc->flags &XCHK_REAPING_DISABLED ) -xchk_start_reaping (sc);if (sc->flags &XCHK_HAS_QUOTAOFFLOCK ) {mutex_unlock (&sc->mp->m_quotainfo->qi_quotaofflock); sc->flags &= ~XCHK_HAS_QUOTAOFFLOCK ;
fs/xfs/scrub/scrub.h +0 -1
@@ -89,7 +89,6 @@ struct xfs_scrub {/* XCHK state flags grow up from zero, XREP state flags grown down from 2^31 */ #define XCHK_TRY_HARDER (1 << 0)/* can't get resources, try again */ #define XCHK_HAS_QUOTAOFFLOCK (1 << 1)/* we hold the quotaoff lock */ -#define XCHK_REAPING_DISABLED (1 << 2)/* background block reaping paused */ #define XREP_ALREADY_FIXED (1 << 31)/* checking our repair work */ /* Metadata scrubbers */
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 77/183 xfs: fix xfs_inodegc_stop racing with mod_delayed_work
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Darrick J. Wong <[email protected]>
[ Upstream commit 2254a7396a0ca6309854948ee1c0a33fa4268cec ]
syzbot reported this warning from the faux inodegc shrinker that tries to kick off inodegc work:
------------[ cut here ]------------ WARNING: CPU: 1 PID: 102 at kernel/workqueue.c:1445 __queue_work+0xd44/0x1120 kernel/workqueue.c:1444 RIP: 0010:__queue_work+0xd44/0x1120 kernel/workqueue.c:1444 Call Trace: __queue_delayed_work+0x1c8/0x270 kernel/workqueue.c:1672 mod_delayed_work_on+0xe1/0x220 kernel/workqueue.c:1746 xfs_inodegc_shrinker_scan fs/xfs/xfs_icache.c:2212 [inline] xfs_inodegc_shrinker_scan+0x250/0x4f0 fs/xfs/xfs_icache.c:2191 do_shrink_slab+0x428/0xaa0 mm/vmscan.c:853 shrink_slab+0x175/0x660 mm/vmscan.c:1013 shrink_one+0x502/0x810 mm/vmscan.c:5343 shrink_many mm/vmscan.c:5394 [inline] lru_gen_shrink_node mm/vmscan.c:5511 [inline] shrink_node+0x2064/0x35f0 mm/vmscan.c:6459 kswapd_shrink_node mm/vmscan.c:7262 [inline] balance_pgdat+0xa02/0x1ac0 mm/vmscan.c:7452 kswapd+0x677/0xd60 mm/vmscan.c:7712 kthread+0x2e8/0x3a0 kernel/kthread.c:376 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:308
This warning corresponds to this code in __queue_work:
/* * For a draining wq, only works from the same workqueue are * allowed. The __WQ_DESTROYING helps to spot the issue that * queues a new work item to a wq after destroy_workqueue(wq). */ if (unlikely(wq->flags & (__WQ_DESTROYING | __WQ_DRAINING) && WARN_ON_ONCE(!is_chained_work(wq)))) return;
For this to trip, we must have a thread draining the inodedgc workqueue and a second thread trying to queue inodegc work to that workqueue. This can happen if freezing or a ro remount race with reclaim poking our faux inodegc shrinker and another thread dropping an unlinked O_RDONLY file:
Thread 0 Thread 1 Thread 2
xfs_inodegc_stop
xfs_inodegc_shrinker_scan xfs_is_inodegc_enabled <yes, will continue>
xfs_clear_inodegc_enabledxfs_inodegc_queue_all
<list empty, do not queue inodegc worker>
xfs_inodegc_queue
<add to list>
xfs_is_inodegc_enabled
<no, returns>
drain_workqueue
<set WQ_DRAINING>
llist_empty
<no, will queue list> mod_delayed_work_on(..., 0) __queue_work
<sees WQ_DRAINING, kaboom>
In other words, everything between the access to inodegc_enabled state and the decision to poke the inodegc workqueue requires some kind of coordination to avoid the WQ_DRAINING state. We could perhaps introduce a lock here, but we could also try to eliminate WQ_DRAINING from the picture.
We could replace the drain_workqueue call with a loop that flushes the workqueue and queues workers as long as there is at least one inode present in the per-cpu inodegc llists. We've disabled inodegc at this point, so we know that the number of queued inodes will eventually hit zero as long as xfs_inodegc_start cannot reactivate the workers.
There are four callers of xfs_inodegc_start. Three of them come from the VFS with s_umount held: filesystem thawing, failed filesystem freezing, and the rw remount transition. The fourth caller is mounting rw (no remount or freezing possible).
There are three callers ofs xfs_inodegc_stop. One is unmounting (no remount or thaw possible). Two of them come from the VFS with s_umount
held: fs freezing and ro remount transition.
Hence, it is correct to replace the drain_workqueue call with a loop that drains the inodegc llists.
--- fs/xfs/xfs_icache.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-)
fs/xfs/xfs_icache.c +27 -5
@@ -448,18 +448,23 @@ xfs_iget_check_free_state( }/* Make all pending inactivation work start immediately. */ -static void +static bool xfs_inodegc_queue_all (struct xfs_mount *mp) {struct xfs_inodegc *gc;int cpu; +bool ret = false;for_each_online_cpu (cpu) { gc =per_cpu_ptr (mp->m_inodegc, cpu); -if (!llist_empty (&gc->list)) +if (!llist_empty (&gc->list)) {mod_delayed_work_on (cpu, mp->m_inodegc_wq, &gc->work,0 ); + ret = true; + } } + +return ret; }/*
@@ -1902,24 +1907,41 @@ xfs_inodegc_flush(/* * Flush all the pending work and then disable the inode inactivation background -* workers and wait for them to stop. +* workers and wait for them to stop. Caller must hold sb->s_umount to +* coordinate changes in the inodegc_enabled state. */ void xfs_inodegc_stop (struct xfs_mount *mp) { +bool rerun; +if (!xfs_clear_inodegc_enabled (mp))return ; +/* +* Drain all pending inodegc work, including inodes that could be +* queued by racing xfs_inodegc_queue or xfs_inodegc_shrinker_scan +* threads that sample the inodegc state just prior to us clearing it. +* The inodegc flag state prevents new threads from queuing more +* inodes, so we queue pending work items and flush the workqueue until +* all inodegc lists are empty. IOWs, we cannot use drain_workqueue +* here because it does not allow other unserialized mechanisms to +* reschedule inodegc work while this draining is in progress. +*/ xfs_inodegc_queue_all (mp); -drain_workqueue (mp->m_inodegc_wq); +do { +flush_workqueue (mp->m_inodegc_wq); + rerun =xfs_inodegc_queue_all (mp); + }while (rerun);trace_xfs_inodegc_stop (mp, __return_address); }/* * Enable the inode inactivation background workers and schedule deferred inode -* inactivation work if there is any. +* inactivation work if there is any. Caller must hold sb->s_umount to +* coordinate changes in the inodegc_enabled state. */ void xfs_inodegc_start(
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 78/183 Input: i8042 - rename i8042-x86ia64io.h to i8042-acpipnpio.h
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Huacai Chen <[email protected]>
[ Upstream commit 8761b9b580d53162cca7868385069c0d4354c9e0 ]
Now i8042-x86ia64io.h is shared by X86 and IA64, but it can be shared by more platforms (such as LoongArch) with ACPI firmware on which PNP typed keyboard and mouse is configured in DSDT. So rename it to i8042- acpipnpio.h.
Stable-dep-of: eb09074bdb05 ("Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN")
---
.../input/serio/{i8042-x86ia64io.h => i8042-acpipnpio.h} | 6 +++---
drivers/input/serio/i8042.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
rename drivers/input/serio/{i8042-x86ia64io.h => i8042-acpipnpio.h} (99%)drivers/input/serio/i8042-acpipnpio.h renamed from drivers/input/serio/i8042-x86ia64io.h +3 -3
@@ -1,6 +1,6 @@/* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _I8042_X86IA64IO_H -#define _I8042_X86IA64IO_H +#ifndef _I8042_ACPIPNPIO_H +#define _I8042_ACPIPNPIO_H#ifdef CONFIG_X86
@@ -1647,4 +1647,4 @@ static inline void i8042_platform_exit(void) i8042_pnp_exit(); } -#endif /* _I8042_X86IA64IO_H */ +#endif /* _I8042_ACPIPNPIO_H */
drivers/input/serio/i8042.h +1 -1
@@ -20,7 +20,7 @@#elif defined(CONFIG_SPARC )#include "i8042-sparcio.h" #elif defined(CONFIG_X86 ) || defined(CONFIG_IA64 ) -#include "i8042-x86ia64io.h" +#include "i8042-acpipnpio.h" #else #include "i8042-io.h" #endif
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 79/183 Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Werner Sembach <[email protected]>
[ Upstream commit eb09074bdb05ffd6bfe77f8b4a41b76ef78c997b ]
The touchpad of this device is both connected via PS/2 and i2c. This causes strange behavior when both driver fight for control. The easy fix is to prevent the PS/2 driver from accessing the mouse port as the full feature set of the touchpad is only supported in the i2c interface anyway.
The strange behavior in this case is, that when an external screen is connected and the notebook is closed, the pointer on the external screen is moving to the lower right corner. When the notebook is opened again, this movement stops, but the touchpad clicks are unresponsive afterwards until reboot.
--- drivers/input/serio/i8042-acpipnpio.h | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/input/serio/i8042-acpipnpio.h +7 -0
@@ -1244,6 +1244,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) }, +/* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */ + { + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOAUX ) + }, { .matches = { DMI_MATCH(DMI_BOARD_NAME, "X170SM"),
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 80/183 perf jevents: Switch build to use jevents.py
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Ian Rogers <[email protected]>
[ Upstream commit 00facc760903be6675870c2749e2cd72140e396e ]
Generate pmu-events.c using jevents.py rather than the binary built from jevents.c.
Add a new config variable NO_JEVENTS that is set when there is no architecture json or an appropriate python interpreter isn't present.
When NO_JEVENTS is defined the file pmu-events/empty-pmu-events.c is copied and used as the pmu-events.c file.
Stable-dep-of: 7822a8913f4c ("perf build: Update build rule for generated files")
--- tools/perf/Makefile.config | 19 +++ tools/perf/Makefile.perf | 1 + tools/perf/pmu-events/Build | 13 +- tools/perf/pmu-events/empty-pmu-events.c | 158 +++++++++++++++++++++++ 4 files changed, 189 insertions(+), 2 deletions(-) create mode 100644 tools/perf/pmu-events/empty-pmu-events.c
tools/perf/Makefile.config +19 -0
@@ -857,6 +857,25 @@ else endif endif +ifneq ($(NO_JEVENTS),1) + ifeq ($(wildcard pmu-events/arch/$(SRCARCH)/mapfile.csv),) + NO_JEVENTS := 1 + endif +endif +ifneq ($(NO_JEVENTS),1) + NO_JEVENTS := 0 + ifndef PYTHON + $(warning No python interpreter disabling jevent generation) + NO_JEVENTS := 1 + else + # jevents.py uses f-strings present in Python 3.6 released in Dec. 2016. + JEVENTS_PYTHON_GOOD := $(shell $(PYTHON) -c 'import sys;print("1" if(sys.version_info.major >= 3 and sys.version_info.minor >= 6) else "0")' 2> /dev/null) + ifneq ($(JEVENTS_PYTHON_GOOD), 1) + $(warning Python interpreter too old (older than 3.6) disabling jevent generation) + NO_JEVENTS := 1 + endif + endif +endif ifndef NO_LIBBFD ifeq ($(feature-libbfd), 1)
tools/perf/Makefile.perf +1 -0
@@ -649,6 +649,7 @@ JEVENTS := $(OUTPUT)pmu-events/jevents JEVENTS_IN := $(OUTPUT)pmu-events/jevents-in.o PMU_EVENTS_IN := $(OUTPUT)pmu-events/pmu-events-in.o +export NO_JEVENTS export JEVENTS
tools/perf/pmu-events/Build +11 -2
@@ -9,10 +9,19 @@ JSON = $(shell [ -d $(JDIR) ] && \ JDIR_TEST = pmu-events/arch/test JSON_TEST = $(shell [ -d $(JDIR_TEST) ] && \ find $(JDIR_TEST) -name '*.json') +JEVENTS_PY = pmu-events/jevents.py # # Locate/process JSON files in pmu-events/arch/ # directory and create tables in pmu-events.c. # -$(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS) - $(Q)$(call echo-cmd,gen)$(JEVENTS) $(SRCARCH) pmu-events/arch $(OUTPUT)pmu-events/pmu-events.c $(V) + +ifeq ($(NO_JEVENTS),1) +$(OUTPUT)pmu-events/pmu-events.c: pmu-events/empty-pmu-events.c + $(call rule_mkdir) + $(Q)$(call echo-cmd,gen)cp $< $@ +else +$(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS_PY) + $(call rule_mkdir) + $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(SRCARCH) pmu-events/arch $@ +endif
tools/perf/pmu-events/empty-pmu-events.c new file +158 -0
158 lines not on this page · raw message
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 81/183 perf build: Update build rule for generated files
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Namhyung Kim <[email protected]>
[ Upstream commit 7822a8913f4c51c7d1aff793b525d60c3384fb5b ]
The bison and flex generate C files from the source (.y and .l) files. When O= option is used, they are saved in a separate directory but the default build rule assumes the .C files are in the source directory. So it might read invalid file if there are generated files from an old version. The same is true for the pmu-events files.
For example, the following command would cause a build failure:
$ git checkout v6.3 $ make -C tools/perf # build in the same directory
$ git checkout v6.5-rc2
$ mkdir build # create a build directory
$ make -C tools/perf O=build # build in a different directory but it
# refers files in the source directoryLet's update the build rule to specify those cases explicitly to depend on the files in the output directory.
Note that it's not a complete fix and it needs the next patch for the include path too.
--- tools/build/Makefile.build | 10 ++++++++++ tools/perf/pmu-events/Build | 6 ++++++ 2 files changed, 16 insertions(+)
tools/build/Makefile.build +10 -0
@@ -116,6 +116,16 @@ $(OUTPUT)%.s: %.c FORCE $(call rule_mkdir) $(call if_changed_dep,cc_s_c) +# bison and flex files are generated in the OUTPUT directory +# so it needs a separate rule to depend on them properly +$(OUTPUT)%-bison.o: $(OUTPUT)%-bison.c FORCE + $(call rule_mkdir) + $(call if_changed_dep,$(host)cc_o_c) + +$(OUTPUT)%-flex.o: $(OUTPUT)%-flex.c FORCE + $(call rule_mkdir) + $(call if_changed_dep,$(host)cc_o_c) + # Gather build data: # obj-y - list of build objects # subdir-y - list of directories to nest
tools/perf/pmu-events/Build +6 -0
@@ -25,3 +25,9 @@ $(OUTPUT)pmu-events/pmu-events.c: $(JSON) $(JSON_TEST) $(JEVENTS_PY) $(call rule_mkdir) $(Q)$(call echo-cmd,gen)$(PYTHON) $(JEVENTS_PY) $(SRCARCH) pmu-events/arch $@ endif + +# pmu-events.c file is generated in the OUTPUT directory so it needs a +# separate rule to depend on it properly +$(OUTPUT)pmu-events/pmu-events.o: $(PMU_EVENTS_C) + $(call rule_mkdir) + $(call if_changed_dep,cc_o_c)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 82/183 netfilter: exthdr: add support for tcp option removal
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Florian Westphal <[email protected]>
[ Upstream commit 7890cbea66e78a3a6037b2a12827118d7243270b ]
This allows to replace a tcp option with nop padding to selectively disable a particular tcp option.
Optstrip mode is chosen when userspace passes the exthdr expression with neither a source nor a destination register attribute.
This is identical to xtables TCPOPTSTRIP extension.
The only difference is that TCPOPTSTRIP allows to pass in a bitmap of options to remove rather than a single number.
Unlike TCPOPTSTRIP this expression can be used multiple times in the same rule to get the same effect.
We could add a new nested attribute later on in case there is a use case for single-expression-multi-remove.
Stable-dep-of: 28427f368f0e ("netfilter: nft_exthdr: Fix non-linear header modification")
--- net/netfilter/nft_exthdr.c | 96 +++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-)
net/netfilter/nft_exthdr.c +95 -1
@@ -315,6 +315,63 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr, regs->verdict.code =NFT_BREAK ; } +static void nft_exthdr_tcp_strip_eval (const struct nft_expr *expr, +struct nft_regs *regs, +const struct nft_pktinfo *pkt) +{ +u8 buff[sizeof (struct tcphdr ) +MAX_TCP_OPTION_SPACE ]; +struct nft_exthdr *priv =nft_expr_priv (expr); +unsigned int i, tcphdr_len, optl; +struct tcphdr *tcph; +u8 *opt; + + tcph =nft_tcp_header_pointer (pkt,sizeof (buff), buff, &tcphdr_len); +if (!tcph) + goto err; + +if (skb_ensure_writable (pkt->skb,nft_thoff (pkt) + tcphdr_len)) + goto drop; + + opt = (u8 *)nft_tcp_header_pointer (pkt,sizeof (buff), buff, &tcphdr_len); +if (!opt) + goto err; +for (i =sizeof (*tcph); i < tcphdr_len -1 ; i += optl) { +unsigned int j; + + optl =optlen (opt, i); +if (priv->type != opt[i]) +continue ; + +if (i + optl > tcphdr_len) + goto drop; + +for (j =0 ; j < optl; ++j) { +u16 n =TCPOPT_NOP ; +u16 o = opt[i+j]; + +if ((i + j) %2 ==0 ) { + o <<=8 ; + n <<=8 ; + } +inet_proto_csum_replace2 (&tcph->check, pkt->skb,htons (o), +htons (n), false); + } +memset (opt + i,TCPOPT_NOP , optl); +return ; + } + +/* option not found, continue. This allows to do multiple +* option removals per rule. +*/ +return ; +err: + regs->verdict.code =NFT_BREAK ; +return ; +drop: +/* can't remove, no choice but to drop */ + regs->verdict.code =NF_DROP ; +} +static void nft_exthdr_sctp_eval (const struct nft_expr *expr,struct nft_regs *regs,const struct nft_pktinfo *pkt)
@@ -463,6 +520,28 @@ static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, priv->len); } +static int nft_exthdr_tcp_strip_init (const struct nft_ctx *ctx, +const struct nft_expr *expr, +const struct nlattr *const tb[]) +{ +struct nft_exthdr *priv =nft_expr_priv (expr); + +if (tb[NFTA_EXTHDR_SREG ] || + tb[NFTA_EXTHDR_DREG ] || + tb[NFTA_EXTHDR_FLAGS ] || + tb[NFTA_EXTHDR_OFFSET ] || + tb[NFTA_EXTHDR_LEN ]) +return -EINVAL ; + +if (!tb[NFTA_EXTHDR_TYPE ]) +return -EINVAL ; + + priv->type =nla_get_u8 (tb[NFTA_EXTHDR_TYPE ]); + priv->op =NFT_EXTHDR_OP_TCPOPT ; + +return 0 ; +} +static int nft_exthdr_ipv4_init (const struct nft_ctx *ctx,const struct nft_expr *expr,const struct nlattr *const tb[])
@@ -523,6 +602,13 @@ static int nft_exthdr_dump_set(struct sk_buff *skb, const struct nft_expr *expr)return nft_exthdr_dump_common (skb, priv); } +static int nft_exthdr_dump_strip (struct sk_buff *skb,const struct nft_expr *expr) +{ +const struct nft_exthdr *priv =nft_expr_priv (expr); + +return nft_exthdr_dump_common (skb, priv); +} +static const struct nft_expr_ops nft_exthdr_ipv6_ops = { .type = &nft_exthdr_type, .size =NFT_EXPR_SIZE (sizeof (struct nft_exthdr )),
@@ -555,6 +641,14 @@ static const struct nft_expr_ops nft_exthdr_tcp_set_ops = { .dump = nft_exthdr_dump_set, }; +static const struct nft_expr_ops nft_exthdr_tcp_strip_ops = { + .type = &nft_exthdr_type, + .size =NFT_EXPR_SIZE (sizeof (struct nft_exthdr )), + .eval = nft_exthdr_tcp_strip_eval, + .init = nft_exthdr_tcp_strip_init, + .dump = nft_exthdr_dump_strip, +}; +static const struct nft_expr_ops nft_exthdr_sctp_ops = { .type = &nft_exthdr_type, .size =NFT_EXPR_SIZE (sizeof (struct nft_exthdr )),
@@ -582,7 +676,7 @@ nft_exthdr_select_ops(const struct nft_ctx *ctx,return &nft_exthdr_tcp_set_ops;if (tb[NFTA_EXTHDR_DREG ])return &nft_exthdr_tcp_ops; -break ; +return &nft_exthdr_tcp_strip_ops;case NFT_EXTHDR_OP_IPV6 :if (tb[NFTA_EXTHDR_DREG ])return &nft_exthdr_ipv6_ops;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 83/183 netfilter: nft_exthdr: Fix non-linear header modification
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Xiao Liang <[email protected]>
[ Upstream commit 28427f368f0e08d504ed06e74bc7cc79d6d06511 ]
Fix skb_ensure_writable() size. Don't use nft_tcp_header_pointer() to make it explicit that pointers point to the packet (not local buffer).
--- net/netfilter/nft_exthdr.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-)
net/netfilter/nft_exthdr.c +8 -12
@@ -245,7 +245,12 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr,if (!tcph) goto err; +if (skb_ensure_writable (pkt->skb,nft_thoff (pkt) + tcphdr_len)) + goto err; + + tcph = (struct tcphdr *)(pkt->skb->data +nft_thoff (pkt)); opt = (u8 *)tcph; +for (i =sizeof (*tcph); i < tcphdr_len -1 ; i += optl) {union {__be16 v16;
@@ -260,15 +265,6 @@ static void nft_exthdr_tcp_set_eval(const struct nft_expr *expr,if (i + optl > tcphdr_len || priv->len + priv->offset > optl) goto err; -if (skb_ensure_writable (pkt->skb, -nft_thoff (pkt) + i + priv->len)) - goto err; - - tcph =nft_tcp_header_pointer (pkt,sizeof (buff), buff, - &tcphdr_len); -if (!tcph) - goto err; - offset = i + priv->offset;switch (priv->len) {
@@ -332,9 +328,9 @@ static void nft_exthdr_tcp_strip_eval(const struct nft_expr *expr,if (skb_ensure_writable (pkt->skb,nft_thoff (pkt) + tcphdr_len)) goto drop; - opt = (u8 *)nft_tcp_header_pointer (pkt,sizeof (buff), buff, &tcphdr_len); -if (!opt) - goto err; + tcph = (struct tcphdr *)(pkt->skb->data +nft_thoff (pkt)); + opt = (u8 *)tcph; +for (i =sizeof (*tcph); i < tcphdr_len -1 ; i += optl) {unsigned int j;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 84/183 ata: libata: Rename link flag ATA_LFLAG_NO_DB_DELAY
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Menzel <[email protected]>
[ Upstream commit b9ba367c513dbc165dd6c01266a59db4be2a3564 ]
Rename the link flag ATA_LFLAG_NO_DB_DELAY to ATA_LFLAG_NO_DEBOUNCE_DELAY. The new name is longer, but clearer.
Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller")
--- drivers/ata/ahci_brcm.c | 2 +- drivers/ata/libata-sata.c | 2 +- include/linux/libata.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
drivers/ata/ahci_brcm.c +1 -1
@@ -333,7 +333,7 @@ static struct ata_port_operations ahci_brcm_platform_ops = {static const struct ata_port_info ahci_brcm_port_info = { .flags =AHCI_FLAG_COMMON |ATA_FLAG_NO_DIPM , - .link_flags =ATA_LFLAG_NO_DB_DELAY , + .link_flags =ATA_LFLAG_NO_DEBOUNCE_DELAY , .pio_mask =ATA_PIO4 , .udma_mask =ATA_UDMA6 , .port_ops = &ahci_brcm_platform_ops,
drivers/ata/libata-sata.c +1 -1
@@ -317,7 +317,7 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params,* immediately after resuming. Delay 200ms before * debouncing. */ -if (!(link->flags &ATA_LFLAG_NO_DB_DELAY )) +if (!(link->flags &ATA_LFLAG_NO_DEBOUNCE_DELAY ))ata_msleep (link->ap,200 );/* is SControl restored correctly? */
include/linux/libata.h +1 -1
@@ -191,7 +191,7 @@ enum {ATA_LFLAG_NO_LPM = (1 <<8 ),/* disable LPM on this link */ ATA_LFLAG_RST_ONCE = (1 <<9 ),/* limit recovery to one reset */ ATA_LFLAG_CHANGED = (1 <<10 ),/* LPM state changed on this link */ -ATA_LFLAG_NO_DB_DELAY = (1 <<11 ),/* no debounce delay on link resume */ +ATA_LFLAG_NO_DEBOUNCE_DELAY = (1 <<11 ),/* no debounce delay on link resume */ /* struct ata_port flags */ ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 85/183 ata: ahci: Add support for AMD A85 FCH (Hudson D4)
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Paul Menzel <[email protected]>
[ Upstream commit a17ab7aba5df4135ef77d7f6d7105e1ea414936f ]
Add support for the AMD A85 FCH (Hudson D4) AHCI adapter.
Since this adapter does not require the default 200 ms debounce delay in sata_link_resume(), create a new board board_ahci_no_debounce_delay with the link flag ATA_LFLAG_NO_DEBOUNCE_DELAY, and, for now, configure the AMD A85 FCH (Hudson D4) to use it. On the ASUS F2A85-M PRO it reduces the Linux kernel boot time by the expected 200 ms from 787 ms to 585 ms.
Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller")
--- drivers/ata/ahci.c | 9 +++++++++ 1 file changed, 9 insertions(+)
drivers/ata/ahci.c +9 -0
@@ -51,6 +51,7 @@ enum board_ids { board_ahci, board_ahci_ign_iferr, board_ahci_mobile, + board_ahci_no_debounce_delay, board_ahci_nomsi, board_ahci_noncq, board_ahci_nosntf,
@@ -142,6 +143,13 @@ static const struct ata_port_info ahci_port_info[] = { .udma_mask = ATA_UDMA6, .port_ops = &ahci_ops, }, + [board_ahci_no_debounce_delay] = { + .flags = AHCI_FLAG_COMMON, + .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }, [board_ahci_nomsi] = { AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), .flags = AHCI_FLAG_COMMON,
@@ -442,6 +450,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { board_ahci_al },/* AMD */ { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ + { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */ /* AMD is using RAID class only for ahci controllers */
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 86/183 ata: ahci: Rename board_ahci_mobile
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Mario Limonciello <[email protected]>
[ Upstream commit 099849af27f74981c7e660dd93ff6a987307c1f2 ]
This board definition was originally created for mobile devices to designate default link power managmeent policy to influence runtime power consumption.
As this is interesting for more than just mobile designs, rename the board to board_ahci_low_power to make it clear it is about default policy.
Stable-dep-of: 2a2df98ec592 ("ata: ahci: Add Elkhart Lake AHCI controller")
--- drivers/ata/ahci.c | 96 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 48 deletions(-)
drivers/ata/ahci.c +48 -48
@@ -50,7 +50,7 @@ enum board_ids {/* board IDs by feature in alphabetical order */ board_ahci, board_ahci_ign_iferr, - board_ahci_mobile, + board_ahci_low_power, board_ahci_no_debounce_delay, board_ahci_nomsi, board_ahci_noncq,
@@ -136,7 +136,7 @@ static const struct ata_port_info ahci_port_info[] = { .udma_mask = ATA_UDMA6, .port_ops = &ahci_ops, }, - [board_ahci_mobile] = { + [board_ahci_low_power] = { AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE), .flags = AHCI_FLAG_COMMON, .pio_mask = ATA_PIO4,
@@ -276,13 +276,13 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ - { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */ - { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */ - { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */ - { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */ - { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */ { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ - { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */ + { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */ { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
@@ -292,9 +292,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ - { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */ + { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */ { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ - { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */ + { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */ { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */ { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
@@ -317,9 +317,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */ { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */ { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ - { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */ + { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */ { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ - { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */ + { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */ { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
@@ -328,29 +328,29 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ - { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */ + { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */ { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ - { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */ + { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */ { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ - { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */ + { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */ { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ - { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */ + { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */ { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ - { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */ + { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */ { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ - { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */ - { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */ - { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */ + { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */ + { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */ + { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */ + { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */ + { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */ { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
@@ -382,26 +382,26 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ - { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */ - { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */ + { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */ + { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */ { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ - { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */ + { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */ { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ - { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */ + { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */ { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ - { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */ + { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */ { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ - { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */ - { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */ - { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */ - { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */ + { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */ + { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */ + { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */ + { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */ { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ - { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */ + { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */ { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ - { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */ + { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */ { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
@@ -418,13 +418,13 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */ { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */ { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */ - { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */ - { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */ - { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */ - { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */ - { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */ - { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_mobile }, /* Comet Lake PCH-U AHCI */ - { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_mobile }, /* Comet Lake PCH RAID */ + { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */ + { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */ + { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */ + { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */ + { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ + { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ + { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID *//* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
@@ -452,7 +452,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */ { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ - { PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */ + { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine *//* AMD is using RAID class only for ahci controllers */ { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 87/183 ata: ahci: Add Elkhart Lake AHCI controller
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Werner Fischer <[email protected]>
[ Upstream commit 2a2df98ec592667927b5c1351afa6493ea125c9f ]
Elkhart Lake is the successor of Apollo Lake and Gemini Lake. These CPUs and their PCHs are used in mobile and embedded environments.
With this patch I suggest that Elkhart Lake SATA controllers [1] should use the default LPM policy for mobile chipsets.
The disadvantage of missing hot-plug support with this setting should not be an issue, as those CPUs are used in embedded environments and not in servers with hot-plug backplanes.
We discovered that the Elkhart Lake SATA controllers have been missing in ahci.c after a customer reported the throttling of his SATA SSD after a short period of higher I/O. We determined the high temperature of the SSD controller in idle mode as the root cause for that.
Depending on the used SSD, we have seen up to 1.8 Watt lower system idle power usage and up to 30°C lower SSD controller temperatures in our tests, when we set med_power_with_dipm manually. I have provided a table showing seven different SATA SSDs from ATP, Intel/Solidigm and Samsung [2].
Intel lists a total of 3 SATA controller IDs (4B60, 4B62, 4B63) in [1] for those mobile PCHs.
This commit just adds 0x4b63 as I do not have test systems with 0x4b60 and 0x4b62 SATA controllers.
I have tested this patch with a system which uses 0x4b63 as SATA controller.
[1] https://sata-io.org/product/8803
[2] https://www.thomas-krenn.com/en/wiki/SATA_Link_Power_Management#Example_LES_v4
--- drivers/ata/ahci.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/ata/ahci.c +2 -0
@@ -425,6 +425,8 @@ static const struct pci_device_id ahci_pci_tbl[] = { { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ +/* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */ + { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI *//* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 88/183 scsi: qla2xxx: Select qpair depending on which CPU post_cmd() gets called
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Shreyas Deodhar <[email protected]>
[ Upstream commit 1d201c81d4cc6840735bbcc99e6031503e5cf3b8 ]
In current I/O path, Tx and Rx may not be processed on same CPU. This may lead to thrashing and optimum performance may not be achieved.
Pick qpair such that Tx and Rx are processed on same CPU.
Stable-dep-of: 59f10a05b5c7 ("scsi: qla2xxx: Use raw_smp_processor_id() instead of smp_processor_id()")
--- drivers/scsi/qla2xxx/qla_def.h | 2 ++ drivers/scsi/qla2xxx/qla_init.c | 2 -- drivers/scsi/qla2xxx/qla_inline.h | 55 +++++++++++++++++++++++++++++++ drivers/scsi/qla2xxx/qla_isr.c | 3 +- drivers/scsi/qla2xxx/qla_nvme.c | 4 +++ drivers/scsi/qla2xxx/qla_os.c | 6 ++++ 6 files changed, 69 insertions(+), 3 deletions(-)
drivers/scsi/qla2xxx/qla_def.h +2 -0
@@ -3461,6 +3461,7 @@ struct qla_msix_entry {int have_irq;int in_use;uint32_t vector; +uint32_t vector_base0;uint16_t entry;char name[30 ];void *handle;
@@ -4119,6 +4120,7 @@ struct qla_hw_data {struct req_que **req_q_map;struct rsp_que **rsp_q_map;struct qla_qpair **queue_pair_map; +struct qla_qpair **qp_cpu_map;unsigned long req_qid_map[(QLA_MAX_QUEUES /8 ) /sizeof (unsigned long )];unsigned long rsp_qid_map[(QLA_MAX_QUEUES /8 ) /sizeof (unsigned long )]; unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
drivers/scsi/qla2xxx/qla_init.c +0 -2
@@ -9779,8 +9779,6 @@ struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, qpair->req = ha->req_q_map[req_id]; qpair->rsp->req = qpair->req; qpair->rsp->qpair = qpair; -/* init qpair to this cpu. Will adjust at run time. */ -qla_cpu_update (qpair,raw_smp_processor_id ());if (IS_T10_PI_CAPABLE (ha) && ql2xenabledif) {if (ha->fw_attributes &BIT_4 )
drivers/scsi/qla2xxx/qla_inline.h +55 -0
58 lines not on this page · raw message
drivers/scsi/qla2xxx/qla_isr.c +2 -1
@@ -3782,7 +3782,6 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha,if (rsp->qpair->cpuid !=smp_processor_id () || !rsp->qpair->rcv_intr) { rsp->qpair->rcv_intr =1 ; -qla_cpu_update (rsp->qpair,smp_processor_id ()); }#define __update_rsp_in (_update, _is_shadow_hba, _rsp, _rsp_in) \
@@ -4396,6 +4395,7 @@ qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)for (i =0 ; i < ha->msix_count; i++) { qentry = &ha->msix_entries[i]; qentry->vector =pci_irq_vector (ha->pdev, i); + qentry->vector_base0 = i; qentry->entry = i; qentry->have_irq =0 ; qentry->in_use =0 ;
@@ -4623,5 +4623,6 @@ int qla25xx_request_irq(struct qla_hw_data *ha, struct qla_qpair *qpair, } msix->have_irq =1 ; msix->handle = qpair; +qla_mapq_init_qp_cpu_map (ha, msix, qpair);return ret; }
drivers/scsi/qla2xxx/qla_nvme.c +4 -0
@@ -598,6 +598,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport,fc_port_t *fcport;struct srb_iocb *nvme;struct scsi_qla_host *vha; +struct qla_hw_data *ha;int rval;srb_t *sp;struct qla_qpair *qpair = hw_queue_handle;
@@ -618,6 +619,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport,return -ENODEV ; vha = fcport->vha; + ha = vha->hw;if (test_bit (ABORT_ISP_ACTIVE , &vha->dpc_flags))return -EBUSY ;
@@ -632,6 +634,8 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport,if (fcport->nvme_flag &NVME_FLAG_RESETTING )return -EBUSY ; + qpair =qla_mapq_nvme_select_qpair (ha, qpair); +/* Alloc SRB structure */ sp =qla2xxx_get_qpair_sp (vha, qpair, fcport,GFP_ATOMIC );if (!sp)
drivers/scsi/qla2xxx/qla_os.c +6 -0
@@ -467,6 +467,11 @@ static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, "Unable to allocate memory for queue pair ptrs.\n"); goto fail_qpair_map; } +if (qla_mapq_alloc_qp_cpu_map (ha) !=0 ) { +kfree (ha->queue_pair_map); + ha->queue_pair_map =NULL ; + goto fail_qpair_map; + } }/*
@@ -541,6 +546,7 @@ static void qla2x00_free_queues(struct qla_hw_data *ha) ha->base_qpair =NULL ; } +qla_mapq_free_qp_cpu_map (ha);spin_lock_irqsave (&ha->hardware_lock, flags);for (cnt =0 ; cnt < ha->max_req_queues; cnt++) {if (!test_bit (cnt, ha->req_qid_map))
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 89/183 scsi: qla2xxx: Use raw_smp_processor_id() instead of smp_processor_id()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Nilesh Javali <[email protected]>
[ Upstream commit 59f10a05b5c7b675256a66e3161741239889ff80 ]
The following call trace was observed:
localhost kernel: nvme nvme0: NVME-FC{0}: controller connect complete
localhost kernel: BUG: using smp_processor_id() in preemptible [00000000] code: kworker/u129:4/75092
localhost kernel: nvme nvme0: NVME-FC{0}: new ctrl: NQN "nqn.1992-08.com.netapp:sn.b42d198afb4d11ecad6d00a098d6abfa:subsystem.PR_Channel2022_RH84_subsystem_291" localhost kernel: caller is qla_nvme_post_cmd+0x216/0x1380 [qla2xxx]
localhost kernel: CPU: 6 PID: 75092 Comm: kworker/u129:4 Kdump: loaded Tainted: G B W OE --------- --- 5.14.0-70.22.1.el9_0.x86_64+debug #1
localhost kernel: Hardware name: HPE ProLiant XL420 Gen10/ProLiant XL420 Gen10, BIOS U39 01/13/2022
localhost kernel: Workqueue: nvme-wq nvme_async_event_work [nvme_core]
localhost kernel: Call Trace:
localhost kernel: dump_stack_lvl+0x57/0x7d
localhost kernel: check_preemption_disabled+0xc8/0xd0
localhost kernel: qla_nvme_post_cmd+0x216/0x1380 [qla2xxx]
Use raw_smp_processor_id() instead of smp_processor_id().
Also use queue_work() across the driver instead of queue_work_on() thus avoiding usage of smp_processor_id() when CONFIG_DEBUG_PREEMPT is enabled.
--- drivers/scsi/qla2xxx/qla_inline.h | 2 +- drivers/scsi/qla2xxx/qla_isr.c | 6 +++--- drivers/scsi/qla2xxx/qla_target.c | 3 +-- drivers/scsi/qla2xxx/tcm_qla2xxx.c | 4 ++-- 4 files changed, 7 insertions(+), 8 deletions(-)
drivers/scsi/qla2xxx/qla_inline.h +1 -1
@@ -577,7 +577,7 @@ fcport_is_bigger(fc_port_t *fcport)static inline struct qla_qpair *qla_mapq_nvme_select_qpair (struct qla_hw_data *ha,struct qla_qpair *qpair) { -int cpuid =smp_processor_id (); +int cpuid =raw_smp_processor_id ();if (qpair->cpuid != cpuid && ha->qp_cpu_map[cpuid]) {
drivers/scsi/qla2xxx/qla_isr.c +3 -3
@@ -3780,7 +3780,7 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha,if (!ha->flags.fw_started)return ; -if (rsp->qpair->cpuid !=smp_processor_id () || !rsp->qpair->rcv_intr) { +if (rsp->qpair->cpuid !=raw_smp_processor_id () || !rsp->qpair->rcv_intr) { rsp->qpair->rcv_intr =1 ; }
@@ -4276,7 +4276,7 @@ qla2xxx_msix_rsp_q(int irq, void *dev_id) } ha = qpair->hw; -queue_work_on (smp_processor_id (), ha->wq, &qpair->q_work); +queue_work (ha->wq, &qpair->q_work);return IRQ_HANDLED ; }
@@ -4302,7 +4302,7 @@ qla2xxx_msix_rsp_q_hs(int irq, void *dev_id)wrt_reg_dword (®->hccr,HCCRX_CLR_RISC_INT );spin_unlock_irqrestore (&ha->hardware_lock, flags); -queue_work_on (smp_processor_id (), ha->wq, &qpair->q_work); +queue_work (ha->wq, &qpair->q_work);return IRQ_HANDLED ; }
drivers/scsi/qla2xxx/qla_target.c +1 -2
@@ -4459,8 +4459,7 @@ static int qlt_handle_cmd_for_atio(struct scsi_qla_host *vha,queue_work_on (cmd->se_cmd.cpuid, qla_tgt_wq, &cmd->work); }else if (ha->msix_count) {if (cmd->atio.u.isp24.fcp_cmnd.rddata) -queue_work_on (smp_processor_id (), qla_tgt_wq, - &cmd->work); +queue_work (qla_tgt_wq, &cmd->work);else queue_work_on (cmd->se_cmd.cpuid, qla_tgt_wq, &cmd->work);
drivers/scsi/qla2xxx/tcm_qla2xxx.c +2 -2
@@ -310,7 +310,7 @@ static void tcm_qla2xxx_free_cmd(struct qla_tgt_cmd *cmd) cmd->trc_flags |=TRC_CMD_DONE ;INIT_WORK (&cmd->work, tcm_qla2xxx_complete_free); -queue_work_on (smp_processor_id (), tcm_qla2xxx_free_wq, &cmd->work); +queue_work (tcm_qla2xxx_free_wq, &cmd->work); }/*
@@ -557,7 +557,7 @@ static void tcm_qla2xxx_handle_data(struct qla_tgt_cmd *cmd) cmd->trc_flags |=TRC_DATA_IN ; cmd->cmd_in_wq =1 ;INIT_WORK (&cmd->work, tcm_qla2xxx_handle_data_work); -queue_work_on (smp_processor_id (), tcm_qla2xxx_free_wq, &cmd->work); +queue_work (tcm_qla2xxx_free_wq, &cmd->work); }static int tcm_qla2xxx_chk_dif_tags (uint32_t tag)
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 90/183 btrfs: reset destination buffer when read_extent_buffer() gets invalid range
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Qu Wenruo <[email protected]>
[ Upstream commit 74ee79142c0a344d4eae2eb7012ebc4e82254109 ]
Commit f98b6215d7d1 ("btrfs: extent_io: do extra check for extent buffer read write functions") changed how we handle invalid extent buffer range for read_extent_buffer().
Previously if the range is invalid we just set the destination to zero, but after the patch we do nothing and error out.
This can lead to smatch static checker errors like:
fs/btrfs/print-tree.c:186 print_uuid_item() error: uninitialized symbol 'subvol_id'. fs/btrfs/tests/extent-io-tests.c:338 check_eb_bitmap() error: uninitialized symbol 'has'. fs/btrfs/tests/extent-io-tests.c:353 check_eb_bitmap() error: uninitialized symbol 'has'. fs/btrfs/uuid-tree.c:203 btrfs_uuid_tree_remove() error: uninitialized symbol 'read_subid'. fs/btrfs/uuid-tree.c:353 btrfs_uuid_tree_iterate() error: uninitialized symbol 'subid_le'. fs/btrfs/uuid-tree.c:72 btrfs_uuid_tree_lookup() error: uninitialized symbol 'data'. fs/btrfs/volumes.c:7415 btrfs_dev_stats_value() error: uninitialized symbol 'val'.
Fix those warnings by reverting back to the old memset() behavior. By this we keep the static checker happy and would still make a lot of noise when such invalid ranges are passed in.
--- fs/btrfs/extent_io.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
fs/btrfs/extent_io.c +7 -1
@@ -6722,8 +6722,14 @@ void read_extent_buffer(const struct extent_buffer *eb, void *dstv,char *dst = (char *)dstv;unsigned long i =get_eb_page_index (start); -if (check_eb_range (eb, start, len)) +if (check_eb_range (eb, start, len)) { +/* +* Invalid range hit, reset the memory, so callers won't get +* some random garbage for their uninitialzed memory. +*/ +memset (dstv,0 , len);return ; + } offset =get_eb_offset_in_page (eb, start);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 91/183 MIPS: Alchemy: only build mmc support helpers if au1xmmc is enabled
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christoph Hellwig <[email protected]>
[ Upstream commit ef8f8f04a0b25e8f294b24350e8463a8d6a9ba0b ]
While commit d4a5c59a955b ("mmc: au1xmmc: force non-modular build and remove symbol_get usage") to be built in, it can still build a kernel without MMC support and thuse no mmc_detect_change symbol at all.
Add ifdefs to build the mmc support code in the alchemy arch code conditional on mmc support.
--- arch/mips/alchemy/devboards/db1000.c | 4 ++++ arch/mips/alchemy/devboards/db1200.c | 6 ++++++ arch/mips/alchemy/devboards/db1300.c | 4 ++++ 3 files changed, 14 insertions(+)
arch/mips/alchemy/devboards/db1000.c +4 -0
@@ -164,6 +164,7 @@ static struct platform_device db1x00_audio_dev = {/******************************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1100_mmc_cd (int irq,void *ptr) {mmc_detect_change (ptr,msecs_to_jiffies (500 ));
@@ -369,6 +370,7 @@ static struct platform_device db1100_mmc1_dev = { .num_resources = ARRAY_SIZE(au1100_mmc1_res), .resource = au1100_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /******************************************************************************/
@@ -432,8 +434,10 @@ static struct platform_device *db1x00_devs[] = {static struct platform_device *db1100_devs[] = { &au1100_lcd_device, +#ifdef CONFIG_MMC_AU1X &db1100_mmc0_dev, &db1100_mmc1_dev, +#endif };int __init db1000_dev_setup (void )
arch/mips/alchemy/devboards/db1200.c +6 -0
@@ -326,6 +326,7 @@ static struct platform_device db1200_ide_dev = {/**********************************************************************/ +#ifdef CONFIG_MMC_AU1X /* SD carddetects: they're supposed to be edge-triggered, but ack * doesn't seem to work (CPLD Rev 2). Instead, the screaming one * is disabled and its counterpart enabled. The 200ms timeout is
@@ -584,6 +585,7 @@ static struct platform_device pb1200_mmc1_dev = { .num_resources = ARRAY_SIZE(au1200_mmc1_res), .resource = au1200_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/
@@ -751,7 +753,9 @@ static struct platform_device db1200_audiodma_dev = {static struct platform_device *db1200_devs[]__initdata = {NULL ,/* PSC0, selected by S6.8 */ &db1200_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1200_mmc0_dev, +#endif &au1200_lcd_dev, &db1200_eth_dev, &db1200_nand_dev,
@@ -762,7 +766,9 @@ static struct platform_device *db1200_devs[] __initdata = { };static struct platform_device *pb1200_devs[]__initdata = { +#ifdef CONFIG_MMC_AU1X &pb1200_mmc1_dev, +#endif };/* Some peripheral base addresses differ on the PB1200 */
arch/mips/alchemy/devboards/db1300.c +4 -0
@@ -450,6 +450,7 @@ static struct platform_device db1300_ide_dev = {/**********************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1300_mmc_cd (int irq,void *ptr) {disable_irq_nosync (irq);
@@ -632,6 +633,7 @@ static struct platform_device db1300_sd0_dev = { .resource = au1300_sd0_res, .num_resources = ARRAY_SIZE(au1300_sd0_res), }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/
@@ -776,8 +778,10 @@ static struct platform_device *db1300_dev[] __initdata = { &db1300_5waysw_dev, &db1300_nand_dev, &db1300_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1300_sd0_dev, &db1300_sd1_dev, +#endif &db1300_lcd_dev, &db1300_ac97_dev, &db1300_i2s_dev,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 92/183 drm/bridge: ti-sn65dsi83: Do not generate HFP/HBP/HSA and EOT packet
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marek Vasut <[email protected]>
[ Upstream commit f4d324fb5628773907dd90342d18f978bd9a6d09 ]
[ Upstream commit ca161b259cc84fe1f4a2ce4c73c3832cf6f713f1 ]
Do not generate the HS front and back porch gaps, the HSA gap and EOT packet, as per "SN65DSI83 datasheet SLLSEC1I - SEPTEMBER 2012
- REVISED OCTOBER 2020", page 22, these packets are not required. This makes the TI SN65DSI83 bridge work with Samsung DSIM on i.MX8MN.
--- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/gpu/drm/bridge/ti-sn65dsi83.c +3 -1
@@ -272,7 +272,9 @@ static int sn65dsi83_attach(struct drm_bridge *bridge, dsi->lanes = ctx->dsi_lanes; dsi->format =MIPI_DSI_FMT_RGB888 ; - dsi->mode_flags =MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST ; + dsi->mode_flags =MIPI_DSI_MODE_VIDEO |MIPI_DSI_MODE_VIDEO_BURST | +MIPI_DSI_MODE_VIDEO_NO_HFP |MIPI_DSI_MODE_VIDEO_NO_HBP | +MIPI_DSI_MODE_VIDEO_NO_HSA |MIPI_DSI_MODE_NO_EOT_PACKET ; ret =mipi_dsi_attach (dsi);if (ret <0 ) {
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 93/183 bus: ti-sysc: Use fsleep() instead of usleep_range() in sysc_reset()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Julien Panis <[email protected]>
[ Upstream commit d929b2b7464f95ec01e47f560b1e687482ba8929 ]
The am335x-evm started producing boot errors because of subtle timing changes:
Unhandled fault: external abort on non-linefetch (0x1008) at 0xf03c1010
...sysc_reset from sysc_probe+0xf60/0x1514sysc_probe from platform_probe+0x5c/0xbc
...
The fix consists in using the appropriate sleep function in sysc reset. For flexible sleeping, fsleep is recommended. Here, sysc delay parameter can take any value in [0 - 255] us range. As a result, fsleep() should be used, calling udelay() for a sysc delay lower than 10 us.
Message-ID: <[email protected]>
--- drivers/bus/ti-sysc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/bus/ti-sysc.c +1 -2
@@ -2096,8 +2096,7 @@ static int sysc_reset(struct sysc *ddata) }if (ddata->cfg.srst_udelay) -usleep_range (ddata->cfg.srst_udelay, - ddata->cfg.srst_udelay *2 ); +fsleep (ddata->cfg.srst_udelay);if (ddata->post_reset_quirk) ddata->post_reset_quirk (ddata);
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 94/183 bus: ti-sysc: Fix missing AM35xx SoC matching
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Adam Ford <[email protected]>
[ Upstream commit 11729caa520950e17cd81bc43ffc477c46cf791e ]
Commit feaa8baee82a ("bus: ti-sysc: Implement SoC revision handling") created a list of SoC types searching for strings based on names and wildcards which associates the SoC to different families.
The OMAP34xx and OMAP35xx are treated as SOC_3430 while OMAP36xx and OMAP37xx are treated as SOC_3630, but the AM35xx isn't listed.
The AM35xx is mostly an OMAP3430, and a later commit a12315d6d270 ("bus: ti-sysc: Make omap3 gpt12 quirk handling SoC specific") looks for the SOC type and behaves in a certain way if it's SOC_3430.
This caused a regression on the AM3517 causing it to return two errors:
ti-sysc: probe of 48318000.target-module failed with error -16
ti-sysc: probe of 49032000.target-module failed with error -16
Fix this by treating the creating SOC_AM35 and inserting it between the SOC_3430 and SOC_3630. If it is treaed the same way as the SOC_3430 when checking the status of sysc_check_active_timer, the error conditions will disappear.
Message-ID: <[email protected]>
--- drivers/bus/ti-sysc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/bus/ti-sysc.c +4 -2
@@ -38,6 +38,7 @@ enum sysc_soc {SOC_2420 ,SOC_2430 ,SOC_3430 , +SOC_AM35 ,SOC_3630 ,SOC_4430 , SOC_4460,
@@ -1829,7 +1830,7 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)dev_warn (ddata->dev,"%s: timed out %08x !+ %08x\n" , __func__, val, irq_mask); -if (sysc_soc->soc ==SOC_3430 ) { +if (sysc_soc->soc ==SOC_3430 || sysc_soc->soc ==SOC_AM35 ) {/* Clear DSS_SDI_CONTROL */ sysc_write (ddata,0x44 ,0 );
@@ -2972,6 +2973,7 @@ static void ti_sysc_idle(struct work_struct *work)static const struct soc_device_attribute sysc_soc_match[] = {SOC_FLAG ("OMAP242*" ,SOC_2420 ),SOC_FLAG ("OMAP243*" ,SOC_2430 ), +SOC_FLAG ("AM35*" ,SOC_AM35 ),SOC_FLAG ("OMAP3[45]*" ,SOC_3430 ),SOC_FLAG ("OMAP3[67]*" ,SOC_3630 ),SOC_FLAG ("OMAP443*" ,SOC_4430 ),
@@ -3178,7 +3180,7 @@ static int sysc_check_active_timer(struct sysc *ddata)* can be dropped if we stop supporting old beagleboard revisions * A to B4 at some point. */ -if (sysc_soc->soc ==SOC_3430 ) +if (sysc_soc->soc ==SOC_3430 || sysc_soc->soc ==SOC_AM35 ) error = -ENXIO ;else error = -EBUSY ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 95/183 clk: tegra: fix error return case for recalc_rate
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Timo Alho <[email protected]>
[ Upstream commit a47b44fbb13f5e7a981b4515dcddc93a321ae89c ]
tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0."
--- drivers/clk/tegra/clk-bpmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/tegra/clk-bpmp.c +1 -1
@@ -159,7 +159,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw, err =tegra_bpmp_clk_transfer (clk->bpmp, &msg);if (err <0 ) -return err; +return 0 ;return response.rate; }
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 96/183 treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 1)
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Thomas Gleixner <[email protected]>
[ Upstream commit 0fdebc5ec2ca492d69df2d93a6a7abade4941aae ]
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Stable-dep-of: 6469b2feade8 ("ARM: dts: ti: omap: Fix bandgap thermal cells addressing for omap3/4")
--- arch/arm/boot/dts/am33xx.dtsi | 5 +---- arch/arm/boot/dts/am3517.dtsi | 5 +---- arch/arm/boot/dts/am4372.dtsi | 5 +---- arch/arm/boot/dts/artpec6-devboard.dts | 9 ++------- arch/arm/boot/dts/dm814x.dtsi | 6 +----- arch/arm/boot/dts/dm816x.dtsi | 6 +----- arch/arm/boot/dts/dra62x.dtsi | 6 +----- arch/arm/boot/dts/dra7-dspeve-thermal.dtsi | 5 +---- arch/arm/boot/dts/dra7-iva-thermal.dtsi | 5 +---- arch/arm/boot/dts/imx6q-gk802.dts | 9 ++------- arch/arm/boot/dts/omap2.dtsi | 5 +---- arch/arm/boot/dts/omap2420.dtsi | 5 +---- arch/arm/boot/dts/omap2430.dtsi | 5 +---- arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 5 +---- arch/arm/boot/dts/omap3.dtsi | 5 +---- arch/arm/boot/dts/omap34xx.dtsi | 5 +---- arch/arm/boot/dts/omap36xx.dtsi | 5 +---- arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 5 +---- arch/arm/boot/dts/omap443x.dtsi | 5 +---- arch/arm/boot/dts/omap4460.dtsi | 5 +---- arch/arm/boot/dts/omap5-core-thermal.dtsi | 5 +---- arch/arm/boot/dts/omap5-gpu-thermal.dtsi | 5 +---- arch/arm/boot/dts/orion5x-lacie-d2-network.dts | 5 +---- .../arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts | 9 ++------- arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts | 5 +---- arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 9 ++------- arch/arm/boot/dts/orion5x-mv88f5182.dtsi | 9 ++------- arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 9 ++------- arch/arm/boot/dts/orion5x-rd88f5182-nas.dts | 9 ++------- arch/arm/boot/dts/orion5x.dtsi | 9 ++------- arch/arm/include/asm/hardware/cache-aurora-l2.h | 5 +---- arch/arm/include/asm/hardware/cache-feroceon-l2.h | 6 +----- arch/arm/include/asm/hardware/cache-tauros2.h | 5 +---- arch/arm/mach-davinci/board-da830-evm.c | 6 ++---- arch/arm/mach-davinci/board-da850-evm.c | 6 ++---- arch/arm/mach-davinci/board-dm355-evm.c | 6 ++---- arch/arm/mach-davinci/board-dm355-leopard.c | 5 +---- arch/arm/mach-davinci/board-dm644x-evm.c | 6 ++---- arch/arm/mach-davinci/board-dm646x-evm.c | 7 +------ arch/arm/mach-davinci/board-mityomapl138.c | 5 +---- arch/arm/mach-davinci/board-neuros-osd2.c | 5 +---- arch/arm/mach-davinci/board-omapl138-hawk.c | 5 +---- arch/arm/mach-davinci/common.c | 6 ++---- arch/arm/mach-davinci/cpuidle.h | 5 +---- arch/arm/mach-davinci/da830.c | 6 ++---- arch/arm/mach-davinci/da850.c | 6 ++---- arch/arm/mach-davinci/dm355.c | 6 ++---- arch/arm/mach-davinci/dm644x.c | 6 ++---- arch/arm/mach-davinci/dm646x.c | 6 ++---- arch/arm/mach-davinci/include/mach/common.h | 6 ++---- arch/arm/mach-davinci/include/mach/cputype.h | 6 ++---- arch/arm/mach-davinci/include/mach/da8xx.h | 6 ++---- arch/arm/mach-davinci/include/mach/hardware.h | 6 ++---- arch/arm/mach-davinci/include/mach/serial.h | 6 ++---- arch/arm/mach-davinci/mux.c | 6 ++---- arch/arm/mach-davinci/mux.h | 6 ++---- arch/arm/mach-davinci/pm_domain.c | 5 +---- arch/arm/mach-dove/bridge-regs.h | 9 ++------- arch/arm/mach-dove/cm-a510.c | 5 +---- arch/arm/mach-dove/common.c | 5 +---- arch/arm/mach-dove/common.h | 5 +---- arch/arm/mach-dove/dove-db-setup.c | 5 +---- arch/arm/mach-dove/dove.h | 9 ++------- arch/arm/mach-dove/irq.c | 5 +---- arch/arm/mach-dove/irqs.h | 9 ++------- arch/arm/mach-dove/mpp.c | 5 +---- arch/arm/mach-dove/pcie.c | 5 +---- arch/arm/mach-dove/pm.h | 6 +----- arch/arm/mach-lpc18xx/board-dt.c | 5 +---- arch/arm/mach-lpc32xx/pm.c | 6 ++---- arch/arm/mach-lpc32xx/suspend.S | 6 ++---- arch/arm/mach-mv78xx0/bridge-regs.h | 6 +----- arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 5 +---- arch/arm/mach-mv78xx0/common.c | 5 +---- arch/arm/mach-mv78xx0/common.h | 5 +---- arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 5 +---- arch/arm/mach-mv78xx0/irq.c | 5 +---- arch/arm/mach-mv78xx0/irqs.h | 9 ++------- arch/arm/mach-mv78xx0/mpp.c | 5 +---- arch/arm/mach-mv78xx0/mpp.h | 6 +----- arch/arm/mach-mv78xx0/mv78xx0.h | 5 +---- arch/arm/mach-mv78xx0/pcie.c | 5 +---- arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 5 +---- arch/arm/mach-mvebu/armada-370-xp.h | 5 +---- arch/arm/mach-mvebu/board-v7.c | 5 +---- arch/arm/mach-mvebu/coherency.c | 5 +---- arch/arm/mach-mvebu/coherency.h | 6 +----- arch/arm/mach-mvebu/coherency_ll.S | 5 +---- arch/arm/mach-mvebu/common.h | 5 +---- arch/arm/mach-mvebu/cpu-reset.c | 5 +---- arch/arm/mach-mvebu/dove.c | 5 +---- arch/arm/mach-mvebu/headsmp-a9.S | 5 +---- arch/arm/mach-mvebu/headsmp.S | 5 +---- arch/arm/mach-mvebu/kirkwood.c | 5 +---- arch/arm/mach-mvebu/kirkwood.h | 5 +---- arch/arm/mach-mvebu/mvebu-soc-id.c | 5 +---- arch/arm/mach-mvebu/mvebu-soc-id.h | 5 +---- arch/arm/mach-mvebu/platsmp-a9.c | 5 +---- arch/arm/mach-mvebu/platsmp.c | 5 +---- arch/arm/mach-mvebu/pm-board.c | 5 +---- arch/arm/mach-mvebu/pm.c | 5 +---- arch/arm/mach-mvebu/pmsu.c | 5 +---- arch/arm/mach-mvebu/pmsu.h | 5 +---- arch/arm/mach-mvebu/pmsu_ll.S | 5 +---- arch/arm/mach-mvebu/system-controller.c | 5 +---- arch/arm/mach-omap1/include/mach/mtd-xip.h | 6 ++---- arch/arm/mach-omap1/pm_bus.c | 6 +----- arch/arm/mach-omap2/prcm43xx.h | 5 +---- arch/arm/mach-omap2/vc.c | 6 +----- arch/arm/mach-orion5x/board-d2net.c | 5 +---- arch/arm/mach-orion5x/board-dt.c | 5 +---- arch/arm/mach-orion5x/board-rd88f5182.c | 5 +---- arch/arm/mach-orion5x/bridge-regs.h | 9 ++------- arch/arm/mach-orion5x/common.c | 5 +---- arch/arm/mach-orion5x/db88f5281-setup.c | 5 +---- arch/arm/mach-orion5x/irq.c | 5 +---- arch/arm/mach-orion5x/irqs.h | 5 +---- arch/arm/mach-orion5x/kurobox_pro-setup.c | 5 +---- arch/arm/mach-orion5x/ls_hgl-setup.c | 5 +---- arch/arm/mach-orion5x/mpp.c | 5 +---- arch/arm/mach-orion5x/net2big-setup.c | 6 +----- arch/arm/mach-orion5x/orion5x.h | 5 +---- arch/arm/mach-orion5x/pci.c | 5 +---- arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 5 +---- arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 5 +---- arch/arm/mach-orion5x/rd88f5182-setup.c | 5 +---- arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 5 +---- arch/arm/mach-orion5x/ts78xx-setup.c | 5 +---- arch/arm/mach-orion5x/wnr854t-setup.c | 9 ++------- arch/arm/mach-orion5x/wrt350n-v2-setup.c | 9 ++------- arch/arm/mach-pxa/eseries.c | 7 +------ arch/arm/mach-pxa/standby.S | 6 ++---- arch/arm/mach-spear/generic.h | 5 +---- arch/arm/mach-spear/include/mach/misc_regs.h | 5 +---- arch/arm/mach-spear/include/mach/spear.h | 5 +---- arch/arm/mach-spear/pl080.c | 5 +---- arch/arm/mach-spear/pl080.h | 5 +---- arch/arm/mach-spear/restart.c | 5 +---- arch/arm/mach-spear/spear1310.c | 5 +---- arch/arm/mach-spear/spear1340.c | 5 +---- arch/arm/mach-spear/spear13xx.c | 5 +---- arch/arm/mach-spear/spear300.c | 5 +---- arch/arm/mach-spear/spear310.c | 5 +---- arch/arm/mach-spear/spear320.c | 5 +---- arch/arm/mach-spear/spear3xx.c | 5 +---- arch/arm/mach-spear/spear6xx.c | 5 +---- arch/arm/mach-spear/time.c | 5 +---- arch/arm/mm/cache-feroceon-l2.c | 5 +---- arch/arm/mm/cache-tauros2.c | 5 +---- 149 files changed, 185 insertions(+), 656 deletions(-)
arch/arm/boot/dts/am33xx.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM33XX SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/am3517.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for am3517 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap3.dtsi"
arch/arm/boot/dts/am4372.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for AM4372 SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/artpec6-devboard.dts +2 -7
@@ -1,10 +1,5 @@ -/* - * Axis ARTPEC-6 development board. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Axis ARTPEC-6 development board. /dts-v1/; #include "artpec6.dtsi"
arch/arm/boot/dts/dm814x.dtsi +1 -5
@@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/clock/dm814.h>
arch/arm/boot/dts/dm816x.dtsi +1 -5
@@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include <dt-bindings/bus/ti-sysc.h> #include <dt-bindings/clock/dm816.h>
arch/arm/boot/dts/dra62x.dtsi +1 -5
@@ -1,8 +1,4 @@ -/* - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only #include "dm814x.dtsi"
arch/arm/boot/dts/dra7-dspeve-thermal.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC DSPEVE thermal * * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/dra7-iva-thermal.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for DRA7x SoC IVA thermal * * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/imx6q-gk802.dts +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2013 Philipp Zabel - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013 Philipp Zabel /dts-v1/; #include <dt-bindings/gpio/gpio.h>
arch/arm/boot/dts/omap2.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP2 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/omap2420.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP2420 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap2.dtsi"
arch/arm/boot/dts/omap2430.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP243x SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap2.dtsi"
arch/arm/boot/dts/omap3-cpu-thermal.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC CPU thermal * * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/omap3.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/omap34xx.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP34xx/OMAP35xx SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/omap36xx.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP3 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/bus/ti-sysc.h>
arch/arm/boot/dts/omap4-cpu-thermal.dtsi +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4/5 SoC CPU thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <[email protected]> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/omap443x.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP443x SoC * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap4.dtsi"
arch/arm/boot/dts/omap4460.dtsi +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP4460 SoC * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "omap4.dtsi"
arch/arm/boot/dts/omap5-core-thermal.dtsi +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC CORE thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <[email protected]> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/omap5-gpu-thermal.dtsi +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree Source for OMAP543x SoC GPU thermal * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * Contact: Eduardo Valentin <[email protected]> - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include <dt-bindings/thermal/thermal.h>
arch/arm/boot/dts/orion5x-lacie-d2-network.dts +1 -4
@@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Thomas Petazzoni <[email protected]> * Copyright (C) 2009 Simon Guinot <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/;
arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni <[email protected]> /* * TODO: add Orion USB device port init when kernel.org support is added.
arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts +1 -4
@@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Thomas Petazzoni <[email protected]> * Copyright (C) Sylver Bruneau <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ /dts-v1/;
arch/arm/boot/dts/orion5x-mv88f5181.dtsi +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2016 Jamie Lentin <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin <[email protected]> #include "orion5x.dtsi"
arch/arm/boot/dts/orion5x-mv88f5182.dtsi +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni <[email protected]> #include "orion5x.dtsi"
arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2016 Jamie Lentin <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2016 Jamie Lentin <[email protected]> /dts-v1/;
arch/arm/boot/dts/orion5x-rd88f5182-nas.dts +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2014 Thomas Petazzoni <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2014 Thomas Petazzoni <[email protected]> /dts-v1/;
arch/arm/boot/dts/orion5x.dtsi +2 -7
@@ -1,10 +1,5 @@ -/* - * Copyright (C) 2012 Thomas Petazzoni <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2012 Thomas Petazzoni <[email protected]> #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
arch/arm/include/asm/hardware/cache-aurora-l2.h +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * AURORA shared L2 cache controller support *
@@ -5,10 +6,6 @@* * Yehuda Yitschak <[email protected]> * Gregory CLEMENT <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
arch/arm/include/asm/hardware/cache-feroceon-l2.h +1 -5
@@ -1,13 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/include/asm/hardware/cache-feroceon-l2.h * * Copyright (C) 2008 Marvell Semiconductor -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ extern void __init feroceon_l2_init (int l2_wt_override);extern int __init feroceon_of_init (void ); -
arch/arm/include/asm/hardware/cache-tauros2.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/include/asm/hardware/cache-tauros2.h * * Copyright (C) 2008 Marvell Semiconductor -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define CACHE_TAUROS2_PREFETCH_ON (1 << 0)
arch/arm/mach-davinci/board-da830-evm.c +2 -4
@@ -1,13 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA830/OMAP L137 EVM board * * Author: Mark A. Greer <[email protected]> * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c * -* 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007, 2009 (c) MontaVista Software, Inc. */ #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-davinci/board-da850-evm.c +2 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA850/OMAP-L138 EVM board *
@@ -6,10 +7,7 @@* Derived from: arch/arm/mach-davinci/board-da830-evm.c * Original Copyrights follow: * -* 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007, 2009 (c) MontaVista Software, Inc. */ #include <linux/console.h> #include <linux/delay.h>
arch/arm/mach-davinci/board-dm355-evm.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci EVM board support * * Author: Kevin Hilman, Deep Root Systems, LLC * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. */ #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-davinci/board-dm355-leopard.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * DM355 leopard board support * * Based on board-dm355-evm.c -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-davinci/board-dm644x-evm.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci EVM board support * * Author: Kevin Hilman, MontaVista Software, Inc. <[email protected]> * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. */ #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-davinci/board-dm646x-evm.c +1 -6
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci DM646X EVM board *
@@ -5,11 +6,6 @@* Copyright (C) 2006 Texas Instruments. * * (C) 2007-2008, MontaVista Software, Inc. -* -* This file is licensed under the terms of the GNU General Public License -* version 2. This program is licensed "as is" without any warranty of any -* kind, whether express or implied. -* */ /**************************************************************************
@@ -873,4 +869,3 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") .init_late = davinci_init_late, .dma_zone_size =SZ_128M ,MACHINE_END -
arch/arm/mach-davinci/board-mityomapl138.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Critical Link MityOMAP-L138 SoM * * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com -* -* This file is licensed under the terms of the GNU General Public License -* version 2. This program is licensed "as is" without any warranty of -* any kind, whether express or implied. */ #define pr_fmt (fmt) "MityOMAPL138: " fmt
arch/arm/mach-davinci/board-neuros-osd2.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Neuros Technologies OSD2 board support *
@@ -18,10 +19,6 @@* * For more information please refer to * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/platform_device.h> #include <linux/gpio.h>
arch/arm/mach-davinci/board-omapl138-hawk.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Hawkboard.org based on TI's OMAP-L138 Platform * * Initial code: Syed Mohammed Khasim * * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com -* -* This file is licensed under the terms of the GNU General Public License -* version 2. This program is licensed "as is" without any warranty of -* any kind, whether express or implied. */ #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-davinci/common.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Code commons to all DaVinci SoCs. * * Author: Mark A. Greer <[email protected]> * -* 2009 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2009 (c) MontaVista Software, Inc. */ #include <linux/module.h> #include <linux/io.h>
arch/arm/mach-davinci/cpuidle.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * TI DaVinci cpuidle platform support * * 2009 (C) Texas Instruments, Inc. https://www.ti.com/ -* -* This file is licensed under the terms of the GNU General Public License -* version 2. This program is licensed "as is" without any warranty of any -* kind, whether express or implied. */ #ifndef _MACH_DAVINCI_CPUIDLE_H#define _MACH_DAVINCI_CPUIDLE_H
arch/arm/mach-davinci/da830.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA830/OMAP L137 chip specific setup * * Author: Mark A. Greer <[email protected]> * -* 2009 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2009 (c) MontaVista Software, Inc. */ #include <linux/clk-provider.h> #include <linux/clk/davinci.h>
arch/arm/mach-davinci/da850.c +2 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DA850/OMAP-L138 chip specific setup *
@@ -6,10 +7,7 @@* Derived from: arch/arm/mach-davinci/da830.c * Original Copyrights follow: * -* 2009 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2009 (c) MontaVista Software, Inc. */ #include <linux/clk-provider.h>
arch/arm/mach-davinci/dm355.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci DM355 chip specific setup * * Author: Kevin Hilman, Deep Root Systems, LLC * -* 2007 (c) Deep Root Systems, LLC. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) Deep Root Systems, LLC. */ #include <linux/clk-provider.h>
arch/arm/mach-davinci/dm644x.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci DM644x chip specific setup * * Author: Kevin Hilman, Deep Root Systems, LLC * -* 2007 (c) Deep Root Systems, LLC. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) Deep Root Systems, LLC. */ #include <linux/clk-provider.h>
arch/arm/mach-davinci/dm646x.c +2 -4
@@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * TI DaVinci DM646x chip specific setup * * Author: Kevin Hilman, Deep Root Systems, LLC * -* 2007 (c) Deep Root Systems, LLC. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) Deep Root Systems, LLC. */ #include <linux/clk-provider.h>
arch/arm/mach-davinci/include/mach/common.h +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header for code common to all DaVinci machines. * * Author: Kevin Hilman, MontaVista Software, Inc. <[email protected]> * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. */ #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H
arch/arm/mach-davinci/include/mach/cputype.h +2 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * DaVinci CPU type detection *
@@ -8,10 +9,7 @@* compiled in to the kernel, the macros return 0 so that * resulting code can be optimized out. * -* 2009 (c) Deep Root Systems, LLC. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2009 (c) Deep Root Systems, LLC. */ #ifndef _ASM_ARCH_CPU_H#define _ASM_ARCH_CPU_H
arch/arm/mach-davinci/include/mach/da8xx.h +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Chip specific defines for DA8XX/OMAP L1XX SoC * * Author: Mark A. Greer <[email protected]> * -* 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007, 2009-2010 (c) MontaVista Software, Inc. */ #ifndef __ASM_ARCH_DAVINCI_DA8XX_H#define __ASM_ARCH_DAVINCI_DA8XX_H
arch/arm/mach-davinci/include/mach/hardware.h +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Hardware definitions common to all DaVinci family processors * * Author: Kevin Hilman, Deep Root Systems, LLC * -* 2007 (c) Deep Root Systems, LLC. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) Deep Root Systems, LLC. */ #ifndef __ASM_ARCH_HARDWARE_H#define __ASM_ARCH_HARDWARE_H
arch/arm/mach-davinci/include/mach/serial.h +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * DaVinci serial device definitions * * Author: Kevin Hilman, MontaVista Software, Inc. <[email protected]> * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. */ #ifndef __ASM_ARCH_SERIAL_H#define __ASM_ARCH_SERIAL_H
arch/arm/mach-davinci/mux.c +2 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Utility to set the DAVINCI MUX register from a table in mux.h *
@@ -8,10 +9,7 @@* * Written by Tony Lindgren * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. * * Copyright (C) 2008 Texas Instruments. */
arch/arm/mach-davinci/mux.h +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Pin-multiplex helper macros for TI DaVinci family devices * * Author: Vladimir Barinov, MontaVista Software, Inc. <[email protected]> * -* 2007 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2007 (c) MontaVista Software, Inc. * * Copyright (C) 2008 Texas Instruments. */
arch/arm/mach-davinci/pm_domain.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Runtime PM support code for DaVinci * * Author: Kevin Hilman * * Copyright (C) 2012 Texas Instruments, Inc. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/init.h> #include <linux/pm_runtime.h>
arch/arm/mach-dove/bridge-regs.h +2 -7
@@ -1,10 +1,5 @@ -/* -* Mbus-L to Mbus Bridge Registers -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Mbus-L to Mbus Bridge Registers */ #ifndef __ASM_ARCH_BRIDGE_REGS_H#define __ASM_ARCH_BRIDGE_REGS_H
arch/arm/mach-dove/cm-a510.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/cm-a510.c *
@@ -5,10 +6,6 @@* Konstantin Sinyuk <[email protected]> * * Based on Marvell DB-MV88AP510-BP Development Board Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-dove/common.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/common.c * * Core functions for Marvell Dove 88AP510 System On Chip -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/clk-provider.h>
arch/arm/mach-dove/common.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-dove/common.h * * Core functions for Marvell Dove 88AP510 System On Chip -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ARCH_DOVE_COMMON_H
arch/arm/mach-dove/dove-db-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/dove-db-setup.c * * Marvell DB-MV88AP510-BP Development Board Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-dove/dove.h +2 -7
@@ -1,10 +1,5 @@ -/* -* Generic definitions for Marvell Dove 88AP510 SoC -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Generic definitions for Marvell Dove 88AP510 SoC */ #ifndef __ASM_ARCH_DOVE_H#define __ASM_ARCH_DOVE_H
arch/arm/mach-dove/irq.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/irq.c * * Dove IRQ handling. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/init.h> #include <linux/irq.h>
arch/arm/mach-dove/irqs.h +2 -7
@@ -1,10 +1,5 @@ -/* -* IRQ definitions for Marvell Dove 88AP510 SoC -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* IRQ definitions for Marvell Dove 88AP510 SoC */ #ifndef __ASM_ARCH_IRQS_H#define __ASM_ARCH_IRQS_H
arch/arm/mach-dove/mpp.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/mpp.c * * MPP functions for Marvell Dove SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-dove/pcie.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-dove/pcie.c * * PCIe functions for Marvell Dove 88AP510 SoC -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-dove/pm.h +1 -5
@@ -1,8 +1,4 @@ -/* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __ASM_ARCH_PM_H#define __ASM_ARCH_PM_H
arch/arm/mach-lpc18xx/board-dt.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree board file for NXP LPC18xx/43xx * * Copyright (C) 2015 Joachim Eastwood <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <asm/mach/arch.h>
arch/arm/mach-lpc32xx/pm.c +2 -4
@@ -1,13 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-lpc32xx/pm.c * * Original authors: Vitaly Wool, Dmitry Chigirev <[email protected]> * Modified by Kevin Wells <[email protected]> * -* 2005 (c) MontaVista Software, Inc. This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. +* 2005 (c) MontaVista Software, Inc. */ /*
arch/arm/mach-lpc32xx/suspend.S +2 -4
@@ -1,13 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-lpc32xx/suspend.S * * Original authors: Dmitry Chigirev, Vitaly Wool <[email protected]> * Modified by Kevin Wells <[email protected]> * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2005 (c) MontaVista Software, Inc. */ #include <linux/linkage.h> #include <asm/assembler.h>
arch/arm/mach-mv78xx0/bridge-regs.h +1 -5
@@ -1,8 +1,4 @@ -/* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef __ASM_ARCH_BRIDGE_REGS_H#define __ASM_ARCH_BRIDGE_REGS_H
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c * * Buffalo WXL (Terastation Duo) Setup routines * * sebastien requiem <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mv78xx0/common.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/common.c * * Core functions for Marvell MV78xx0 SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mv78xx0/common.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-mv78xx0/common.h * * Core functions for Marvell MV78xx0 SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ARCH_MV78XX0_COMMON_H
arch/arm/mach-mv78xx0/db78x00-bp-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/db78x00-bp-setup.c * * Marvell DB-78x00-BP Development Board Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mv78xx0/irq.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/irq.c * * MV78xx0 IRQ handling. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-mv78xx0/irqs.h +2 -7
@@ -1,10 +1,5 @@ -/* -* IRQ definitions for Marvell MV78xx0 SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* IRQ definitions for Marvell MV78xx0 SoCs */ #ifndef __ASM_ARCH_IRQS_H#define __ASM_ARCH_IRQS_H
arch/arm/mach-mv78xx0/mpp.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78x00/mpp.c * * MPP functions for Marvell MV78x00 SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-mv78xx0/mpp.h +1 -5
@@ -1,12 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins * -* * sebastien requiem <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MV78X00_MPP_H
arch/arm/mach-mv78xx0/mv78xx0.h +1 -4
@@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Generic definitions for Marvell MV78xx0 SoC flavors: * MV781x0 and MV782x0. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ASM_ARCH_MV78XX0_H
arch/arm/mach-mv78xx0/pcie.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78xx0/pcie.c * * PCIe functions for Marvell MV78xx0 SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mv78x00/rd78x00-masa-setup.c * * Marvell RD-78x00-mASA Development Board Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mvebu/armada-370-xp.h +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Generic definitions for Marvell Armada_370_XP SoCs *
@@ -6,10 +7,6 @@* Lior Amsalem <[email protected]> * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_ARMADA_370_XP_H
arch/arm/mach-mvebu/board-v7.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Device Tree support for Armada 370 and XP platforms. *
@@ -6,10 +7,6 @@* Lior Amsalem <[email protected]> * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-mvebu/coherency.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP * platforms.
@@ -8,10 +9,6 @@* Gregory Clement <[email protected]> * Thomas Petazzoni <[email protected]> * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is * responsible for ensuring hardware coherency between all CPUs and between * CPUs and I/O masters. This file initializes the coherency fabric and
arch/arm/mach-mvebu/coherency.h +1 -5
@@ -1,14 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-mvebu/include/mach/coherency.h * -* * Coherency fabric (Aurora) support for Armada 370 and XP platforms. * * Copyright (C) 2012 Marvell -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_370_XP_COHERENCY_H
arch/arm/mach-mvebu/coherency_ll.S +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Coherency fabric: low level functions *
@@ -5,10 +6,6 @@ * * Gregory CLEMENT <[email protected]> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file implements the assembly function to add a CPU to the * coherency fabric. This function is called by each of the secondary * CPUs during their early boot in an SMP kernel, this why this
arch/arm/mach-mvebu/common.h +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Core functions for Marvell System On Chip *
@@ -6,10 +7,6 @@* Lior Amsalem <[email protected]> * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ARCH_MVEBU_COMMON_H
arch/arm/mach-mvebu/cpu-reset.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 Marvell * * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "mvebu-cpureset: " fmt
arch/arm/mach-mvebu/dove.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-mvebu/dove.c * * Marvell Dove 88AP510 System On Chip FDT Board -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/init.h>
arch/arm/mach-mvebu/headsmp-a9.S +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * SMP support: Entry point for secondary CPUs of Marvell EBU * Cortex-A9 based SOCs (Armada 375 and Armada 38x).
@@ -6,10 +7,6 @@ * * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/linkage.h>
arch/arm/mach-mvebu/headsmp.S +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * SMP support: Entry point for secondary CPUs *
@@ -7,10 +8,6 @@ * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * * This file implements the assembly entry point for secondary CPUs in * an SMP kernel. The only thing we need to do is to add the CPU to * the coherency fabric by writing to 2 registers. Currently the base
arch/arm/mach-mvebu/kirkwood.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2012 (C), Jason Cooper <[email protected]> * * arch/arm/mach-mvebu/kirkwood.c * * Flattened Device Tree board initialization -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/clk.h>
arch/arm/mach-mvebu/kirkwood.h +1 -4
@@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-mvebu/kirkwood.h * * Generic definitions for Marvell Kirkwood SoC flavors: * 88F6180, 88F6192 and 88F6281. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
arch/arm/mach-mvebu/mvebu-soc-id.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * ID and revision information for mvebu SoCs *
@@ -5,10 +6,6 @@* * Gregory CLEMENT <[email protected]> * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * All the mvebu SoCs have information related to their variant and * revision that can be read from the PCI control register. This is * done before the PCI initialization to avoid any conflict. Once the
arch/arm/mach-mvebu/mvebu-soc-id.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Marvell EBU SoC ID and revision definitions. * * Copyright (C) 2014 Marvell Semiconductor -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __LINUX_MVEBU_SOC_ID_H
arch/arm/mach-mvebu/platsmp-a9.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Symmetric Multi Processing (SMP) support for Marvell EBU Cortex-A9 * based SOCs (Armada 375/38x).
@@ -6,10 +7,6 @@* * Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/init.h>
arch/arm/mach-mvebu/platsmp.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Symmetric Multi Processing (SMP) support for Armada XP *
@@ -8,10 +9,6 @@* Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency * This file implements the routines for preparing the SMP infrastructure * and waking up the secondary CPUs
arch/arm/mach-mvebu/pm-board.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Board-level suspend/resume support. * * Copyright (C) 2014-2015 Marvell * * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/delay.h>
arch/arm/mach-mvebu/pm.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Suspend/resume support. Currently supporting Armada XP only. * * Copyright (C) 2014 Marvell * * Thomas Petazzoni <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/cpu_pm.h>
arch/arm/mach-mvebu/pmsu.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. *
@@ -7,10 +8,6 @@* Gregory Clement <[email protected]> * Thomas Petazzoni <[email protected]> * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * The Armada 370 and Armada XP SOCs have a power management service * unit which is responsible for powering down and waking up CPUs and * other SOC units
arch/arm/mach-mvebu/pmsu.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Power Management Service Unit (PMSU) support for Armada 370/XP platforms. * * Copyright (C) 2012 Marvell -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_MVEBU_PMSU_H
arch/arm/mach-mvebu/pmsu_ll.S +1 -4
@@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Marvell * * Thomas Petazzoni <[email protected]> * Gregory Clement <[email protected]> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/linkage.h>
arch/arm/mach-mvebu/system-controller.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * System controller support for Armada 370, 375 and XP platforms. *
@@ -7,10 +8,6 @@* Gregory CLEMENT <[email protected]> * Thomas Petazzoni <[email protected]> * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * The Armada 370, 375 and Armada XP SoCs have a range of * miscellaneous registers, that do not belong to a particular device, * but rather provide system-level features. This basic
arch/arm/mach-omap1/include/mach/mtd-xip.h +2 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * MTD primitives for XIP support. Architecture specific functions. *
@@ -5,10 +6,7 @@* * Author: Vladimir Barinov <[email protected]> * -* (c) 2005 MontaVista Software, Inc. This file is licensed under the -* terms of the GNU General Public License version 2. This program is -* licensed "as is" without any warranty of any kind, whether express or -* implied. +* (c) 2005 MontaVista Software, Inc. */ #ifndef __ARCH_OMAP_MTD_XIP_H__
arch/arm/mach-omap1/pm_bus.c +1 -5
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Runtime PM support code for OMAP1 * * Author: Kevin Hilman, Deep Root Systems, LLC * * Copyright (C) 2010 Texas Instruments, Inc. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/init.h> #include <linux/kernel.h>
@@ -43,4 +40,3 @@ static int __init omap1_pm_runtime_init(void)return 0 ; }core_initcall (omap1_pm_runtime_init); -
arch/arm/mach-omap2/prcm43xx.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * AM43x PRCM defines * * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ -* -* This file is licensed under the terms of the GNU General Public License -* version 2. This program is licensed "as is" without any warranty of any -* kind, whether express or implied. */ #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H
arch/arm/mach-omap2/vc.c +1 -5
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * OMAP Voltage Controller (VC) interface * * Copyright (C) 2011 Texas Instruments, Inc. -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h> #include <linux/delay.h>
@@ -895,4 +892,3 @@ void __init omap_vc_init_channel(struct voltagedomain *voltdm)else if (cpu_is_omap44xx ())omap4_vc_init_channel (voltdm); } -
arch/arm/mach-orion5x/board-d2net.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/board-d2net.c * * LaCie d2Network and Big Disk Network NAS setup * * Copyright (C) 2009 Simon Guinot <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/board-dt.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright 2012 (C), Thomas Petazzoni <[email protected]> * * arch/arm/mach-orion5x/board-dt.c * * Flattened Device Tree board initialization -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/board-rd88f5182.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/rd88f5182-setup.c * * Marvell Orion-NAS Reference Design Setup * * Maintainer: Ronen Shitrit <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/bridge-regs.h +2 -7
@@ -1,10 +1,5 @@ -/* -* Orion CPU Bridge Registers -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Orion CPU Bridge Registers */ #ifndef __ASM_ARCH_BRIDGE_REGS_H#define __ASM_ARCH_BRIDGE_REGS_H
arch/arm/mach-orion5x/common.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/common.c * * Core functions for Marvell Orion 5x SoCs * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/db88f5281-setup.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/db88f5281-setup.c * * Marvell Orion-2 Development Board Setup * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/irq.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/irq.c * * Core IRQ functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/irqs.h +1 -4
@@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * IRQ definitions for Orion SoC * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ASM_ARCH_IRQS_H
arch/arm/mach-orion5x/kurobox_pro-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/kurobox_pro-setup.c * * Maintainer: Ronen Shitrit <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/ls_hgl-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/ls_hgl-setup.c * * Maintainer: Zhu Qingsen <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/mpp.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/mpp.c * * MPP functions for Marvell Orion 5x SoCs -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/net2big-setup.c +1 -5
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/net2big-setup.c * * LaCie 2Big Network NAS setup * * Copyright (C) 2009 Simon Guinot <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
@@ -432,4 +429,3 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network") .fixup = tag_fixup_mem32, .restart = orion5x_restart,MACHINE_END -
arch/arm/mach-orion5x/orion5x.h +1 -4
@@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Generic definitions of Orion SoC flavors: * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __ASM_ARCH_ORION5X_H
arch/arm/mach-orion5x/pci.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/pci.c * * PCI and PCIe functions for Marvell Orion System On Chip * * Maintainer: Tzachi Perelstein <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/kernel.h>
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c * * Marvell Orion-VoIP FXO Reference Design Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c * * Marvell Orion-VoIP GE Reference Design Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/rd88f5182-setup.c +1 -4
@@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/rd88f5182-setup.c * * Marvell Orion-NAS Reference Design Setup * * Maintainer: Ronen Shitrit <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c * * Marvell Orion-1-90 AP GE Reference Design Setup -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/gpio.h> #include <linux/kernel.h>
arch/arm/mach-orion5x/ts78xx-setup.c +1 -4
@@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-orion5x/ts78xx-setup.c * * Maintainer: Alexander Clouter <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) KBUILD_MODNAME ": " fmt
arch/arm/mach-orion5x/wnr854t-setup.c +2 -7
@@ -1,10 +1,5 @@ -/* -* arch/arm/mach-orion5x/wnr854t-setup.c -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +// SPDX-License-Identifier: GPL-2.0-only +// arch/arm/mach-orion5x/wnr854t-setup.c #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-orion5x/wrt350n-v2-setup.c +2 -7
@@ -1,10 +1,5 @@ -/* -* arch/arm/mach-orion5x/wrt350n-v2-setup.c -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -*/ +// SPDX-License-Identifier: GPL-2.0-only +// arch/arm/mach-orion5x/wrt350n-v2-setup.c #include <linux/gpio.h> #include <linux/kernel.h> #include <linux/init.h>
arch/arm/mach-pxa/eseries.c +1 -6
@@ -1,13 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Hardware definitions for the Toshiba eseries PDAs * * Copyright (c) 2003 Ian Molton <[email protected]> -* -* This file is licensed under -* the terms of the GNU General Public License version 2. This program -* is licensed "as is" without any warranty of any kind, whether express -* or implied. -* */ #include <linux/clkdev.h>
arch/arm/mach-pxa/standby.S +2 -4
@@ -1,12 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * PXA27x standby mode * * Author: David Burrage * - * 2005 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. + * 2005 (c) MontaVista Software, Inc. */ #include <linux/linkage.h>
arch/arm/mach-spear/generic.h +1 -4
@@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * spear machine family generic header file * * Copyright (C) 2009-2012 ST Microelectronics * Rajeev Kumar <[email protected]> * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_GENERIC_H
arch/arm/mach-spear/include/mach/misc_regs.h +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/mach-spear3xx/include/mach/misc_regs.h *
@@ -5,10 +6,6 @@* * Copyright (C) 2009 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_MISC_REGS_H
arch/arm/mach-spear/include/mach/spear.h +1 -4
@@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * SPEAr3xx/6xx Machine family specific definition * * Copyright (C) 2009,2012 ST Microelectronics * Rajeev Kumar<[email protected]> * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __MACH_SPEAR_H
arch/arm/mach-spear/pl080.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/plat-spear/pl080.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/amba/pl08x.h>
arch/arm/mach-spear/pl080.h +1 -4
@@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * arch/arm/plat-spear/include/plat/pl080.h *
@@ -5,10 +6,6 @@* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #ifndef __PLAT_PL080_H
arch/arm/mach-spear/restart.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/plat-spear/restart.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2009 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/io.h> #include <linux/amba/sp810.h>
arch/arm/mach-spear/spear1310.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear13xx/spear1310.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr1310: " fmt
arch/arm/mach-spear/spear1340.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear13xx/spear1340.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr1340: " fmt
arch/arm/mach-spear/spear13xx.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear13xx/spear13xx.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr13xx: " fmt
arch/arm/mach-spear/spear300.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear3xx/spear300.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2009-2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr300: " fmt
arch/arm/mach-spear/spear310.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear3xx/spear310.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2009-2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr310: " fmt
arch/arm/mach-spear/spear320.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear3xx/spear320.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2009-2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr320: " fmt
arch/arm/mach-spear/spear3xx.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear3xx/spear3xx.c *
@@ -5,10 +6,6 @@* * Copyright (C) 2009-2012 ST Microelectronics * Viresh Kumar <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #define pr_fmt (fmt) "SPEAr3xx: " fmt
arch/arm/mach-spear/spear6xx.c +1 -4
@@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mach-spear6xx/spear6xx.c *
@@ -7,10 +8,6 @@* Rajeev Kumar<[email protected]> * * Copyright 2012 Stefan Roese <[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/amba/pl08x.h>
arch/arm/mach-spear/time.c +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/plat-spear/time.c * * Copyright (C) 2010 ST Microelectronics * Shiraz Hashim<[email protected]> -* -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. */ #include <linux/clk.h>
arch/arm/mm/cache-feroceon-l2.c +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support * * Copyright (C) 2008 Marvell Semiconductor * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * References: * - Unified Layer 2 Cache for Feroceon CPU Cores, * Document ID MV-S104858-00, Rev. A, October 23 2007.
arch/arm/mm/cache-tauros2.c +1 -4
@@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support * * Copyright (C) 2008 Marvell Semiconductor * -* This file is licensed under the terms of the GNU General Public -* License version 2. This program is licensed "as is" without any -* warranty of any kind, whether express or implied. -* * References: * - PJ1 CPU Core Datasheet, * Document ID MV-S104837-01, Rev 0.7, January 24 2008.
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 97/183 ARM: dts: omap: correct indentation
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Krzysztof Kozlowski <[email protected]>
[ Upstream commit 8ae9c7a69fa14e95d032e64d8d758e3f85bee132 ]
Do not use spaces for indentation.
Stable-dep-of: 6469b2feade8 ("ARM: dts: ti: omap: Fix bandgap thermal cells addressing for omap3/4")
--- arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi | 6 +-- arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi | 6 +-- arch/arm/boot/dts/omap3-cm-t3517.dts | 12 ++--- arch/arm/boot/dts/omap3-gta04.dtsi | 6 +-- arch/arm/boot/dts/omap3-ldp.dts | 2 +- arch/arm/boot/dts/omap3-n900.dts | 38 +++++++------- arch/arm/boot/dts/omap3-zoom3.dts | 44 ++++++++-------- arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 24 ++++----- arch/arm/boot/dts/omap5-cm-t54.dts | 64 +++++++++++------------ 9 files changed, 101 insertions(+), 101 deletions(-)
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +3 -3
@@ -8,9 +8,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a {
arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi +3 -3
@@ -12,9 +12,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a {
arch/arm/boot/dts/omap3-cm-t3517.dts +6 -6
@@ -11,12 +11,12 @@ model = "CompuLab CM-T3517"; compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; wl12xx_vmmc2: wl12xx_vmmc2 { compatible = "regulator-fixed";
arch/arm/boot/dts/omap3-gta04.dtsi +3 -3
@@ -332,7 +332,7 @@ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; - }; + }; gps_pins: pinmux_gps_pins { pinctrl-single,pins = <
@@ -866,8 +866,8 @@ }; &hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; }; /* image signal processor within OMAP3 SoC */
arch/arm/boot/dts/omap3-ldp.dts +1 -1
@@ -301,5 +301,5 @@ &vaux1 { /* Needed for ads7846 */ - regulator-name = "vcc"; + regulator-name = "vcc"; };
arch/arm/boot/dts/omap3-n900.dts +19 -19
@@ -236,27 +236,27 @@ pinctrl-single,pins = < /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ /* * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable * according to TRM. OneNAND seems to require PIN_INPUT on clock. */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; }; i2c1_pins: pinmux_i2c1_pins {
@@ -738,12 +738,12 @@ si4713: si4713@63 { compatible = "silabs,si4713"; - reg = <0x63>; + reg = <0x63>; - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ + reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ + vio-supply = <&vio>; + vdd-supply = <&vaux1>; }; bq24150a: bq24150a@6b {
arch/arm/boot/dts/omap3-zoom3.dts +22 -22
81 lines not on this page · raw message
arch/arm/boot/dts/omap4-cpu-thermal.dtsi +12 -12
@@ -13,20 +13,20 @@ cpu_thermal: cpu_thermal { polling-delay = <1000>; /* milliseconds */ /* sensor ID */ - thermal-sensors = <&bandgap 0>; + thermal-sensors = <&bandgap 0>; cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; + cpu_alert0: cpu_alert { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <125000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; cpu_cooling_maps: cooling-maps { map0 {
arch/arm/boot/dts/omap5-cm-t54.dts +32 -32
76 lines not on this page · raw message
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 98/183 ARM: dts: ti: omap: Fix bandgap thermal cells addressing for omap3/4
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tony Lindgren <[email protected]>
[ Upstream commit 6469b2feade8fd82d224dd3734e146536f3e9f0e ]
Fix "thermal_sys: cpu_thermal: Failed to read thermal-sensors cells: -2" error on boot for omap3/4. This is caused by wrong addressing in the dts for bandgap sensor for single sensor instances.
Note that omap4-cpu-thermal.dtsi is shared across omap4/5 and dra7, so we can't just change the addressing in omap4-cpu-thermal.dtsi.
--- arch/arm/boot/dts/omap3-cpu-thermal.dtsi | 3 +-- arch/arm/boot/dts/omap4-cpu-thermal.dtsi | 5 ++++- arch/arm/boot/dts/omap443x.dtsi | 1 + arch/arm/boot/dts/omap4460.dtsi | 1 + 4 files changed, 7 insertions(+), 3 deletions(-)
arch/arm/boot/dts/omap3-cpu-thermal.dtsi +1 -2
@@ -12,8 +12,7 @@ cpu_thermal: cpu_thermal { polling-delay = <1000>; /* milliseconds */ coefficients = <0 20000>; - /* sensor ID */ - thermal-sensors = <&bandgap 0>; + thermal-sensors = <&bandgap>; cpu_trips: trips { cpu_alert0: cpu_alert {
arch/arm/boot/dts/omap4-cpu-thermal.dtsi +4 -1
@@ -12,7 +12,10 @@ cpu_thermal: cpu_thermal { polling-delay-passive = <250>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ - /* sensor ID */ + /* + * See 44xx files for single sensor addressing, omap5 and dra7 need + * also sensor ID for addressing. + */ thermal-sensors = <&bandgap 0>; cpu_trips: trips {
arch/arm/boot/dts/omap443x.dtsi +1 -0
@@ -69,6 +69,7 @@ }; &cpu_thermal { + thermal-sensors = <&bandgap>; coefficients = <0 20000>; };
arch/arm/boot/dts/omap4460.dtsi +1 -0
@@ -79,6 +79,7 @@ }; &cpu_thermal { + thermal-sensors = <&bandgap>; coefficients = <348 (-9301)>; };
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 99/183 ARM: dts: ti: omap: motorola-mapphone: Fix abe_clkctrl warning on boot
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tony Lindgren <[email protected]>
[ Upstream commit ac08bda1569b06b7a62c7b4dd00d4c3b28ceaaec ]
Commit 0840242e8875 ("ARM: dts: Configure clock parent for pwm vibra") attempted to fix the PWM settings but ended up causin an additional clock reparenting error:
clk: failed to reparent abe-clkctrl:0060:24 to sys_clkin_ck: -22
Only timer9 is in the PER domain and can use the sys_clkin_ck clock source. For timer8, the there is no sys_clkin_ck available as it's in the ABE domain, instead it should use syc_clk_div_ck. However, for power management, we want to use the always on sys_32k_ck instead.
Depends-on: 61978617e905 ("ARM: dts: Add minimal support for Droid Bionic xt875")
--- arch/arm/boot/dts/motorola-mapphone-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/boot/dts/motorola-mapphone-common.dtsi +2 -2
@@ -614,12 +614,12 @@ /* Configure pwm clock source for timers 8 & 9 */ &timer8 { assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; &timer9 { assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; /*
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 100/183 bus: ti-sysc: Fix SYSC_QUIRK_SWSUP_SIDLE_ACT handling for uart wake-up
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Tony Lindgren <[email protected]>
[ Upstream commit e5deb8f76e64d94ccef715e75ebafffd0c312d80 ]
The uarts should be tagged with SYSC_QUIRK_SWSUP_SIDLE instead of SYSC_QUIRK_SWSUP_SIDLE_ACT. The difference is that SYSC_QUIRK_SWSUP_SIDLE is used to force idle target modules rather than block idle during usage.
The SYSC_QUIRK_SWSUP_SIDLE_ACT should disable autoidle and wake-up when a target module is active, and configure autoidle and wake-up when a target module is inactive. We are missing configuring the target module on sysc_disable_module(), and missing toggling of the wake-up bit.
Let's fix the issue to allow uart wake-up to work.
--- drivers/bus/ti-sysc.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
drivers/bus/ti-sysc.c +17 -5
@@ -1118,6 +1118,11 @@ static int sysc_enable_module(struct device *dev)if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_SWSUP_SIDLE_ACT )) { best_mode =SYSC_IDLE_NO ; + +/* Clear WAKEUP */ +if (regbits->enwkup_shift >=0 && + ddata->cfg.sysc_val &BIT (regbits->enwkup_shift)) + reg &= ~BIT (regbits->enwkup_shift); }else { best_mode =fls (ddata->cfg.sidlemodes) -1 ;if (best_mode >SYSC_IDLE_MASK ) {
@@ -1238,6 +1243,13 @@ static int sysc_disable_module(struct device *dev) } } +if (ddata->cfg.quirks &SYSC_QUIRK_SWSUP_SIDLE_ACT ) { +/* Set WAKEUP */ +if (regbits->enwkup_shift >=0 && + ddata->cfg.sysc_val &BIT (regbits->enwkup_shift)) + reg |=BIT (regbits->enwkup_shift); + } + reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); reg |= best_mode << regbits->sidle_shift; if (regbits->autoidle_shift >= 0 &&
@@ -1497,16 +1509,16 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {SYSC_QUIRK ("sham" ,0 ,0x100 ,0x110 ,0x114 ,0x40000c03 ,0xffffffff ,SYSC_QUIRK_LEGACY_IDLE ),SYSC_QUIRK ("uart" ,0 ,0x50 ,0x54 ,0x58 ,0x00000046 ,0xffffffff , -SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_LEGACY_IDLE ), +SYSC_QUIRK_SWSUP_SIDLE_ACT |SYSC_QUIRK_LEGACY_IDLE ),SYSC_QUIRK ("uart" ,0 ,0x50 ,0x54 ,0x58 ,0x00000052 ,0xffffffff , -SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_LEGACY_IDLE ), +SYSC_QUIRK_SWSUP_SIDLE_ACT |SYSC_QUIRK_LEGACY_IDLE ),/* Uarts on omap4 and later */ SYSC_QUIRK ("uart" ,0 ,0x50 ,0x54 ,0x58 ,0x50411e03 ,0xffff00ff , -SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_LEGACY_IDLE ), +SYSC_QUIRK_SWSUP_SIDLE_ACT |SYSC_QUIRK_LEGACY_IDLE ),SYSC_QUIRK ("uart" ,0 ,0x50 ,0x54 ,0x58 ,0x47422e03 ,0xffffffff , -SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_LEGACY_IDLE ), +SYSC_QUIRK_SWSUP_SIDLE_ACT |SYSC_QUIRK_LEGACY_IDLE ),SYSC_QUIRK ("uart" ,0 ,0x50 ,0x54 ,0x58 ,0x47424e03 ,0xffffffff , -SYSC_QUIRK_SWSUP_SIDLE |SYSC_QUIRK_LEGACY_IDLE ), +SYSC_QUIRK_SWSUP_SIDLE_ACT |SYSC_QUIRK_LEGACY_IDLE ),/* Quirks that need to be set based on the module address */ SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 101/183 power: supply: ucs1002: fix error code in ucs1002_get_property()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dan Carpenter <[email protected]>
[ Upstream commit e35059949daa83f8dadf710d0f829ab3c3a72fe2 ]
This function is supposed to return 0 for success instead of returning the val->intval. This makes it the same as the other case statements in this function.
--- drivers/power/supply/ucs1002_power.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/power/supply/ucs1002_power.c +2 -1
@@ -384,7 +384,8 @@ static int ucs1002_get_property(struct power_supply *psy,case POWER_SUPPLY_PROP_USB_TYPE :return ucs1002_get_usb_type (info, val);case POWER_SUPPLY_PROP_HEALTH : -return val->intval = info->health; + val->intval = info->health; +return 0 ;case POWER_SUPPLY_PROP_PRESENT : val->intval = info->present;return 0 ;
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 102/183 firmware: imx-dsp: Fix an error handling path in imx_dsp_setup_channels()
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Christophe JAILLET <[email protected]>
[ Upstream commit e527adfb9b7d9d05a4577c116519e59a2bda4b05 ]
If mbox_request_channel_byname() fails, the memory allocated a few lines above still need to be freed before going to the error handling path.
--- drivers/firmware/imx/imx-dsp.c | 1 + 1 file changed, 1 insertion(+)
drivers/firmware/imx/imx-dsp.c +1 -0
@@ -115,6 +115,7 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) dsp_chan->idx = i %2 ; dsp_chan->ch =mbox_request_channel_byname (cl, chan_name);if (IS_ERR (dsp_chan->ch)) { +kfree (dsp_chan->name); ret =PTR_ERR (dsp_chan->ch);if (ret != -EPROBE_DEFER ) dev_err(dev, "Failed to request mbox chan %s ret %d\n",
Signature · 1 line
2.40.1
Greg Kroah-Hartman
maintainerPATCH 103/183 xtensa: add default definition for XCHAL_HAVE_DIV32
In reply to Greg Kroah-Hartman5.15-stable review patch. If anyone has any objections, please let me know.
------------------
From: Max Filippov <[email protected]>
[ Upstream commit 494e87ffa0159b3f879694a9231089707792a44d ]
When variant FSF is set, XCHAL_HAVE_DIV32 is not defined. Add default definition for that macro to prevent build warnings:
arch/xtensa/lib/divsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32
arch/xtensa/lib/modsi3.S:9:5: warning: "XCHAL_HAVE_DIV32" is not defined, evaluates to 0 [-Wundef]
9 | #if XCHAL_HAVE_DIV32--- arch/xtensa/include/asm/core.h | 4 ++++ 1 file changed, 4 insertions(+)
arch/xtensa/include/asm/core.h +4 -0
@@ -6,6 +6,10 @@#include <variant/core.h> +#ifndef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 0 +#endif +#ifndef XCHAL_HAVE_EXCLUSIVE #define XCHAL_HAVE_EXCLUSIVE 0#endif
Signature · 1 line
2.40.1