Add Milk-V Duo board support
Subsystems (6)
v2 cover Add Milk-V Duo board support
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series[3] for the vendor prefix and ARCH_SOPHGO option.
since v1:
- fix dtbs_check warning
- add clint node
- sort dts in Makefile
Jisheng Zhang (5):
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
dt-bindings: timer: Add SOPHGO CV1800B clint
dt-bindings: riscv: Add Milk-V Duo board compatibles
riscv: dts: sophgo: add initial CV1800B SoC device tree
riscv: dts: sophgo: add Milk-V Duo board device tree
.../sifive,plic-1.0.0.yaml | 1 + .../devicetree/bindings/riscv/sophgo.yaml | 4 + .../bindings/timer/sifive,clint.yaml | 1 + arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 ++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 123 ++++++++++++++++++ 6 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
Signature · 1 line
2.40.1
PATCH v2 1/5 dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
Add compatible string for SOPHGO CV1800B plic.
--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0
@@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,cv1800b-plic - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic
Signature · 1 line
2.40.1
PATCH v2 2/5 dt-bindings: timer: Add SOPHGO CV1800B clint
In reply to Jisheng ZhangAdd compatible string for the SOPHGO CV1800B clint.
--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/timer/sifive,clint.yaml +1 -0
@@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - sophgo,cv1800b-clint - thead,th1520-clint - const: thead,c900-clint - items:
Signature · 1 line
2.40.1
PATCH v2 3/5 dt-bindings: riscv: Add Milk-V Duo board compatibles
In reply to Jisheng ZhangDocument the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2].
--- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/riscv/sophgo.yaml +4 -0
@@ -18,6 +18,10 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - milkv,duo + - const: sophgo,cv1800b - items: - enum: - milkv,pioneer
Signature · 1 line
2.40.1
PATCH v2 4/5 riscv: dts: sophgo: add initial CV1800B SoC device tree
In reply to Jisheng ZhangAdd initial device tree for the CV1800B RISC-V SoC by SOPHGO.
--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 123 ++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +123 -0
@@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +};
Signature · 1 line
2.40.1
Re: [PATCH v2 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree
Quoted 3 lines · Jisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
Signed-off-by Jisheng Zhang <[email protected]>
Thanks, Chen
Quoted 134 lines
--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 123 ++++++++++++++++++++++++ 1 file changed, 123 insertions(+)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b.dtsiarch/riscv/boot/dts/sophgo/cv1800b.dtsi new file +123
-0@@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +};
PATCH v2 5/5 riscv: dts: sophgo: add Milk-V Duo board device tree
In reply to Jisheng ZhangMilk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board.
Support basic uart drivers, so supports booting to a basic shell.
--- arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
arch/riscv/boot/dts/sophgo/Makefile +1 -1
@@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb -
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts new file +38 -0
@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +/dts-v1/; + +#include "cv1800b.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo", "sophgo,cv1800b"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x3f40000>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};
Signature · 1 line
2.40.1
Re: [PATCH v2 5/5] riscv: dts: sophgo: add Milk-V Duo board device tree
Quoted 7 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board.
Support basic uart drivers, so supports booting to a basic shell.
Link https://milkv.io/duo [1]Signed-off-by Jisheng Zhang <[email protected]>
Thanks, Chen
Quoted 59 lines
--- arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-)create mode 100644
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dtsarch/riscv/boot/dts/sophgo/Makefile +1
-1@@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb -arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts new file +38
-0@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <[email protected]> + */ + +/dts-v1/; + +#include "cv1800b.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo", "sophgo,cv1800b"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x3f40000>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};
From: Conor Dooley <[email protected]>
Quoted 8 lines · Jisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B[2] chip. Add minimal device tree files for the development board. Currently, now it's supported to boot to a basic shell.
NOTE: this series is based on the SG2042 upstream series[3] for the vendor prefix and
ARCH_SOPHGOoption.[...]
These look grand to me, so I have applied them on a temp. basis to a "sophgo" branch. I'll merge it in for real to the riscv-dt-for-next if my changes to the prereq series for the sg2042 are acceptable to their authors.
[1/5] dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic
https://git.kernel.org/conor/c/101276d77e84 [2/5] dt-bindings: timer: Add SOPHGO CV1800B clint https://git.kernel.org/conor/c/a3a24243b83b [3/5] dt-bindings: riscv: Add Milk-V Duo board compatibles https://git.kernel.org/conor/c/533874200f8c [4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree https://git.kernel.org/conor/c/4e31e0e61845 [5/5] riscv: dts: sophgo: add Milk-V Duo board device tree https://git.kernel.org/conor/c/0edd1de88d35
Thanks,
Conor.