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FAILED: patch "[PATCH] drm/amd/display: Negate IPS allow and commit bits" failed to apply to 6.1-stable tree

PATCH [email protected] 1 participant 1 message Nov 24, 2023

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core
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The patch below does not apply to the 6.1-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y
git checkout FETCH_HEAD
git cherry-pick -x 5e8a0d3598b47ee5a57708072bdef08816264538
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2023112445-mutilator-landed-4578@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^..

Possible dependencies:

5e8a0d3598b4 ("drm/amd/display: Negate IPS allow and commit bits")
92e11f0159f6 ("drm/amd/display: Enable more IPS options")
da2d16fcdda3 ("drm/amd/display: Fix IPS handshake for idle optimizations") d591284288c2 ("drm/amd/display: Add a check for idle power optimization") d5f9a92bd1e2 ("drm/amd/display: Revert "Improve x86 and dmub ips handshake"") bf7951561051 ("drm/amd/display: reprogram det size while seamless boot") d0a767f7b8e2 ("drm/amd/display: Revert "drm/amd/display: Add a check for idle power optimization"") 2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")
2358ecdabe37 ("drm/amd/display: 3.2.254")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 5e8a0d3598b47ee5a57708072bdef08816264538 Mon Sep 17 00:00:00 2001
From: Duncan Ma <[email protected]>
Date: Wed, 25 Oct 2023 19:07:21 -0400
Subject: [PATCH] drm/amd/display: Negate IPS allow and commit bits

[WHY]
On s0i3, IPS mask isn't saved and restored.
It is reset to zero on exit.

If it is cleared unexpectedly, driver will
proceed operations while DCN is in IPS2 and
cause a hang.

[HOW]
Negate the bit logic. Default value of
zero indicates it is still in IPS2. Driver
must poll for the bit to assert.

Cc Mario Limonciello <[email protected]>
Cc Alex Deucher <[email protected]>
Cc [email protected]
Reviewed-by Charlene Liu <[email protected]>
Acked-by Alex Hung <[email protected]>
Signed-off-by Duncan Ma <[email protected]>
Tested-by Daniel Wheeler <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +9 -9
index 0fa4fcd00de2..507a7cf56711 100644
@@ -820,22 +820,22 @@ static void dcn35_set_idle_state(struct clk_mgr *clk_mgr_base, bool allow_idle)
 
 	if (dc->config.disable_ips == DMUB_IPS_ENABLE ||
 		dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) {
-		val |= DMUB_IPS1_ALLOW_MASK;
-		val |= DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
 		val = val & ~DMUB_IPS1_ALLOW_MASK;
 		val = val & ~DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
-		val |= DMUB_IPS1_ALLOW_MASK;
-		val = val & ~DMUB_IPS2_ALLOW_MASK;
-	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS1) {
 		val |= DMUB_IPS1_ALLOW_MASK;
 		val |= DMUB_IPS2_ALLOW_MASK;
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2) {
+		val = val & ~DMUB_IPS1_ALLOW_MASK;
+		val |= DMUB_IPS2_ALLOW_MASK;
+	} else if (dc->config.disable_ips == DMUB_IPS_DISABLE_IPS2_Z10) {
+		val = val & ~DMUB_IPS1_ALLOW_MASK;
+		val = val & ~DMUB_IPS2_ALLOW_MASK;
 	}
 
 	if (!allow_idle) {
-		val = val & ~DMUB_IPS1_ALLOW_MASK;
-		val = val & ~DMUB_IPS2_ALLOW_MASK;
+		val |= DMUB_IPS1_ALLOW_MASK;
+		val |= DMUB_IPS2_ALLOW_MASK;
 	}
 
 	dcn35_smu_write_ips_scratch(clk_mgr, val);
drivers/gpu/drm/amd/display/dc/core/dc.c +2 -2
index d8f434738212..76b47f178127 100644
@@ -4934,8 +4934,8 @@ bool dc_dmub_is_ips_idle_state(struct dc *dc)
 	if (dc->hwss.get_idle_state)
 		idle_state = dc->hwss.get_idle_state(dc);
 
-	if ((idle_state & DMUB_IPS1_ALLOW_MASK) ||
-		(idle_state & DMUB_IPS2_ALLOW_MASK))
+	if (!(idle_state & DMUB_IPS1_ALLOW_MASK) ||
+		!(idle_state & DMUB_IPS2_ALLOW_MASK))
 		return true;
 
 	return false;
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +5 -5
index e4c007203318..0e07699c1e83 100644
@@ -1202,11 +1202,11 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 		allow_state = dc->hwss.get_idle_state(dc);
 		dc->hwss.set_idle_state(dc, false);
 
-		if (allow_state & DMUB_IPS2_ALLOW_MASK) {
+		if (!(allow_state & DMUB_IPS2_ALLOW_MASK)) {
 			// Wait for evaluation time
 			udelay(dc->debug.ips2_eval_delay_us);
 			commit_state = dc->hwss.get_idle_state(dc);
-			if (commit_state & DMUB_IPS2_COMMIT_MASK) {
+			if (!(commit_state & DMUB_IPS2_COMMIT_MASK)) {
 				// Tell PMFW to exit low power state
 				dc->clk_mgr->funcs->exit_low_power_state(dc->clk_mgr);
 

@@ -1216,7 +1216,7 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 
 				for (i = 0; i < max_num_polls; ++i) {
 					commit_state = dc->hwss.get_idle_state(dc);
-					if (!(commit_state & DMUB_IPS2_COMMIT_MASK))
+					if (commit_state & DMUB_IPS2_COMMIT_MASK)
 						break;
 
 					udelay(1);

@@ -1235,10 +1235,10 @@ void dc_dmub_srv_exit_low_power_state(const struct dc *dc)
 		}
 
 		dc_dmub_srv_notify_idle(dc, false);
-		if (allow_state & DMUB_IPS1_ALLOW_MASK) {
+		if (!(allow_state & DMUB_IPS1_ALLOW_MASK)) {
 			for (i = 0; i < max_num_polls; ++i) {
 				commit_state = dc->hwss.get_idle_state(dc);
-				if (!(commit_state & DMUB_IPS1_COMMIT_MASK))
+				if (commit_state & DMUB_IPS1_COMMIT_MASK)
 					break;
 
 				udelay(1);