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drm/msm/dpu: Correct UBWC settings for sc8280xp

PATCH Applied Rob Clark 4 participants 4 messages Nov 30, 2023 – Dec 3, 2023

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PATCH 1/1 drm/msm/dpu: Correct UBWC settings for sc8280xp

From: Rob Clark <[email protected]>

The UBWC settings need to match between the display and GPU. When we updated the GPU settings, we forgot to make the corresponding update on the display side.

Fixes 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
---
 drivers/gpu/drm/msm/msm_mdss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/msm/msm_mdss.c +1 -1
index 6865db1e3ce8..29bb38f0bb2c 100644
@@ -545,7 +545,7 @@ static const struct msm_mdss_data sc8280xp_data = {
 	.ubwc_dec_version = UBWC_4_0,
 	.ubwc_swizzle = 6,
 	.ubwc_static = 1,
-	.highest_bank_bit = 2,
+	.highest_bank_bit = 3,
 	.macrotile_mode = 1,
 };
 
Signature · 1 line
2.42.0
Tested-by on v1 1/1
#1 lore raw
Quoted 28 lines · Rob Clark

From: Rob Clark <[email protected]>

The UBWC settings need to match between the display and GPU. When we updated the GPU settings, we forgot to make the corresponding update on the display side.

Fixes 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
---
 drivers/gpu/drm/msm/msm_mdss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/msm/msm_mdss.c +1 -2
index 6865db1e3ce8..29bb38f0bb2c 100644
@@ -545,7 +545,7 @@ static const struct msm_mdss_data sc8280xp_data = {
        .ubwc_dec_version = UBWC_4_0,
        .ubwc_swizzle = 6,
        .ubwc_static = 1,
-       .highest_bank_bit = 2,
+       .highest_bank_bit = 3,
        .macrotile_mode = 1,
 };
 
--
Quoted 2 lines

2.42.0

Tested on Lenovo Thinkpad X13s

Reviewed-by on v1 1/1
#2 lore raw
In reply to Rob Clark
Quoted 10 lines · Rob Clark

From: Rob Clark <[email protected]>

The UBWC settings need to match between the display and GPU. When we updated the GPU settings, we forgot to make the corresponding update on the display side.

Fixes 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")

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