arm: dts: marvell: clearfog-gtr: miscellaneous enhancements
Subsystems (2)
cover arm: dts: marvell: clearfog-gtr: miscellaneous enhancements
Dear Maintainers,
The initially merged device-tree for Clearfog GTR devices contained various subtle mistakes and omissions:
- missing pinctrl entries
- off-by-1 errors on gpio numbers
- mismatch of labels between dsa ports and enclosure
- invalid sfp loss-of-signal gpio
- missing second sfp connector
Most notably this had caused functional issues with the mini-pci-e connectors and sfp module insertions were not detected.
This patch set includes corrections for all gpio references where appropriate, matching board revision 1.1.
The secondary sfp connector is added to board-variant "L8", connected to the managed ethernet switch port number 9.
To help support OpenWRT board-specific configurations, new compatible strings are added to both boards.
Documentation has not been added because marvell armada-388 dt-bindings are not yet converted to yaml, and document not a single board:Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
Finally labels of dsa switch ports were updated to match the enclosure. That patch is not suitable for stable.
Josua Mayer (5):
arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically
arm: dts: marvell: clearfog-gtr: fix various off-by-1 gpio numbers
arm: dts: marvell: clearfog-gtr-l8: add support for second sfp
connector
arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
.../marvell/armada-385-clearfog-gtr-l8.dts | 35 ++++-- .../marvell/armada-385-clearfog-gtr-s4.dts | 1 + .../dts/marvell/armada-385-clearfog-gtr.dtsi | 103 ++++++++++++------ 3 files changed, 99 insertions(+), 40 deletions(-)
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 1/5 arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies.
Add board-specific properties to both variants of the Clearfog GTR:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4
Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity.
Since announcement of the two products no additional variants were added it is assumed that there will always be just two.
--- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 1 + arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 1 + 2 files changed, 2 insertions(+)
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +1 -0
@@ -4,6 +4,7 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380"; }; &mdio {
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts +1 -0
@@ -4,6 +4,7 @@ / { model = "SolidRun Clearfog GTR S4"; + compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", "marvell,armada380"; }; &sfp0 {
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/5] arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
Quoted 24 lines · Josua Mayer
Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies.
Add board-specific properties to both variants of the Clearfog GTR:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity.
Since announcement of the two products no additional variants were added it is assumed that there will always be just two.Signed-off-by Josua Mayer <[email protected]>--- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 1 + arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 1 + 2 files changed, 2 insertions(+)arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +0
-0
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts line 7
Quoted 4 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +1
-0@@ -4,6 +4,7 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380";
Please run scripts/checkpatch.pl and fix reported warnings. Some warnings can be ignored, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear.
I don't see them being documented.
Also, wrap at 80, as Linux coding style asks.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/5] arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
Am 24.12.23 um 10:10 schrieb Krzysztof Kozlowski:
Quoted 26 lines · Josua Mayer
Quoted 25 lines
Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies.
Add board-specific properties to both variants of the Clearfog GTR:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity.
Since announcement of the two products no additional variants were added it is assumed that there will always be just two.Signed-off-by Josua Mayer <[email protected]>--- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 1 + arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 1 + 2 files changed, 2 insertions(+)arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +0
-0@@ -4,6 +4,7 @@
Quoted 8 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts line 7
Quoted 3 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +1
-0/ { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380";Please run
scripts/checkpatch.pland fix reported warnings. Some warnings can be ignored, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear.I don't see them being documented.
Yes, checkpatch warned about that specifially, but I am not sure how to proceed.
The armada-38x dt bindings documentation is stil in text format, and doesn't document any board:
Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
Quoted 2 lines
Also, wrap at 80, as Linux coding style asks.
Will do.
Quoted 4 lines
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/5] arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
Quoted 34 lines · Josua Mayer
Am 24.12.23 um 10:10 schrieb Krzysztof Kozlowski:
Quoted 33 lines · Josua Mayer
Quoted 24 lines
Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies.
Add board-specific properties to both variants of the Clearfog GTR:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity.
Since announcement of the two products no additional variants were added it is assumed that there will always be just two.Signed-off-by Josua Mayer <[email protected]>--- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 1 + arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 1 + 2 files changed, 2 insertions(+)arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +0
-0arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts line 7
Quoted 4 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +1
-0@@ -4,6 +4,7 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380";Please run
scripts/checkpatch.pland fix reported warnings. Some warnings can be ignored, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear.
Quoted 8 lines
Quoted 1 line
I don't see them being documented.
Yes, checkpatch warned about that specifially, but I am not sure how to proceed.
The armada-38x dt bindings documentation is stil in text format, and doesn't document any board:
Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
There was some work in progress, AFAIR. This should be solved before bringing more undocumented compatibles.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/5] arm: dts: marvell: clearfog-gtr: add board-specific compatible strings
Am 24.12.23 um 11:52 schrieb Krzysztof Kozlowski:
Quoted 36 lines · Josua Mayer
Quoted 35 lines
Am 24.12.23 um 10:10 schrieb Krzysztof Kozlowski:
Quoted 34 lines · Josua Mayer
Quoted 24 lines
Most arm board have a board-specific compatible string that allows e.g. userspace to match specific firmware variants or apply specific policies.
Add board-specific properties to both variants of the Clearfog GTR:
- solidrun,clearfog-gtr-l8
- solidrun,clearfog-gtr-s4Introduction of a common parent (e.g. "solidrun,clearfog-gtr") is omitted for brevity.
Since announcement of the two products no additional variants were added it is assumed that there will always be just two.Signed-off-by Josua Mayer <[email protected]>--- arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts | 1 + arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts | 1 + 2 files changed, 2 insertions(+)arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +0
-0arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts line 7
Quoted 4 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +1
-0@@ -4,6 +4,7 @@ / { model = "SolidRun Clearfog GTR L8"; + compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380";Please run
scripts/checkpatch.pland fix reported warnings. Some warnings can be ignored, but the code here looks like it needs a fix. Feel free to get in touch if the warning is not clear.I don't see them being documented.
Quoted 8 lines
Quoted 6 lines
Yes, checkpatch warned about that specifially, but I am not sure how to proceed.
The armada-38x dt bindings documentation is stil in text format, and doesn't document any board:
Documentation/devicetree/bindings/arm/marvell/armada-38x.txtThere was some work in progress, AFAIR. This should be solved before bringing more undocumented compatibles.
Okay. Since armada-38x.txt is small enough,
I have drafted conversion to yaml and new bindings. Will submit them as part of a v2 after validating other changes.
Thanks!
Quoted 4 lines
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 2/5 arm: dts: marvell: clearfog-gtr: sort pinctrl nodes alphabetically
In reply to Josua MayerCosmetic change to increase future patches readability when adding new pinctrl nodes.
--- .../dts/marvell/armada-385-clearfog-gtr.dtsi | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-)
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +20 -20
@@ -141,18 +141,13 @@ i2c@11100 { /* SFP (CON5/CON6) */ }; pinctrl@18000 { - cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { - marvell,pins = "mpp18"; - marvell,function = "gpio"; - }; - - cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { - marvell,pins = "mpp22"; + cf_gtr_fan_pwm: cf-gtr-fan-pwm { + marvell,pins = "mpp23"; marvell,function = "gpio"; }; - cf_gtr_fan_pwm: cf-gtr-fan-pwm { - marvell,pins = "mpp23"; + cf_gtr_front_button_pins: cf-gtr-front-button-pins { + marvell,pins = "mpp53"; marvell,function = "gpio"; };
@@ -162,13 +157,6 @@ cf_gtr_i2c1_pins: i2c1-pins { marvell,function = "i2c1"; }; - cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { - marvell,pins = "mpp21", "mpp28", - "mpp37", "mpp38", - "mpp39", "mpp40"; - marvell,function = "sd0"; - }; - cf_gtr_isolation_pins: cf-gtr-isolation-pins { marvell,pins = "mpp47"; marvell,function = "gpio";
@@ -179,18 +167,30 @@ cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,function = "gpio"; }; + cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { + marvell,pins = "mpp21", "mpp28", + "mpp37", "mpp38", + "mpp39", "mpp40"; + marvell,function = "sd0"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1"; }; - cf_gtr_front_button_pins: cf-gtr-front-button-pins { - marvell,pins = "mpp53"; + cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins { + marvell,pins = "mpp18"; marvell,function = "gpio"; }; - cf_gtr_rear_button_pins: cf-gtr-rear-button-pins { - marvell,pins = "mpp36"; + cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { + marvell,pins = "mpp22"; marvell,function = "gpio"; }; };
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 3/5 arm: dts: marvell: clearfog-gtr: fix various off-by-1 gpio numbers
In reply to Josua MayerVarious control signals such as sfp module-absence, pci-e reset or led gpios had off-by-1 mistakes where calculation from mpp number to gpio index in bank 1 was incorrect.
Fix all such mistakes, and add explicit pinctrl entries for those gpios where missing.
--- .../dts/marvell/armada-385-clearfog-gtr.dtsi | 61 ++++++++++++++----- 1 file changed, 47 insertions(+), 14 deletions(-)
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +47 -14
@@ -162,6 +162,22 @@ cf_gtr_isolation_pins: cf-gtr-isolation-pins { marvell,function = "gpio"; }; + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35"; + marvell,function = "gpio"; + }; + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,pins = "mpp48"; marvell,function = "gpio";
@@ -179,6 +195,12 @@ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { marvell,function = "sd0"; }; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1";
@@ -193,6 +215,11 @@ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { marvell,pins = "mpp22"; marvell,function = "gpio"; }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; + marvell,function = "gpio"; + }; }; sdhci@d8000 {
@@ -221,34 +248,38 @@ usb3@f8000 { }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ pcie@1,0 { - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; status = "okay"; }; pcie@2,0 { - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; pcie@3,0 { - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; status = "okay"; }; }; }; + /* CON5 */ sfp0: sfp { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; gpio-keys {
@@ -258,14 +289,14 @@ gpio-keys { button-0 { label = "Rear Button"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_0>; }; button-1 { label = "Front Button"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_1>; };
@@ -273,17 +304,19 @@ button-1 { gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; led2 { function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; }; }; };
@@ -408,7 +441,7 @@ &ahci1 { }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable {
@@ -420,12 +453,12 @@ wifi-disable { }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; + gpios = <3 GPIO_ACTIVE_LOW>; output-low; line-name = "lte-disable"; };
@@ -436,14 +469,14 @@ lte-disable { */ sar-isolation { gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; + gpios = <16 GPIO_ACTIVE_LOW>; output-low; line-name = "sar-isolation"; }; poe-reset { gpio-hog; - gpios = <16 GPIO_ACTIVE_LOW>; + gpios = <17 GPIO_ACTIVE_LOW>; output-low; line-name = "poe-reset"; };
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 3/5] arm: dts: marvell: clearfog-gtr: fix various off-by-1 gpio numbers
Hi everyone,
please disregard this patch, i added several mistakes of my own, will carefully rework this one for a v2.
Am 23.12.23 um 22:29 schrieb Josua Mayer:
Quoted 178 lines
Various control signals such as sfp module-absence, pci-e reset or led gpios had off-by-1 mistakes where calculation from mpp number to gpio index in bank 1 was incorrect.
Fix all such mistakes, and add explicit pinctrl entries for those gpios where missing.
Signed-off-by Josua Mayer <[email protected]>--- .../dts/marvell/armada-385-clearfog-gtr.dtsi | 61 ++++++++++++++----- 1 file changed, 47 insertions(+), 14 deletions(-)arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +46
-13@@ -162,6 +162,22 @@ cf_gtr_isolation_pins: cf-gtr-isolation-pins { marvell,function = "gpio"; }; + cf_gtr_led_pins: led-pins { + marvell,pins = "mpp42", "mpp52"; + marvell,function = "gpio"; + }; + + cf_gtr_lte_disable_pins: lte-disable-pins { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + cf_gtr_pci_pins: pci-pins { + // pci reset + marvell,pins = "mpp33", "mpp35"; + marvell,function = "gpio"; + }; + cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins { marvell,pins = "mpp48"; marvell,function = "gpio";@@ -179,6 +195,12 @@ cf_gtr_sdhci_pins: cf-gtr-sdhci-pins { marvell,function = "sd0"; }; + cf_gtr_sfp0_pins: sfp0-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp25", "mpp46"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1";@@ -193,6 +215,11 @@ cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus { marvell,pins = "mpp22"; marvell,function = "gpio"; }; + + cf_gtr_wifi_disable_pins: wifi-disable-pins { + marvell,pins = "mpp30", "mpp31"; + marvell,function = "gpio"; + }; }; sdhci@d8000 {@@ -221,34 +248,38 @@ usb3@f8000 { }; pcie { + pinctrl-0 = <&cf_gtr_pci_pins>; + pinctrl-names = "default"; status = "okay"; /* * The PCIe units are accessible through * the mini-PCIe connectors on the board. */ pcie@1,0 { - reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; status = "okay"; }; pcie@2,0 { - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; status = "okay"; }; pcie@3,0 { - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; status = "okay"; }; }; }; + /* CON5 */ sfp0: sfp { compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp0_pins>; + pinctrl-names = "default"; i2c-bus = <&i2c1>; - los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>; - tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + tx-disable-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; gpio-keys {@@ -258,14 +289,14 @@ gpio-keys { button-0 { label = "Rear Button"; - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_0>; }; button-1 { label = "Front Button"; - gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; linux,can-disable; linux,code = <BTN_1>; };@@ -273,17 +304,19 @@ button-1 { gpio-leds { compatible = "gpio-leds"; + pinctrl-0 = <&cf_gtr_led_pins>; + pinctrl-names = "default"; led1 { function = LED_FUNCTION_CPU; color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; led2 { function = LED_FUNCTION_HEARTBEAT; color = <LED_COLOR_ID_GREEN>; - gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; }; }; };@@ -408,7 +441,7 @@ &ahci1 { }; &gpio0 { - pinctrl-0 = <&cf_gtr_fan_pwm>; + pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; wifi-disable {@@ -420,12 +453,12 @@ wifi-disable { }; &gpio1 { - pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>; + pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; lte-disable { gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; + gpios = <3 GPIO_ACTIVE_LOW>; output-low; line-name = "lte-disable"; };@@ -436,14 +469,14 @@ lte-disable { */ sar-isolation { gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; + gpios = <16 GPIO_ACTIVE_LOW>; output-low;
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi lte-disable { · line 482
Quoted 10 lines
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +1
-1line-name = "sar-isolation"; }; poe-reset { gpio-hog; - gpios = <16 GPIO_ACTIVE_LOW>; + gpios = <17 GPIO_ACTIVE_LOW>; output-low; line-name = "poe-reset"; };
_______________________________________________
linux-arm-kernel mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 4/5 arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
In reply to Josua MayerClearfog GTR L8 has an extra SFP connector on the managed switch port 9. Add descriptions for both entities along with pinctrl.
--- .../dts/marvell/armada-385-clearfog-gtr-l8.dts | 18 ++++++++++++++++++ .../dts/marvell/armada-385-clearfog-gtr.dtsi | 8 +++++++- 2 files changed, 25 insertions(+), 1 deletion(-)
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +18 -0
@@ -5,6 +5,16 @@ / { model = "SolidRun Clearfog GTR L8"; compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", "marvell,armada380"; + + /* CON25 */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + pinctrl-0 = <&cf_gtr_sfp1_pins>; + pinctrl-names = "default"; + i2c-bus = <&i2c0>; + mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + }; }; &mdio {
@@ -67,6 +77,14 @@ port@8 { phy-handle = <&switch0phy7>; }; + port@9 { + reg = <9>; + label = "lan-sfp"; + phy-mode = "sgmii"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + port@10 { reg = <10>; phy-mode = "2500base-x";
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi +7 -1
@@ -201,6 +201,12 @@ cf_gtr_sfp0_pins: sfp0-pins { marvell,function = "gpio"; }; + cf_gtr_sfp1_pins: sfp1-pins { + /* sfp modabs, txdisable */ + marvell,pins = "mpp24", "mpp54"; + marvell,function = "gpio"; + }; + cf_gtr_spi1_cs_pins: spi1-cs-pins { marvell,pins = "mpp59"; marvell,function = "spi1";
@@ -273,7 +279,7 @@ pcie@3,0 { }; /* CON5 */ - sfp0: sfp { + sfp0: sfp-0 { compatible = "sff,sfp"; pinctrl-0 = <&cf_gtr_sfp0_pins>; pinctrl-names = "default";
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 5/5 arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
In reply to Josua MayerClearfog GTR has an official enclosure with labels for all interfaces. The "lan" ports on the 8-port switch in device-tree were numbered in reverse wrt. enclosure.
Update all device-tree labels to match.
--- .../dts/marvell/armada-385-clearfog-gtr-l8.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts +8 -8
@@ -31,49 +31,49 @@ ports { port@1 { reg = <1>; - label = "lan8"; + label = "lan1"; phy-handle = <&switch0phy0>; }; port@2 { reg = <2>; - label = "lan7"; + label = "lan2"; phy-handle = <&switch0phy1>; }; port@3 { reg = <3>; - label = "lan6"; + label = "lan3"; phy-handle = <&switch0phy2>; }; port@4 { reg = <4>; - label = "lan5"; + label = "lan4"; phy-handle = <&switch0phy3>; }; port@5 { reg = <5>; - label = "lan4"; + label = "lan5"; phy-handle = <&switch0phy4>; }; port@6 { reg = <6>; - label = "lan3"; + label = "lan6"; phy-handle = <&switch0phy5>; }; port@7 { reg = <7>; - label = "lan2"; + label = "lan7"; phy-handle = <&switch0phy6>; }; port@8 { reg = <8>; - label = "lan1"; + label = "lan8"; phy-handle = <&switch0phy7>; };
Signature · 7 lines
2.35.3 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel