gpio: pmic-eic-sprd: Configure the bit corresponding to the EIC through offset

A bank PMIC EIC contains 16 EICs, and the operating registers are BIT0-BIT15, such as BIT0 of the register operated by EIC0. Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance will cause the configuration of other EICs to be affected when operating a certain EIC. In order to solve this problem, configure the bit corresponding to the EIC through offset.

Signed-off-by Wenhua Lin <[email protected]>

---
Change in V3:

(quoted diff) +0 -5

-Change title.
-Change commit message.
-Delete the modification of the two-dimensional array maintenance pmic eic,
 and add the corresponding bits to configure the eic according to the offset.
---
---
 drivers/gpio/gpio-pmic-eic-sprd.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

drivers/gpio/gpio-pmic-eic-sprd.c +10 -10

index 01c0fd0a9d8c..d9b228bea42e 100644
@@ -151,8 +151,8 @@ static void sprd_pmic_eic_irq_mask(struct irq_data *data)
        struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
        u32 offset = irqd_to_hwirq(data);
 
-       pmic_eic->reg[REG_IE] = 0;
-       pmic_eic->reg[REG_TRIG] = 0;
+       pmic_eic->reg[REG_IE] &= ~BIT(offset);
+       pmic_eic->reg[REG_TRIG] &= ~BIT(offset);
 
        gpiochip_disable_irq(chip, offset);
 }

@@ -165,8 +165,8 @@ static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
 
        gpiochip_enable_irq(chip, offset);
 
-       pmic_eic->reg[REG_IE] = 1;
-       pmic_eic->reg[REG_TRIG] = 1;
+       pmic_eic->reg[REG_IE] |= BIT(offset);
+       pmic_eic->reg[REG_TRIG] |= BIT(offset);
 }
 
 static int sprd_pmic_eic_irq_set_type(struct irq_data *data,

@@ -174,13 +174,14 @@ static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
 {
        struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
        struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
+       u32 offset = irqd_to_hwirq(data);
 
        switch (flow_type) {
        case IRQ_TYPE_LEVEL_HIGH:
-               pmic_eic->reg[REG_IEV] = 1;
+               pmic_eic->reg[REG_IEV] |= BIT(offset);
                break;
        case IRQ_TYPE_LEVEL_LOW:
-               pmic_eic->reg[REG_IEV] = 0;
+               pmic_eic->reg[REG_IEV] &= ~BIT(offset);
                break;
        case IRQ_TYPE_EDGE_RISING:
        case IRQ_TYPE_EDGE_FALLING:

@@ -222,15 +223,15 @@ static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
                        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
        } else {
                sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
-                                    pmic_eic->reg[REG_IEV]);
+                                    !!(pmic_eic->reg[REG_IEV] & BIT(offset)));
        }
 
        /* Set irq unmask */
        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
-                            pmic_eic->reg[REG_IE]);
+                            !!(pmic_eic->reg[REG_IE] & BIT(offset)));
        /* Generate trigger start pulse for debounce EIC */
        sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
-                            pmic_eic->reg[REG_TRIG]);
+                            !!(pmic_eic->reg[REG_TRIG] & BIT(offset)));
 
        mutex_unlock(&pmic_eic->buslock);
 }
--

2.17.1

A bank PMIC EIC contains 16 EICs, and the operating registers are BIT0-BIT15, such as BIT0 of the register operated by EIC0. Using the one-dimensional array reg[CACHE_NR_REGS] for maintenance will cause the configuration of other EICs to be affected when operating a certain EIC. In order to solve this problem, configure the bit corresponding to the EIC through offset.

Signed-off-by Wenhua Lin <[email protected]>

---
Change in V3: