dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible
Subsystems (3)
PATCH 1/2 dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible
Add TI SERDES control registers compatible. This is a region found in the TI AM65 CTRL_MMR0 register space[0]. Each instance is used to control a SERDES clock and lane select mux.
[0] https://www.ti.com/lit/pdf/spruid7
--- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/mfd/syscon.yaml +1 -0
@@ -73,6 +73,7 @@ properties: - rockchip,rv1126-qos - starfive,jh7100-sysmain - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl - const: syscon
Signature · 1 line
2.39.2
PATCH 2/2 arm64: dts: ti: k3-am65: Add full compatible to SerDes control nodes
This matches the binding for this register region which fixes a couple DTS check warnings.
While here trim the leading 0s from the "reg" definition.
--- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +4 -4
@@ -483,13 +483,13 @@ scm_conf: scm-conf@100000 { ranges = <0x0 0x0 0x00100000 0x1c000>; serdes0_clk: clock@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4080 0x4>; }; serdes1_clk: clock@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4090 0x4>; }; serdes_mux: mux-controller {
Signature · 1 line
2.39.2
Quoted 7 lines · Andrew Davis
Add TI SERDES control registers compatible. This is a region found in the TI AM65
CTRL_MMR0register space[0]. Each instance is used to control a SERDES clock and lane select mux.[0] https://www.ti.com/lit/pdf/spruid7
Signed-off-by Andrew Davis <[email protected]>
Best regards,
Krzysztof
Vignesh Raghavendra
maintainerQuoted 16 lines · Andrew Davis
Add TI SERDES control registers compatible. This is a region found in the TI AM65
CTRL_MMR0register space[0]. Each instance is used to control a SERDES clock and lane select mux.[0] https://www.ti.com/lit/pdf/spruid7
Signed-off-by Andrew Davis <[email protected]>--- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mfd/syscon.yaml +0
-0
Documentation/devicetree/bindings/mfd/syscon.yaml properties: · line 79
Quoted 7 lines
Documentation/devicetree/bindings/mfd/syscon.yaml +1
-0@@ -73,6 +73,7 @@ properties: - rockchip,rv1126-qos - starfive,jh7100-sysmain - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl - const: syscon
This needs to go via mfd tree (or at least need an ACK). Please cc appropriate maintainer (Lee Jones <[email protected]>). So, I recommended to split 2/2 out into separate series and post once this patch is merged.
Signature · 2 lines
Regards Vignesh
Quoted 24 lines · Vignesh Raghavendra
Quoted 21 lines · Andrew Davis
Add TI SERDES control registers compatible. This is a region found in the TI AM65
CTRL_MMR0register space[0]. Each instance is used to control a SERDES clock and lane select mux.[0] https://www.ti.com/lit/pdf/spruid7
Signed-off-by Andrew Davis <[email protected]>--- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/mfd/syscon.yaml +1
-0@@ -73,6 +73,7 @@ properties: - rockchip,rv1126-qos - starfive,jh7100-sysmain - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl
Quoted 7 lines
Documentation/devicetree/bindings/mfd/syscon.yaml properties: · line 79
Quoted 2 lines
Documentation/devicetree/bindings/mfd/syscon.yaml +0
-0- const: sysconThis needs to go via mfd tree (or at least need an ACK). Please cc appropriate maintainer (Lee Jones <[email protected]>). So, I recommended to split 2/2 out into separate series and post once this patch is merged.
Sure, will send this patch standalone, then post the dts changes later.
Andrew