PCI: dwc: Add common pme_turn_off message by using outbound iATU

Reserve space at end of first IORESOURCE_MEM window as message TLP MMIO window. This space's size is 'region_align'.

Set outbound ATU map memory write to send PCI message. So one MMIO write can trigger a PCI message, such as PME_Turn_Off.

Add common dwc_pme_turn_off() function.

Call dwc_pme_turn_off() to send out PME_Turn_Off message in general dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off() exist.

Signed-off-by Frank Li <[email protected]>

---
 drivers/pci/controller/dwc/pcie-designware-host.c | 93 ++++++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-designware.h      |  2 +
 2 files changed, 91 insertions(+), 4 deletions(-)

drivers/pci/controller/dwc/pcie-designware-host.c +25 -0

index 267687ab33cbc..5e83756492462 100644
@@ -393,6 +393,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
 	return 0;
 }
 
+static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct resource_entry *win;
+	struct resource *res;
+
+	win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+	if (win) {
+		res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
+		if (!res)
+			return;
+
+		/* Reserve last region_align block as message TLP space */
+		res->start = win->res->end - pci->region_align + 1;
+		res->end = win->res->end;
+		res->name = "msg";
+		res->flags = win->res->flags | IORESOURCE_BUSY;
+
+		if (!request_resource(win->res, res))
+			pp->msg_res = res;
+		else
+			devm_kfree(pci->dev, res);
+	}
+}
+
 int dw_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

drivers/pci/controller/dwc/pcie-designware-host.c +1 -0

+
 	ret = dw_pcie_edma_detect(pci);
 	if (ret)

drivers/pci/controller/dwc/pcie-designware-host.c +61 -4

 		goto err_free_msi;

@@ -536,6 +564,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 
 	dw_pcie_edma_remove(pci);
 
+	if (pp->msg_res) {
+		release_resource(pp->msg_res);
+		devm_kfree(pci->dev, pp->msg_res);
+	}
+
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
 

@@ -697,6 +730,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		atu.pci_addr = entry->res->start - entry->offset;
 		atu.size = resource_size(entry->res);
 
+		/* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */
+		if (pp->msg_res && pp->msg_res->parent == entry->res)
+			atu.size -= resource_size(pp->msg_res);
+
 		ret = dw_pcie_prog_outbound_atu(pci, &atu);
 		if (ret) {
 			dev_err(pci->dev, "Failed to set MEM range %pr\n",

@@ -728,6 +765,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
 			 pci->num_ob_windows);
 
+	pp->msg_atu_index = i;
+
 	i = 0;
 	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
 		if (resource_type(entry->res) != IORESOURCE_MEM)

@@ -833,11 +872,54 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
 
+/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */
+static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
+{
+	struct dw_pcie_ob_atu_cfg atu = { 0 };
+	void __iomem *m;
+	int ret;
+
+	if (pci->num_ob_windows <= pci->pp.msg_atu_index)
+		return -EINVAL;
+
+	if (!pci->pp.msg_res)
+		return -EINVAL;
+
+	atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
+	atu.routing = PCIE_MSG_TYPE_R_BC;
+	atu.type = PCIE_ATU_TYPE_MSG;
+	atu.size = resource_size(pci->pp.msg_res);
+	atu.index = pci->pp.msg_atu_index;
+
+	if (!atu.size) {
+		dev_dbg(pci->dev,
+			"atu memory map windows is zero, please check 'msg' reg in dts\n");
+		return -ENOMEM;
+	}
+
+	atu.cpu_addr = pci->pp.msg_res->start;
+
+	ret = dw_pcie_prog_outbound_atu(pci, &atu);
+	if (ret)
+		return ret;
+
+	m = ioremap(atu.cpu_addr, pci->region_align);
+	if (!m)
+		return -ENOMEM;
+
+	/* A dummy write is converted to a Msg TLP */
+	writel(0, m);
+
+	iounmap(m);
+
+	return 0;
+}
+
 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 {
 	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
-	int ret;
+	int ret = 0;
 
 	/*
 	 * If L1SS is supported, then do not put the link into L2 as some

@@ -849,10 +931,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 	if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
 		return 0;
 
-	if (!pci->pp.ops->pme_turn_off)
-		return 0;
+	if (pci->pp.ops->pme_turn_off)
+		pci->pp.ops->pme_turn_off(&pci->pp);
+	else
+		ret = dw_pcie_pme_turn_off(pci);
 
-	pci->pp.ops->pme_turn_off(&pci->pp);
+	if (ret)
+		return ret;
 
 	ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
 				PCIE_PME_TO_L2_TIMEOUT_US/10,

drivers/pci/controller/dwc/pcie-designware.h +2 -0

index 703b50bc5e0f1..9e6076aa4c850 100644
@@ -341,6 +341,8 @@ struct dw_pcie_rp {
 	struct pci_host_bridge  *bridge;
 	raw_spinlock_t		lock;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
+	int			msg_atu_index;
+	struct resource		*msg_res;
 };
 
 struct dw_pcie_ep_ops {

Signature · 2 lines

-- 
2.34.1

Quoted 56 lines · Frank Li

Reserve space at end of first IORESOURCE_MEM window as message TLP MMIO window. This space's size is 'region_align'.

Set outbound ATU map memory write to send PCI message. So one MMIO write can trigger a PCI message, such as PME_Turn_Off.

Add common dwc_pme_turn_off() function.

Call dwc_pme_turn_off() to send out PME_Turn_Off message in general dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off() exist.

Signed-off-by Frank Li <[email protected]>

---
 drivers/pci/controller/dwc/pcie-designware-host.c | 93 ++++++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-designware.h      |  2 +
 2 files changed, 91 insertions(+), 4 deletions(-)

drivers/pci/controller/dwc/pcie-designware-host.c +25 -0

index 267687ab33cbc..5e83756492462 100644
@@ -393,6 +393,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
 	return 0;
 }
 
+static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct resource_entry *win;
+	struct resource *res;
+
+	win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+	if (win) {
+		res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
+		if (!res)
+			return;
+
+		/* Reserve last region_align block as message TLP space */
+		res->start = win->res->end - pci->region_align + 1;
+		res->end = win->res->end;
+		res->name = "msg";
+		res->flags = win->res->flags | IORESOURCE_BUSY;
+
+		if (!request_resource(win->res, res))
+			pp->msg_res = res;
+		else
+			devm_kfree(pci->dev, res);
+	}
+}
+
 int dw_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

@@ -479,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 

drivers/pci/controller/dwc/pcie-designware-host.c int dw_pcie_host_init(struct dw_pcie_rp *pp) · line 508

Quoted 5 lines

drivers/pci/controller/dwc/pcie-designware-host.c +2 -0

 	dw_pcie_iatu_detect(pci);
 
 
+	/* Need call after dw_pcie_iatu_detect() before dw_pcie_setup_rc() */
+	dw_pcie_host_request_msg_tlp_res(pp);

This may cause regressions for instance if the outbound memory window is small and is fully dedicated for some device like VGA/GPU/etc.

Why not to use a new ranges-based mapping as we discussed earlier:
https://lore.kernel.org/linux-pci/20240214061412.GB4618@thinkpad/
?

I know it might be troublesome but still it would be much better and more portable across various platforms.

Bjorn, Lorenzo, Krzysztofm Rob could you please follow the link above and give your opinion about the solution suggested there?

-Serge(y)

Quoted 127 lines

drivers/pci/controller/dwc/pcie-designware-host.c +1 -0

+
 	ret = dw_pcie_edma_detect(pci);
 	if (ret)

drivers/pci/controller/dwc/pcie-designware-host.c +61 -4

 		goto err_free_msi;

@@ -536,6 +564,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 
 	dw_pcie_edma_remove(pci);
 
+	if (pp->msg_res) {
+		release_resource(pp->msg_res);
+		devm_kfree(pci->dev, pp->msg_res);
+	}
+
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
 

@@ -697,6 +730,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		atu.pci_addr = entry->res->start - entry->offset;
 		atu.size = resource_size(entry->res);
 
+		/* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */
+		if (pp->msg_res && pp->msg_res->parent == entry->res)
+			atu.size -= resource_size(pp->msg_res);
+
 		ret = dw_pcie_prog_outbound_atu(pci, &atu);
 		if (ret) {
 			dev_err(pci->dev, "Failed to set MEM range %pr\n",

@@ -728,6 +765,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
 			 pci->num_ob_windows);
 
+	pp->msg_atu_index = i;
+
 	i = 0;
 	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
 		if (resource_type(entry->res) != IORESOURCE_MEM)

@@ -833,11 +872,54 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
 
+/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */
+static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
+{
+	struct dw_pcie_ob_atu_cfg atu = { 0 };
+	void __iomem *m;
+	int ret;
+
+	if (pci->num_ob_windows <= pci->pp.msg_atu_index)
+		return -EINVAL;
+
+	if (!pci->pp.msg_res)
+		return -EINVAL;
+
+	atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
+	atu.routing = PCIE_MSG_TYPE_R_BC;
+	atu.type = PCIE_ATU_TYPE_MSG;
+	atu.size = resource_size(pci->pp.msg_res);
+	atu.index = pci->pp.msg_atu_index;
+
+	if (!atu.size) {
+		dev_dbg(pci->dev,
+			"atu memory map windows is zero, please check 'msg' reg in dts\n");
+		return -ENOMEM;
+	}
+
+	atu.cpu_addr = pci->pp.msg_res->start;
+
+	ret = dw_pcie_prog_outbound_atu(pci, &atu);
+	if (ret)
+		return ret;
+
+	m = ioremap(atu.cpu_addr, pci->region_align);
+	if (!m)
+		return -ENOMEM;
+
+	/* A dummy write is converted to a Msg TLP */
+	writel(0, m);
+
+	iounmap(m);
+
+	return 0;
+}
+
 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 {
 	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
-	int ret;
+	int ret = 0;
 
 	/*
 	 * If L1SS is supported, then do not put the link into L2 as some

@@ -849,10 +931,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 	if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
 		return 0;
 
-	if (!pci->pp.ops->pme_turn_off)
-		return 0;
+	if (pci->pp.ops->pme_turn_off)
+		pci->pp.ops->pme_turn_off(&pci->pp);
+	else
+		ret = dw_pcie_pme_turn_off(pci);
 
-	pci->pp.ops->pme_turn_off(&pci->pp);
+	if (ret)
+		return ret;
 
 	ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
 				PCIE_PME_TO_L2_TIMEOUT_US/10,

drivers/pci/controller/dwc/pcie-designware.h +2 -0

index 703b50bc5e0f1..9e6076aa4c850 100644
@@ -341,6 +341,8 @@ struct dw_pcie_rp {
 	struct pci_host_bridge  *bridge;
 	raw_spinlock_t		lock;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
+	int			msg_atu_index;
+	struct resource		*msg_res;
 };
 
 struct dw_pcie_ep_ops {

Signature · 2 lines

-- 
2.34.1

Quoted 57 lines · Serge Semin

Quoted 56 lines · Frank Li

Reserve space at end of first IORESOURCE_MEM window as message TLP MMIO window. This space's size is 'region_align'.

Set outbound ATU map memory write to send PCI message. So one MMIO write can trigger a PCI message, such as PME_Turn_Off.

Add common dwc_pme_turn_off() function.

Call dwc_pme_turn_off() to send out PME_Turn_Off message in general dw_pcie_suspend_noirq() if there are not platform callback pme_turn_off() exist.

Signed-off-by Frank Li <[email protected]>

---
 drivers/pci/controller/dwc/pcie-designware-host.c | 93 ++++++++++++++++++++++-
 drivers/pci/controller/dwc/pcie-designware.h      |  2 +
 2 files changed, 91 insertions(+), 4 deletions(-)

drivers/pci/controller/dwc/pcie-designware-host.c +25 -0

index 267687ab33cbc..5e83756492462 100644
@@ -393,6 +393,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
 	return 0;
 }
 
+static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct resource_entry *win;
+	struct resource *res;
+
+	win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+	if (win) {
+		res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
+		if (!res)
+			return;
+
+		/* Reserve last region_align block as message TLP space */
+		res->start = win->res->end - pci->region_align + 1;
+		res->end = win->res->end;
+		res->name = "msg";
+		res->flags = win->res->flags | IORESOURCE_BUSY;
+
+		if (!request_resource(win->res, res))
+			pp->msg_res = res;
+		else
+			devm_kfree(pci->dev, res);
+	}
+}
+
 int dw_pcie_host_init(struct dw_pcie_rp *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

@@ -479,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 

Quoted 8 lines

drivers/pci/controller/dwc/pcie-designware-host.c int dw_pcie_host_init(struct dw_pcie_rp *pp) · line 508

Quoted 5 lines

drivers/pci/controller/dwc/pcie-designware-host.c +2 -0

 	dw_pcie_iatu_detect(pci);
 
 
+	/* Need call after dw_pcie_iatu_detect() before dw_pcie_setup_rc() */
+	dw_pcie_host_request_msg_tlp_res(pp);

This may cause regressions for instance if the outbound memory window is small and is fully dedicated for some device like VGA/GPU/etc.

There are host memory map windows, which are quite big. It will be too small if only because one page size windows less.

Look like it is impossible to dedicated to one device, all pcie devices (VGA/GPU) should go through standard pcie probe flow, the bar will be allocated from bridge windows space.

Quoted 4 lines

Why not to use a new ranges-based mapping as we discussed earlier:
https://lore.kernel.org/linux-pci/20240214061412.GB4618@thinkpad/
?

If driver can auto alloc from known range, why need static defined in dts files.

static alloc can't resolve small outbound memory windows problem. It may disable this feature.

Quoted 136 lines

I know it might be troublesome but still it would be much better and more portable across various platforms.

Bjorn, Lorenzo, Krzysztofm Rob could you please follow the link above and give your opinion about the solution suggested there?

-Serge(y)

Quoted 127 lines

drivers/pci/controller/dwc/pcie-designware-host.c +1 -0

+
 	ret = dw_pcie_edma_detect(pci);
 	if (ret)

drivers/pci/controller/dwc/pcie-designware-host.c +61 -4

 		goto err_free_msi;

@@ -536,6 +564,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp)
 
 	dw_pcie_edma_remove(pci);
 
+	if (pp->msg_res) {
+		release_resource(pp->msg_res);
+		devm_kfree(pci->dev, pp->msg_res);
+	}
+
 	if (pp->has_msi_ctrl)
 		dw_pcie_free_msi(pp);
 

@@ -697,6 +730,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		atu.pci_addr = entry->res->start - entry->offset;
 		atu.size = resource_size(entry->res);
 
+		/* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */
+		if (pp->msg_res && pp->msg_res->parent == entry->res)
+			atu.size -= resource_size(pp->msg_res);
+
 		ret = dw_pcie_prog_outbound_atu(pci, &atu);
 		if (ret) {
 			dev_err(pci->dev, "Failed to set MEM range %pr\n",

@@ -728,6 +765,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
 			 pci->num_ob_windows);
 
+	pp->msg_atu_index = i;
+
 	i = 0;
 	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
 		if (resource_type(entry->res) != IORESOURCE_MEM)

@@ -833,11 +872,54 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 }
 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
 
+/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */
+static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
+{
+	struct dw_pcie_ob_atu_cfg atu = { 0 };
+	void __iomem *m;
+	int ret;
+
+	if (pci->num_ob_windows <= pci->pp.msg_atu_index)
+		return -EINVAL;
+
+	if (!pci->pp.msg_res)
+		return -EINVAL;
+
+	atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
+	atu.routing = PCIE_MSG_TYPE_R_BC;
+	atu.type = PCIE_ATU_TYPE_MSG;
+	atu.size = resource_size(pci->pp.msg_res);
+	atu.index = pci->pp.msg_atu_index;
+
+	if (!atu.size) {
+		dev_dbg(pci->dev,
+			"atu memory map windows is zero, please check 'msg' reg in dts\n");
+		return -ENOMEM;
+	}
+
+	atu.cpu_addr = pci->pp.msg_res->start;
+
+	ret = dw_pcie_prog_outbound_atu(pci, &atu);
+	if (ret)
+		return ret;
+
+	m = ioremap(atu.cpu_addr, pci->region_align);
+	if (!m)
+		return -ENOMEM;
+
+	/* A dummy write is converted to a Msg TLP */
+	writel(0, m);
+
+	iounmap(m);
+
+	return 0;
+}
+
 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 {
 	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
-	int ret;
+	int ret = 0;
 
 	/*
 	 * If L1SS is supported, then do not put the link into L2 as some

@@ -849,10 +931,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 	if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
 		return 0;
 
-	if (!pci->pp.ops->pme_turn_off)
-		return 0;
+	if (pci->pp.ops->pme_turn_off)
+		pci->pp.ops->pme_turn_off(&pci->pp);
+	else
+		ret = dw_pcie_pme_turn_off(pci);
 
-	pci->pp.ops->pme_turn_off(&pci->pp);
+	if (ret)
+		return ret;
 
 	ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
 				PCIE_PME_TO_L2_TIMEOUT_US/10,

drivers/pci/controller/dwc/pcie-designware.h +2 -0

index 703b50bc5e0f1..9e6076aa4c850 100644
@@ -341,6 +341,8 @@ struct dw_pcie_rp {
 	struct pci_host_bridge  *bridge;
 	raw_spinlock_t		lock;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
+	int			msg_atu_index;
+	struct resource		*msg_res;
 };
 
 struct dw_pcie_ep_ops {

Signature · 2 lines

-- 
2.34.1

Involve an new and common mathod to send pme_turn_off() message. Previously pme_turn_off() implement by platform related special register to trigge it.

But Yoshihiro give good idea by using iATU to send out message. Previously Yoshihiro provide patches to raise INTx message by dummy write to outbound iATU.

Use similar mathod to send out pme_turn_off message.

Previous two patches is picked from Yoshihiro' big patch serialise.
PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
PCI: Add INTx Mechanism Messages macros

PCI: Add PME_TURN_OFF message macro
dt-bindings: PCI: dwc: Add 'msg" register region, Add "msg" region to use to map PCI msg.

PCI: dwc: Add common pme_turn_off message method
Using common pme_turn_off() message if platform have not define their.

Signed-off-by Frank Li <[email protected]>

---
Changes in v4:
- Remove dt-binding patch. Needn't change any dts file and binding doc. Reserve a region at end of first IORESOURCE_MEM window by call request_resource(). So PCIe stack will not use this reserve region to any
PCIe devices.
I tested it by reserve at begin of IORESOURCE_MEM window. PCIe stack
will skip it as expection.

Fixed a issue, forget set iATU index when sent PME_turn_off.

- Link to v3: https://lore.kernel.org/r/[email protected]

Changes in v3:
- fix 'MSG"
- Add pcie spec ref in head file
- using function name dw_pci_pme_turn_off()
- Using PCIE_ prefix macro
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Add my sign off at PCI: dwc: Add outbound MSG TLPs support
- Add Bjorn review tag at Add INTx Mechanism Messages macros
- using PME_Turn_Off match PCIe spec
- ref to pcie spec v6.1
- using section number.

- Link to v1: https://lore.kernel.org/r/[email protected]

---
Frank Li (2):
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro
PCI: dwc: Add common send PME_Turn_Off message method

Yoshihiro Shimoda (3):
PCI: Add INTx Mechanism Messages macros
PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
PCI: dwc: Add outbound MSG TLPs support

 drivers/pci/controller/dwc/pcie-designware-ep.c   |  21 ++--
 drivers/pci/controller/dwc/pcie-designware-host.c | 145 +++++++++++++++++++---
 drivers/pci/controller/dwc/pcie-designware.c      |  54 ++++----
 drivers/pci/controller/dwc/pcie-designware.h      |  21 +++-
 drivers/pci/pci.h                                 |  20 +++
 5 files changed, 197 insertions(+), 64 deletions(-)

---
base-commit: e08fc59eee9991afa467d406d684d46d543299a9
change-id: 20240130-pme_msg-dd2d81ee9886

Best regards,

Signature · 1 line

Frank Li <[email protected]>

Quoted 3 lines · Frank Li

Involve an new and common mathod to send pme_turn_off() message. Previously pme_turn_off() implement by platform related special register to trigge it.

@mani:l

Do you have chance look this patches. Actually other patches
already reviewed. Only missed

PCI: dwc: Add common send PME_Turn_Off message method
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro

This patch will reduce customer's PME_Turn_off method. Many code
can be cleaned after this.

Frank Li

Quoted 72 lines

But Yoshihiro give good idea by using iATU to send out message. Previously Yoshihiro provide patches to raise INTx message by dummy write to outbound iATU.

Use similar mathod to send out pme_turn_off message.

Previous two patches is picked from Yoshihiro' big patch serialise.
PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
PCI: Add INTx Mechanism Messages macros

PCI: Add PME_TURN_OFF message macro
dt-bindings: PCI: dwc: Add 'msg" register region, Add "msg" region to use to map PCI msg.

PCI: dwc: Add common pme_turn_off message method
Using common pme_turn_off() message if platform have not define their.

Signed-off-by Frank Li <[email protected]>

---
Changes in v4:
- Remove dt-binding patch. Needn't change any dts file and binding doc. Reserve a region at end of first IORESOURCE_MEM window by call request_resource(). So PCIe stack will not use this reserve region to any
PCIe devices.
I tested it by reserve at begin of IORESOURCE_MEM window. PCIe stack
will skip it as expection.

Fixed a issue, forget set iATU index when sent PME_turn_off.

- Link to v3: https://lore.kernel.org/r/[email protected]

Changes in v3:
- fix 'MSG"
- Add pcie spec ref in head file
- using function name dw_pci_pme_turn_off()
- Using PCIE_ prefix macro
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Add my sign off at PCI: dwc: Add outbound MSG TLPs support
- Add Bjorn review tag at Add INTx Mechanism Messages macros
- using PME_Turn_Off match PCIe spec
- ref to pcie spec v6.1
- using section number.

- Link to v1: https://lore.kernel.org/r/[email protected]

---
Frank Li (2):
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro
PCI: dwc: Add common send PME_Turn_Off message method

Yoshihiro Shimoda (3):
PCI: Add INTx Mechanism Messages macros
PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
PCI: dwc: Add outbound MSG TLPs support

 drivers/pci/controller/dwc/pcie-designware-ep.c   |  21 ++--
 drivers/pci/controller/dwc/pcie-designware-host.c | 145 +++++++++++++++++++---
 drivers/pci/controller/dwc/pcie-designware.c      |  54 ++++----
 drivers/pci/controller/dwc/pcie-designware.h      |  21 +++-
 drivers/pci/pci.h                                 |  20 +++
 5 files changed, 197 insertions(+), 64 deletions(-)

---
base-commit: e08fc59eee9991afa467d406d684d46d543299a9
change-id: 20240130-pme_msg-dd2d81ee9886

Best regards,

Signature · 1 line

Frank Li <[email protected]>

Quoted 13 lines · Frank Li

Quoted 3 lines · Frank Li

Involve an new and common mathod to send pme_turn_off() message. Previously pme_turn_off() implement by platform related special register to trigge it.

@mani:l

Do you have chance look this patches. Actually other patches
already reviewed. Only missed

PCI: dwc: Add common send PME_Turn_Off message method
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro

Quoted 2 lines

This patch will reduce customer's PME_Turn_off method. Many code
can be cleaned after this.

@mani and @lpieralisi

Do you have chance to look these?

Frank

Quoted 75 lines

Frank Li

Quoted 72 lines

But Yoshihiro give good idea by using iATU to send out message. Previously Yoshihiro provide patches to raise INTx message by dummy write to outbound iATU.

Use similar mathod to send out pme_turn_off message.

Previous two patches is picked from Yoshihiro' big patch serialise.
PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
PCI: Add INTx Mechanism Messages macros

PCI: Add PME_TURN_OFF message macro
dt-bindings: PCI: dwc: Add 'msg" register region, Add "msg" region to use to map PCI msg.

PCI: dwc: Add common pme_turn_off message method
Using common pme_turn_off() message if platform have not define their.

Signed-off-by Frank Li <[email protected]>

---
Changes in v4:
- Remove dt-binding patch. Needn't change any dts file and binding doc. Reserve a region at end of first IORESOURCE_MEM window by call request_resource(). So PCIe stack will not use this reserve region to any
PCIe devices.
I tested it by reserve at begin of IORESOURCE_MEM window. PCIe stack
will skip it as expection.

Fixed a issue, forget set iATU index when sent PME_turn_off.

- Link to v3: https://lore.kernel.org/r/[email protected]

Changes in v3:
- fix 'MSG"
- Add pcie spec ref in head file
- using function name dw_pci_pme_turn_off()
- Using PCIE_ prefix macro
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Add my sign off at PCI: dwc: Add outbound MSG TLPs support
- Add Bjorn review tag at Add INTx Mechanism Messages macros
- using PME_Turn_Off match PCIe spec
- ref to pcie spec v6.1
- using section number.

- Link to v1: https://lore.kernel.org/r/[email protected]

---
Frank Li (2):
PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro
PCI: dwc: Add common send PME_Turn_Off message method

Yoshihiro Shimoda (3):
PCI: Add INTx Mechanism Messages macros
PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
PCI: dwc: Add outbound MSG TLPs support

 drivers/pci/controller/dwc/pcie-designware-ep.c   |  21 ++--
 drivers/pci/controller/dwc/pcie-designware-host.c | 145 +++++++++++++++++++---
 drivers/pci/controller/dwc/pcie-designware.c      |  54 ++++----
 drivers/pci/controller/dwc/pcie-designware.h      |  21 +++-
 drivers/pci/pci.h                                 |  20 +++
 5 files changed, 197 insertions(+), 64 deletions(-)

---
base-commit: e08fc59eee9991afa467d406d684d46d543299a9
change-id: 20240130-pme_msg-dd2d81ee9886

Best regards,

Signature · 1 line

Frank Li <[email protected]>