Add common1 region for AM62, AM62A & AM65x
Subsystems (6)
v2 cover Add common1 region for AM62, AM62A & AM65x
This adds DSS common1 region for respective SoCs supporting it.
Devarsh Thakkar (2):
dt-bindings: display: ti,am65x-dss: Add support for common1 region
arm64: dts: ti: Add common1 register space for AM62x, AM62A & AM65x
SoCs
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 4 files changed, 14 insertions(+), 8 deletions(-)
Signature · 1 line
2.34.1
PATCH v2 1/2 dt-bindings: display: ti,am65x-dss: Add support for common1 region
TI keystone display subsystem present in AM65 and other SoCs such as AM62 support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1].
The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region.
This adds binding for "common1" register region too as supported by the hardware.
[1]:
AM62x TRM:
https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers)
AM65x TRM:
https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers)
AM62A TRM:
https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9.1 DSS Registers)
---
V2: Add Acked-by tag
--- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +5 -2
@@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items:
@@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items:
@@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>,
Signature · 1 line
2.34.1
Vignesh Raghavendra
maintainerRe: [PATCH v2 1/2] dt-bindings: display: ti,am65x-dss: Add support for common1 region
Quoted 19 lines · Devarsh Thakkar
TI keystone display subsystem present in AM65 and other SoCs such as AM62 support two separate register spaces namely "common" and "common1" which can be used by two separate hosts to program the display controller as described in respective Technical Reference Manuals [1].
The common1 register space has similar set of configuration registers as supported in common register space except the global configuration registers which are exclusive to common region.
This adds binding for "common1" register region too as supported by the hardware.
[1]:
AM62x TRM:
https://www.ti.com/lit/pdf/spruiv7 (Section 14.8.9.1 DSS Registers)AM65x TRM:
https://www.ti.com/lit/pdf/spruid7 (Section 12.6.5 DSS Registers)
Quoted 6 lines
AM62A TRM:
https://www.ti.com/lit/pdf/spruj16 (Section 14.9.9.1 DSS Registers)Signed-off-by Devarsh Thakkar <[email protected]>Acked-by Conor Dooley <[email protected]>---
I guess all AM65/62/62a DSS variants always had this common1 reg region but wasn't captured in the binding? If so, then this looks like a bug in the original adding this yaml and as such should have Fixes: tag and so should DT patch (patch 2/2)
Quoted 38 lines
V2: Add Acked-by tag
--- .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +5
-2@@ -37,6 +37,7 @@ properties: - description: OVR2 overlay manager for vp2 - description: VP1 video port 1 - description: VP2 video port 2 + - description: common1 DSS register area reg-names: items:@@ -47,6 +48,7 @@ properties: - const: ovr2 - const: vp1 - const: vp2 + - const: common1 clocks: items:@@ -147,9 +149,10 @@ examples: <0x04a07000 0x1000>, /* ovr1 */ <0x04a08000 0x1000>, /* ovr2 */ <0x04a0a000 0x1000>, /* vp1 */ - <0x04a0b000 0x1000>; /* vp2 */ + <0x04a0b000 0x1000>, /* vp2 */ + <0x04a01000 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 67 1>,
Signature · 2 lines
Regards Vignesh
PATCH v2 2/2 arm64: dts: ti: Add common1 register space for AM62x, AM62A & AM65x SoCs
In reply to Devarsh ThakkarThis adds common1 register space for AM62x, AM62A and AM65x SoC's which are using TI's Keystone display hardware and supporting it as described in Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
---
V2: Add common1 region for AM62A SoC too
--- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/ti/k3-am62-main.dtsi +3 -2
@@ -779,9 +779,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&dss_vp1_clk>,
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +3 -2
@@ -994,9 +994,10 @@ dss: dss@30200000 { <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ - <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 186 6>, <&k3_clks 186 0>,
arch/arm64/boot/dts/ti/k3-am65-main.dtsi +3 -2
@@ -991,9 +991,10 @@ dss: dss@4a00000 { <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + <0x0 0x04a0b000 0x0 0x1000>, /* vp2 */ + <0x0 0x04a01000 0x0 0x1000>; /* common1 */ reg-names = "common", "vidl1", "vid", - "ovr1", "ovr2", "vp1", "vp2"; + "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
Signature · 1 line
2.34.1