memory: tegra: Skip restricted register access from Guest
v3 cover memory: tegra: Skip restricted register access from Guest
MC SID and Broadbast channel register access is restricted for Guest VM. But the Tegra MC driver is considering both these regions as mandatory and causes error on access. Change that to consider both the regions as optional in SoC's from Tegra186 onwards. Then skip access to the restricted registers from Guest if its region is not present in Guest DT and hence not mapped.
Previously, the solution in [1] was not accepted. Now, handled the problem with this alternate solution.
---
v2[2] -> v3:
- fix the yaml error.
- add null check for ch_regs in mc_ch_readl() causing error in old SoC's
- remove unused populate label reported by kernel test robot.
- fix existing compile warning about length of name in tegra186_mc_probe.
v1[1] -> v2:
- consider broadcast channel registers also as restricted along with sid
- make sid and broadcast regions optional and access if present in dt.
- update the yaml file.
Sumit Gupta (2):
dt-bindings: make sid and broadcast reg optional
memory: tegra: make sid and broadcast regions optional
.../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- drivers/memory/tegra/mc.c | 9 +- drivers/memory/tegra/mc.h | 22 +++-- drivers/memory/tegra/tegra186.c | 25 ++--- 4 files changed, 82 insertions(+), 69 deletions(-)
[1]https://lore.kernel.org/lkml/[email protected]/ [2]https://lore.kernel.org/lkml/[email protected]/
Signature · 1 line
2.17.1
PATCH v3 1/2 dt-bindings: make sid and broadcast reg optional
MC SID and Broadbast channel register access is restricted for Guest VM. Make both the regions as optional for SoC's from Tegra186 onwards. Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +49 -46
@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:
@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 - if: properties:
@@ -165,29 +166,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 - if: properties:
@@ -196,29 +198,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 additionalProperties: false
Signature · 1 line
2.17.1
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 35 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +2
-5@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +7
-3- - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3
I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
This does not even make sid/broadcast optional, but ch0!
Best regards,
Krzysztof
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sid
Quoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Thierry
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +39 -49
@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:
@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:
@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: true + + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: true - if: properties:
@@ -196,29 +193,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: true + + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: true additionalProperties: false
--- >8 ---
The one restriction that it has is that "sid" and "broadcast" must be optional together. So you can't have just "sid" or "broadcast", but they either must both be there, or they must both not be there.
I suppose we could technically make that work by adding more alternatives, but perhaps it can be avoided for sanity?
Thierry
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 155 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +16
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items:
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 10 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +10
-0+ enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: true + + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: true
No, because order is strict.
...
Quoted 5 lines
The one restriction that it has is that "sid" and "broadcast" must be optional together. So you can't have just "sid" or "broadcast", but they either must both be there, or they must both not be there.
This must be explained in commit msg.
Best regards,
Krzysztof
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 160 lines · Krzysztof Kozlowski
Quoted 159 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +20
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: true
Quoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +6
-0+ + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: trueNo, because order is strict.
Why? I realize that prior to this the order was indeed strict and it's common to have these listed in strict order in the DTS files. However, this is an arbitrary restriction that was introduced in the patch that added reg-names. However, */*-names properties have always assumed the ordering to be non-strict because each entry from the * property gets matched up with the corresponding entry in the *-names property, so the ordering is completely irrelevant.
Thierry
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 170 lines · Thierry Reding
Quoted 160 lines · Krzysztof Kozlowski
Quoted 159 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +20
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: trueQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +6
-0+ + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: trueNo, because order is strict.
Quoted 1 line
Why? I realize that prior to this the order was indeed strict and it's
That's the policy for entire Devicetree. I said why in other email:
because any bindings consumer can take it via indices.
Quoted 6 lines
common to have these listed in strict order in the DTS files. However, this is an arbitrary restriction that was introduced in the patch that added reg-names. However, */*-names properties have always assumed the ordering to be non-strict because each entry from the * property gets matched up with the corresponding entry in the *-names property, so the ordering is completely irrelevant.
This was raised so many times... reg-names is just a helper. It does not change the fact that order should be strict and if binding defined the order, it is an ABI.
Best regards,
Krzysztof
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 183 lines · Krzysztof Kozlowski
Quoted 170 lines · Thierry Reding
Quoted 160 lines · Krzysztof Kozlowski
Quoted 159 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +20
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: trueQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +6
-0+ + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: trueNo, because order is strict.
Quoted 1 line
Why? I realize that prior to this the order was indeed strict and it's
That's the policy for entire Devicetree. I said why in other email:
because any bindings consumer can take it via indices.Quoted 6 lines
common to have these listed in strict order in the DTS files. However, this is an arbitrary restriction that was introduced in the patch that added reg-names. However, */*-names properties have always assumed the ordering to be non-strict because each entry from the * property gets matched up with the corresponding entry in the *-names property, so the ordering is completely irrelevant.
Quoted 3 lines
This was raised so many times... reg-names is just a helper. It does not change the fact that order should be strict and if binding defined the order, it is an ABI.
Sorry, but that's not how we've dealt with this in the past. Even though this was now ten or more years ago, I distinctly recall that when we started adding these *-names properties and at the time it was very much implied that the order didn't matter.
The only use-case that I know of where order was always meant to matter is backwards-compatibility for devices that used to have a single entry (hence drivers couldn't rely on *-names to resolve the index) and then had additional entries added. The *-names entry for that previously single entry would now obviously have to always be first in the list to preserve backwards-compatibility.
Besides, if reg-names was really only a helper, then it would also be completely redundant. Many device tree bindings have *-names properties marked as "required" precisely because of the role that they serve.
Thierry
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 184 lines · Thierry Reding
Quoted 183 lines · Krzysztof Kozlowski
Quoted 170 lines · Thierry Reding
Quoted 160 lines · Krzysztof Kozlowski
Quoted 159 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +20
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: trueQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +6
-0+ + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: trueNo, because order is strict.
Quoted 1 line
Why? I realize that prior to this the order was indeed strict and it's
That's the policy for entire Devicetree. I said why in other email:
because any bindings consumer can take it via indices.Quoted 6 lines
common to have these listed in strict order in the DTS files. However, this is an arbitrary restriction that was introduced in the patch that added reg-names. However, */*-names properties have always assumed the ordering to be non-strict because each entry from the * property gets matched up with the corresponding entry in the *-names property, so the ordering is completely irrelevant.
Quoted 8 lines
Quoted 3 lines
This was raised so many times... reg-names is just a helper. It does not change the fact that order should be strict and if binding defined the order, it is an ABI.
Sorry, but that's not how we've dealt with this in the past. Even though this was now ten or more years ago, I distinctly recall that when we started adding these *-names properties and at the time it was very much implied that the order didn't matter.
Then you added it wrong and Rob was expressing the purpose of names multiple times. The names were for cases when you could not determine the order.
The strict order was repeated so many times in the mailing list, I lost track.
Quoted 10 lines
The only use-case that I know of where order was always meant to matter is backwards-compatibility for devices that used to have a single entry (hence drivers couldn't rely on *-names to resolve the index) and then had additional entries added. The *-names entry for that previously single entry would now obviously have to always be first in the list to preserve backwards-compatibility.
Besides, if reg-names was really only a helper, then it would also be completely redundant. Many device tree bindings have *-names properties marked as "required" precisely because of the role that they serve.
For most of the cases, so ones which do not have flexible order, it is redundant and for that reason Qualcomm has been switching away from xxx-names in several drivers.
However it is not entirely redundant, because it allows bindings consumers to choose either index or name. Both are ABI, when documented in the binding with strict order.
https://lore.kernel.org/all/CAL_JsqJSYAsotjzvOUy_f7ZRfsSrfZyuEzq7eRwwKk12FBgxYg@mail.gmail.com/
Best regards,
Krzysztof
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
Quoted 194 lines · Krzysztof Kozlowski
Quoted 184 lines · Thierry Reding
Quoted 183 lines · Krzysztof Kozlowski
Quoted 170 lines · Thierry Reding
Quoted 160 lines · Krzysztof Kozlowski
Quoted 159 lines · Thierry Reding
Quoted 66 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
Quoted 1 line
This does not even make sid/broadcast optional, but ch0!
Quoted 7 lines
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +20
-29@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -146,17 +146,21 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 6 description: 5 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 6 + + - items: + enum: [ ch0, ch1, ch2, ch3 ] + uniqueItems: true + minItems: 4 - if: properties:@@ -165,29 +169,22 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: - items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + anyOf: + - items: + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ] + minItems: 18 + uniqueItems: trueQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 187
Quoted 6 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +6
-0+ + - items: + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10, + ch11, ch12, ch13, ch14, ch15 ] + minItems: 16 + uniqueItems: trueNo, because order is strict.
Quoted 1 line
Why? I realize that prior to this the order was indeed strict and it's
That's the policy for entire Devicetree. I said why in other email:
because any bindings consumer can take it via indices.Quoted 6 lines
common to have these listed in strict order in the DTS files. However, this is an arbitrary restriction that was introduced in the patch that added reg-names. However, */*-names properties have always assumed the ordering to be non-strict because each entry from the * property gets matched up with the corresponding entry in the *-names property, so the ordering is completely irrelevant.
Quoted 8 lines
Quoted 3 lines
This was raised so many times... reg-names is just a helper. It does not change the fact that order should be strict and if binding defined the order, it is an ABI.
Sorry, but that's not how we've dealt with this in the past. Even though this was now ten or more years ago, I distinctly recall that when we started adding these *-names properties and at the time it was very much implied that the order didn't matter.
Quoted 6 lines
Then you added it wrong and Rob was expressing the purpose of names multiple times. The names were for cases when you could not determine the order.
The strict order was repeated so many times in the mailing list, I lost track.
Sorry, but this isn't true. Perhaps the device tree maintainers' stance on this has changed over the years, but don't go around telling people that they did things wrongly when all they were doing was follow what was considered best practice at the time.
Quoted 15 lines
Quoted 10 lines
The only use-case that I know of where order was always meant to matter is backwards-compatibility for devices that used to have a single entry (hence drivers couldn't rely on *-names to resolve the index) and then had additional entries added. The *-names entry for that previously single entry would now obviously have to always be first in the list to preserve backwards-compatibility.
Besides, if reg-names was really only a helper, then it would also be completely redundant. Many device tree bindings have *-names properties marked as "required" precisely because of the role that they serve.
For most of the cases, so ones which do not have flexible order, it is redundant and for that reason Qualcomm has been switching away from xxx-names in several drivers.
Quoted 5 lines
However it is not entirely redundant, because it allows bindings consumers to choose either index or name. Both are ABI, when documented in the binding with strict order.
https://lore.kernel.org/all/CAL_JsqJSYAsotjzvOUy_f7ZRfsSrfZyuEzq7eRwwKk12FBgxYg@mail.gmail.com/
You do realize that "flexible order" is entirely defined by the bindings, right? There's nothing inherently strict in any of this. The bindings define any order (or lack thereof) that entries should be listed in and the drivers that implement the bindings need to respect whatever the bindings specify.
Thierry
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
In reply to Thierry RedingQuoted 59 lines · Thierry Reding
Quoted 49 lines · Krzysztof Kozlowski
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
Quoted 1 line
Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
Quoted 40 lines
Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>--- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-)Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +4
-8@@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts:@@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sidQuoted 8 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml allOf: · line 160
Quoted 5 lines
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +5
-0+ - broadcast + - ch0 + - ch1 + - ch2 + - ch3I understand why sid and broadcast are becoming optional, but why order of the rest is now fully flexible?
Quoted 4 lines
The reason why the order of the rest doesn't matter is because we have both reg and reg-names properties and so the order in which they appear in the list doesn't matter. The only thing that matters is that the entries of the reg and reg-names properties match.
No, that's not true. Client/implementation can pick up by indices and order always matters, at least as much as possible.
If the reason is "we have reg-names", then the answer is: no. That's not valid argument. The reason could be that entries are so fragmented/randomly distributed that order by indices is impossible.
Quoted 6 lines
Quoted 2 lines
This does not even make sid/broadcast optional, but ch0!
Yeah, this ends up making all entries optional, which isn't what we want. I don't know of a way to accurately express this in json-schema, though. Do you?
I think oneOf: with two cases. Depends what is exactly optional. The commit msg is quite poor here. I expect proper rationale and description of driver. Is sid optional? broadcast? Both? Any? And what does it mean optional? The address is reserved or address is not existing? Or maybe address is there, but can be ignored?
Quoted 6 lines
If not, then maybe we need to resort to something like this and also mention explicitly in some comment that it is sid and broadcast that are optional.
Thierry
Best regards,
Krzysztof
Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
In reply to Sumit GuptaQuoted 9 lines · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM. Make both the regions as optional for SoC's from Tegra186 onwards. Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT.
Suggested-by Thierry Reding <[email protected]>Signed-off-by Sumit Gupta <[email protected]>---
One more thing:
Please use subject prefixes matching the subsystem. You can get them for example with git log --oneline -- DIRECTORY_OR_FILE on the directory your patch is touching.
The current prefix is just terrible... are you changing all bindings in entire kernel repository?
Best regards,
Krzysztof
PATCH v3 2/2 memory: tegra: make sid and broadcast regions optional
In reply to Sumit GuptaMC SID and Broadbast channel register access is restricted for Guest VM. In Tegra MC driver, consider both the regions as optional and skip access to restricted registers from Guest if a region is not present in Guest DT.
--- drivers/memory/tegra/mc.c | 9 ++++++++- drivers/memory/tegra/mc.h | 22 ++++++++++++---------- drivers/memory/tegra/tegra186.c | 25 +++++++++++++------------ 3 files changed, 33 insertions(+), 23 deletions(-)
drivers/memory/tegra/mc.c +8 -1
@@ -899,6 +899,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)static int tegra_mc_probe (struct platform_device *pdev) { +struct resource *res;struct tegra_mc *mc;u64 mask;int err;
@@ -923,7 +924,13 @@ static int tegra_mc_probe(struct platform_device *pdev)/* length of MC tick in nanoseconds */ mc->tick =30 ; - mc->regs =devm_platform_ioremap_resource (pdev,0 ); +if (mc->soc->num_channels) { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"sid" ); +if (res) + mc->regs =devm_ioremap_resource (&pdev->dev, res); + }else { + mc->regs =devm_platform_ioremap_resource (pdev,0 ); + }if (IS_ERR (mc->regs))return PTR_ERR (mc->regs);
drivers/memory/tegra/mc.h +12 -10
@@ -112,25 +112,27 @@ icc_provider_to_tegra_mc(struct icc_provider *provider)static inline u32 mc_ch_readl (const struct tegra_mc *mc,int ch,unsigned long offset) { -if (!mc->bcast_ch_regs) -return 0 ; - -if (ch ==MC_BROADCAST_CHANNEL ) +if (ch ==MC_BROADCAST_CHANNEL ) { +if (!mc->bcast_ch_regs) +return 0 ;return readl_relaxed (mc->bcast_ch_regs + offset); + }else if (mc->ch_regs) { +return readl_relaxed (mc->ch_regs[ch] + offset); + } -return readl_relaxed (mc->ch_regs[ch] + offset); +return 0 ; }static inline void mc_ch_writel (const struct tegra_mc *mc,int ch,u32 value,unsigned long offset) { -if (!mc->bcast_ch_regs) -return ; - -if (ch ==MC_BROADCAST_CHANNEL ) +if (ch ==MC_BROADCAST_CHANNEL ) { +if (!mc->bcast_ch_regs) +return ;writel_relaxed (value, mc->bcast_ch_regs + offset); -else + }else if (mc->ch_regs) {writel_relaxed (value, mc->ch_regs[ch] + offset); + } }static inline u32 mc_readl (const struct tegra_mc *mc,unsigned long offset)
drivers/memory/tegra/tegra186.c +13 -12
@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];int err; - mc->bcast_ch_regs =devm_platform_ioremap_resource_byname (pdev,"broadcast" ); -if (IS_ERR (mc->bcast_ch_regs)) { -if (PTR_ERR (mc->bcast_ch_regs) == -EINVAL ) { -dev_warn (&pdev->dev, -"Broadcast channel is missing, please update your device-tree\n" ); - mc->bcast_ch_regs =NULL ; - goto populate; - } - -return PTR_ERR (mc->bcast_ch_regs); + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"broadcast" ); +if (res) { + mc->bcast_ch_regs =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (mc->bcast_ch_regs)) +return PTR_ERR (mc->bcast_ch_regs); } mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
@@ -55,7 +51,6 @@ static int tegra186_mc_probe(struct tegra_mc *mc)return PTR_ERR (mc->ch_regs[i]); } -populate: err =of_platform_populate (mc->dev->of_node,NULL ,NULL , mc->dev);if (err <0 )return err;
@@ -121,6 +116,9 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)if (!tegra_dev_iommu_get_stream_id (dev, &sid))return 0 ; +if (!mc->regs) +return 0 ; +while (!of_parse_phandle_with_args (dev->of_node,"interconnects" ,"#interconnect-cells" , index, &args)) {if (args.np == mc->dev->of_node && args.args_count !=0 ) {
@@ -146,6 +144,9 @@ static int tegra186_mc_resume(struct tegra_mc *mc)#if IS_ENABLED (CONFIG_IOMMU_API )unsigned int i; +if (!mc->regs) +return 0 ; +for (i =0 ; i < mc->soc->num_clients; i++) {const struct tegra_mc_client *client = &mc->soc->clients[i];
Signature · 1 line
2.17.1
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 1 line · Sumit Gupta
MC SID and Broadbast channel register access is restricted for Guest VM.
Same typo
Quoted 4 lines
In Tegra MC driver, consider both the regions as optional and skip access to restricted registers from Guest if a region is not present in Guest DT.
...
Quoted 7 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0
drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];
How is it relevant? I don't see this being used in your diff.
Best regards,
Krzysztof
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 6 lines · Sumit Gupta
Quoted 1 line
MC SID and Broadbast channel register access is restricted for Guest VM.
Same typo
Thank you for catching. Will correct in v4.
Quoted 25 lines
Quoted 4 lines
In Tegra MC driver, consider both the regions as optional and skip access to restricted registers from Guest if a region is not present in Guest DT.
...
Quoted 7 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
Krzysztof
Did this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294]
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Thank you,
Sumit Gupta
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 44 lines · Sumit Gupta
Quoted 6 lines · Sumit Gupta
Quoted 1 line
MC SID and Broadbast channel register access is restricted for Guest VM.
Same typo
Thank you for catching. Will correct in v4.
Quoted 25 lines
Quoted 4 lines
In Tegra MC driver, consider both the regions as optional and skip access to restricted registers from Guest if a region is not present in Guest DT.
...
Quoted 7 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~
../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
the range [0, 4294967294]
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~
../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
4 and 13 bytes into a destination of size 8
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
BTW, really, such answers do not make review of your code smoother.
Best regards,
Krzysztof
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 48 lines
Quoted 32 lines
Quoted 21 lines
Quoted 10 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i); | ^~ ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294] 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~ ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
Quoted 5 lines
BTW, really, such answers do not make review of your code smoother.
Best regards,
Krzysztof
Apologies for not explaining it earlier.
I increased the buffer size to suppress a static check warning in the existing code due to big range of 'unsigned int i', if copied to small name buffer.
Seems like the warning is harmless as the maximum value of num_channels is 16. I will remove it and keep the buffer size as 8 in the next version.
Thank you,
Sumit Gupta
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 56 lines · Sumit Gupta
Quoted 48 lines
Quoted 32 lines
Quoted 21 lines
Quoted 10 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i); | ^~ ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294] 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~ ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
Quoted 5 lines
BTW, really, such answers do not make review of your code smoother.
Best regards,
KrzysztofApologies for not explaining it earlier.
Quoted 8 lines
I increased the buffer size to suppress a static check warning in the existing code due to big range of 'unsigned int i', if copied to small name buffer.
Seems like the warning is harmless as the maximum value of
num_channelsis 16. I will remove it and keep the buffer size as 8 in the next version.
That's not the point. For the third time: how is it relevant to this change here? Was or was not the warning before?
Best regards,
Krzysztof
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 60 lines
Quoted 60 lines
Quoted 48 lines
Quoted 32 lines
Quoted 21 lines
Quoted 10 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i); | ^~ ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294] 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~ ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
Quoted 5 lines
BTW, really, such answers do not make review of your code smoother.
Best regards,
KrzysztofApologies for not explaining it earlier.
I increased the buffer size to suppress a static check warning in the existing code due to big range of 'unsigned int i', if copied to small name buffer.
Quoted 8 lines
Quoted 4 lines
Seems like the warning is harmless as the maximum value of
num_channelsis 16. I will remove it and keep the buffer size as 8 in the next version.That's not the point. For the third time: how is it relevant to this change here? Was or was not the warning before?
This is not relevant to the change here. The warning was before as well.
Thank you,
Sumit Gupta
Quoted 3 lines
Best regards,
Krzysztof
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 65 lines · Sumit Gupta
Quoted 65 lines
Quoted 64 lines
Quoted 48 lines
Quoted 32 lines
Quoted 21 lines
Quoted 10 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i); | ^~ ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294] 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~ ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
Quoted 5 lines
BTW, really, such answers do not make review of your code smoother.
Best regards,
KrzysztofApologies for not explaining it earlier.
I increased the buffer size to suppress a static check warning in the existing code due to big range of 'unsigned int i', if copied to small name buffer.
Seems like the warning is harmless as the maximum value of
num_channelsis 16. I will remove it and keep the buffer size as 8 in the next version.
Quoted 5 lines
Quoted 3 lines
That's not the point. For the third time: how is it relevant to this change here? Was or was not the warning before?
This is not relevant to the change here. The warning was before as well.
OK, fixing the warning is always a good idea, but this *must* be always separate patch, with its own explanation and rationale, and warning message.
Best regards,
Krzysztof
Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
Quoted 63 lines
Quoted 63 lines
Quoted 63 lines
Quoted 62 lines
Quoted 46 lines
Quoted 30 lines
Quoted 19 lines
Quoted 8 lines
static inline u32
mc_readl(const struct tegra_mc *mc, unsigned long offset)drivers/memory/tegra/tegra186.c +0
-0drivers/memory/tegra/tegra186.c line 31
Quoted 7 lines
drivers/memory/tegra/tegra186.c +2
-1@@ -26,20 +26,16 @@static int tegra186_mc_probe (struct tegra_mc *mc) {struct platform_device *pdev =to_platform_device (mc->dev); +struct resource *res;unsigned int i; -char name[8 ]; +char name[14 ];How is it relevant? I don't see this being used in your diff.
Quoted 3 lines
Best regards,
KrzysztofDid this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In functiontegra186_mc_probe:../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6 [8;;https://gc c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]Quoted 10 lines
51 | snprintf(name, sizeof(name), "ch%u", i); | ^~ ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in the range [0, 4294967294] 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~ ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between 4 and 13 bytes into a destination of size 8 51 | snprintf(name, sizeof(name), "ch%u", i); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I asked how this is relevant to this change and you answer there is a warning. If the warning was there, your answer is really just deflecting the topic, so obviously this is new warning. Which part of code uses longer name?
Quoted 5 lines
BTW, really, such answers do not make review of your code smoother.
Best regards,
KrzysztofApologies for not explaining it earlier.
I increased the buffer size to suppress a static check warning in the existing code due to big range of 'unsigned int i', if copied to small name buffer.
Seems like the warning is harmless as the maximum value of
num_channelsis 16. I will remove it and keep the buffer size as 8 in the next version.
Quoted 9 lines
Quoted 5 lines
Quoted 3 lines
That's not the point. For the third time: how is it relevant to this change here? Was or was not the warning before?
This is not relevant to the change here. The warning was before as well.
OK, fixing the warning is always a good idea, but this *must* be always separate patch, with its own explanation and rationale, and warning message.
Sure, will submit a separate patch for the warning and spin a v4 for this patch series after incorporating all review comments.
Thank you,
Sumit Gupta
Quoted 3 lines
Best regards,
Krzysztof