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arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs

PATCH Superseded Rob Herring 3 participants 3 messages Apr 12, 2024 – Apr 13, 2024

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Rob Herring

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#0 lore raw

PATCH 1/1 arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs

Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by Rob Herring <[email protected]>
---
 arch/arm64/boot/dts/qcom/msm8956.dtsi |  4 ++--
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 10 ++++++++++
 arch/arm64/boot/dts/qcom/sm4450.dtsi  | 11 ++++++++---
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 14 ++++++++++++--
 arch/arm64/boot/dts/qcom/sm8550.dtsi  | 19 +++++++++++++++++--
 arch/arm64/boot/dts/qcom/sm8650.dtsi  | 14 ++++++++++++--
 6 files changed, 61 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/qcom/msm8956.dtsi +2 -2
index 668e05185c21..fa36b62156bb 100644
@@ -8,8 +8,8 @@
 
 #include "msm8976.dtsi"
 
-&pmu {
-	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+&pmu_a72 {
+	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
 };
 
 &tsens {
arch/arm64/boot/dts/qcom/msm8976.dtsi +10 -0
index d2bb1ada361a..1ad102b1633c 100644
@@ -226,6 +226,16 @@ pmu: pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
+	pmu-a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	pmu_a72: pmu-a72 {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
 
 	psci {
 		compatible = "arm,psci-1.0";
arch/arm64/boot/dts/qcom/sm4450.dtsi +8 -3
index 603c962661cc..411eb7577407 100644
@@ -268,9 +268,14 @@ memory@a0000000 {
 		reg = <0x0 0xa0000000 0x0 0x0>;
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	psci {
arch/arm64/boot/dts/qcom/sm8350.dtsi +12 -2
index a5e7dbbd8c6c..127fa9a935da 100644
@@ -300,8 +300,18 @@ memory@80000000 {
 		reg = <0x0 0x80000000 0x0 0x0>;
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x1 {
+		compatible = "arm,cortex-x1-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
arch/arm64/boot/dts/qcom/sm8550.dtsi +17 -2
index 3904348075f6..8e7d0ac17a12 100644
@@ -357,8 +357,23 @@ memory@a0000000 {
 		reg = <0 0xa0000000 0 0>;
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a510 {
+		compatible = "arm,cortex-a510-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a710 {
+		compatible = "arm,cortex-a710-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x3 {
+		compatible = "arm,cortex-x3-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
arch/arm64/boot/dts/qcom/sm8650.dtsi +12 -2
index ba72d8f38420..90102a41489d 100644
@@ -394,8 +394,18 @@ memory@a0000000 {
 		reg = <0 0xa0000000 0 0>;
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a520 {
+		compatible = "arm,cortex-a520-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x4 {
+		compatible = "arm,cortex-x4-pmu";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
Signature · 1 line
2.43.0
#1 lore raw
Quoted 38 lines · Rob Herring

Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by Rob Herring <[email protected]>
---
 arch/arm64/boot/dts/qcom/msm8956.dtsi |  4 ++--
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 10 ++++++++++
 arch/arm64/boot/dts/qcom/sm4450.dtsi  | 11 ++++++++---
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 14 ++++++++++++--
 arch/arm64/boot/dts/qcom/sm8550.dtsi  | 19 +++++++++++++++++--
 arch/arm64/boot/dts/qcom/sm8650.dtsi  | 14 ++++++++++++--
 6 files changed, 61 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/qcom/msm8956.dtsi +2 -2
index 668e05185c21..fa36b62156bb 100644
@@ -8,8 +8,8 @@
 
 #include "msm8976.dtsi"
 
-&pmu {
-       interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+&pmu_a72 {
+       interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
 };
 
 &tsens {
arch/arm64/boot/dts/qcom/msm8976.dtsi +0 -0
index d2bb1ada361a..1ad102b1633c 100644

arch/arm64/boot/dts/qcom/msm8976.dtsi pmu: pmu { · line 227

Quoted 2 lines
arch/arm64/boot/dts/qcom/msm8976.dtsi +0 -0
@@ -226,6 +226,16 @@ pmu: pmu {
                compatible = "arm,armv8-pmuv3";
                interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

I think these two lines were supposed to be dropped.

Quoted 120 lines
arch/arm64/boot/dts/qcom/msm8976.dtsi +10 -0
        };
+       pmu-a53 {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       pmu_a72: pmu-a72 {
+               compatible = "arm,cortex-a72-pmu";
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
 
        psci {
                compatible = "arm,psci-1.0";
arch/arm64/boot/dts/qcom/sm4450.dtsi +8 -3
index 603c962661cc..411eb7577407 100644
@@ -268,9 +268,14 @@ memory@a0000000 {
                reg = <0x0 0xa0000000 0x0 0x0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+       pmu-a55 {
+               compatible = "arm,cortex-a55-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a78 {
+               compatible = "arm,cortex-a78-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
        psci {
arch/arm64/boot/dts/qcom/sm8350.dtsi +12 -2
index a5e7dbbd8c6c..127fa9a935da 100644
@@ -300,8 +300,18 @@ memory@80000000 {
                reg = <0x0 0x80000000 0x0 0x0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a55 {
+               compatible = "arm,cortex-a55-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a78 {
+               compatible = "arm,cortex-a78-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x1 {
+               compatible = "arm,cortex-x1-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
arch/arm64/boot/dts/qcom/sm8550.dtsi +17 -2
index 3904348075f6..8e7d0ac17a12 100644
@@ -357,8 +357,23 @@ memory@a0000000 {
                reg = <0 0xa0000000 0 0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a510 {
+               compatible = "arm,cortex-a510-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a710 {
+               compatible = "arm,cortex-a710-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a720 {
+               compatible = "arm,cortex-a720-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x3 {
+               compatible = "arm,cortex-x3-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
arch/arm64/boot/dts/qcom/sm8650.dtsi +12 -3
index ba72d8f38420..90102a41489d 100644
@@ -394,8 +394,18 @@ memory@a0000000 {
                reg = <0 0xa0000000 0 0>;
        };
 
-       pmu {
-               compatible = "arm,armv8-pmuv3";
+       pmu-a520 {
+               compatible = "arm,cortex-a520-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-a720 {
+               compatible = "arm,cortex-a720-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       pmu-x4 {
+               compatible = "arm,cortex-x4-pmu";
                interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
        };
 
--

2.43.0

Signature · 2 lines
With best wishes
Dmitry
#2 lore raw
In reply to Rob Herring
Quoted 120 lines · Rob Herring

Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by Rob Herring <[email protected]>
---
  arch/arm64/boot/dts/qcom/msm8956.dtsi |  4 ++--
  arch/arm64/boot/dts/qcom/msm8976.dtsi | 10 ++++++++++
  arch/arm64/boot/dts/qcom/sm4450.dtsi  | 11 ++++++++---
  arch/arm64/boot/dts/qcom/sm8350.dtsi  | 14 ++++++++++++--
  arch/arm64/boot/dts/qcom/sm8550.dtsi  | 19 +++++++++++++++++--
  arch/arm64/boot/dts/qcom/sm8650.dtsi  | 14 ++++++++++++--
  6 files changed, 61 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/qcom/msm8956.dtsi +2 -2
index 668e05185c21..fa36b62156bb 100644
@@ -8,8 +8,8 @@
 
  #include "msm8976.dtsi"
 
-&pmu {
-	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+&pmu_a72 {
+	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
  };
 
  &tsens {
arch/arm64/boot/dts/qcom/msm8976.dtsi +10 -0
index d2bb1ada361a..1ad102b1633c 100644
@@ -226,6 +226,16 @@ pmu: pmu {
  		compatible = "arm,armv8-pmuv3";
  		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  	};
+	pmu-a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	pmu_a72: pmu-a72 {
+		compatible = "arm,cortex-a72-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
 
  	psci {
  		compatible = "arm,psci-1.0";
arch/arm64/boot/dts/qcom/sm4450.dtsi +8 -3
index 603c962661cc..411eb7577407 100644
@@ -268,9 +268,14 @@ memory@a0000000 {
  		reg = <0x0 0xa0000000 0x0 0x0>;
  	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  	};
 
  	psci {
arch/arm64/boot/dts/qcom/sm8350.dtsi +12 -2
index a5e7dbbd8c6c..127fa9a935da 100644
@@ -300,8 +300,18 @@ memory@80000000 {
  		reg = <0x0 0x80000000 0x0 0x0>;
  	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a78 {
+		compatible = "arm,cortex-a78-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x1 {
+		compatible = "arm,cortex-x1-pmu";
  		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  	};
arch/arm64/boot/dts/qcom/sm8550.dtsi +10 -2
index 3904348075f6..8e7d0ac17a12 100644
@@ -357,8 +357,23 @@ memory@a0000000 {
  		reg = <0 0xa0000000 0 0>;
  	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a510 {
+		compatible = "arm,cortex-a510-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a710 {
+		compatible = "arm,cortex-a710-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+

arch/arm64/boot/dts/qcom/sm8550.dtsi memory@a0000000 { · line 379

Quoted 10 lines
arch/arm64/boot/dts/qcom/sm8550.dtsi +7 -0
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x3 {
+		compatible = "arm,cortex-x3-pmu";
  		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  	};

I believe SM8550 uses cortex-a715 instead of a720.

Quoted 25 lines
arch/arm64/boot/dts/qcom/sm8650.dtsi +12 -2
index ba72d8f38420..90102a41489d 100644
@@ -394,8 +394,18 @@ memory@a0000000 {
  		reg = <0 0xa0000000 0 0>;
  	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a520 {
+		compatible = "arm,cortex-a520-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmu-x4 {
+		compatible = "arm,cortex-x4-pmu";
  		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  	};