riscv: dts: starfive: add PCIe dts configuration for JH7110
Subsystems (3)
PATCH 1/1 riscv: dts: starfive: add PCIe dts configuration for JH7110
Add PCIe dts configuraion for JH7110 SoC platform.
--- .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+)
arch/riscv/boot/dts/starfive/jh7110-common.dtsi +64 -0
@@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + &pwmdac { pinctrl-names = "default"; pinctrl-0 = <&pwmdac_pins>;
@@ -476,6 +492,54 @@ }; }; + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = <GPIOMUX(27, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(32, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = <GPIOMUX(29, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(21, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + pwmdac_pins: pwmdac-0 { pwmdac-pins { pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
arch/riscv/boot/dts/starfive/jh7110.dtsi +86 -0
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2.17.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Conor Dooley
maintainerQuoted 22 lines · Minda Chen
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+)arch/riscv/boot/dts/starfive/jh7110-common.dtsi +5
-0@@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>;
arch/riscv/boot/dts/starfive/jh7110-common.dtsi line 311
Quoted 10 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi +10
-0+ status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +};
Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I assume if one does, all does, since they're basically identical?
Quoted 32 lines · Minda Chen
Quoted 28 lines
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+)arch/riscv/boot/dts/starfive/jh7110-common.dtsi +10
-0@@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
Quoted 8 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi line 311
Quoted 5 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi +5
-0+ phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +};Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I assume if one does, all does, since they're basically identical?
Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same.
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Conor Dooley
maintainerQuoted 41 lines · Minda Chen
Quoted 32 lines · Minda Chen
Quoted 28 lines
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+)arch/riscv/boot/dts/starfive/jh7110-common.dtsi +10
-0@@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;Quoted 8 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi line 311
Quoted 5 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi +5
-0+ phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +};Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I assume if one does, all does, since they're basically identical?
Quoted 1 line
Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same.
This patch adds both PCIe instances for the Star64 though, since that also includes jh7110-common.dtsi. I think you need to enable these in the board dts files instead?
Quoted 46 lines · Minda Chen
Quoted 11 lines
Quoted 11 lines · Minda Chen
Quoted 7 lines
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>--- .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 86+++++++++++++++++++
Quoted 30 lines
Quoted 29 lines
Quoted 16 lines
2 files changed, 150 insertions(+)arch/riscv/boot/dts/starfive/jh7110-common.dtsi +5
-0@@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>;arch/riscv/boot/dts/starfive/jh7110-common.dtsi line 311
Quoted 10 lines
arch/riscv/boot/dts/starfive/jh7110-common.dtsi +10
-0+ status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +};Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I assume if one does, all does, since they're basically identical?
Quoted 6 lines
Quoted 1 line
Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0,
PCIe1 pins are the same.
This patch adds both PCIe instances for the Star64 though, since that also includes
jh7110-common.dtsi. I think you need to enable these in the board dts files instead?
OK. I will enable them in board dts file. Thanks.
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Quoted 9 lines · Minda Chen
Add PCIe dts configuraion for JH7110 SoC platform.
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>---
.../boot/dts/starfive/jh7110-common.dtsi| 64 ++++++++++++++arch/riscv/boot/dts/starfive/jh7110.dtsi| 86 +++++++++++++++++++2 files changed, 150 insertions(+)
Is there a corresponding YAML schema?
Jess
Conor Dooley
maintainerQuoted 4 lines · Jessica Clarke
Quoted 3 lines · Minda Chen
Add PCIe dts configuraion for JH7110 SoC platform.
Quoted 8 lines
Quoted 6 lines
Signed-off-by Minda Chen <[email protected]>Reviewed-by Hal Feng <[email protected]>---
.../boot/dts/starfive/jh7110-common.dtsi| 64 ++++++++++++++arch/riscv/boot/dts/starfive/jh7110.dtsi| 86 +++++++++++++++++++2 files changed, 150 insertions(+)Is there a corresponding YAML schema?
Yeah, it's in linux-next via the PCI tree:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml