include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
RFC PATCH 1/1 include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension.
However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection.
Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the MHPMEVENT_SSCOF_MASK to support it.
--- include/sbi/riscv_encoding.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
include/sbi/riscv_encoding.h +1 -1
@@ -207,7 +207,7 @@#endif -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_SSCOF_MASK _ULL(0xFF00000000000000)#define ENVCFG_STCE (_ULL(1) << 63)#define ENVCFG_PBMTE (_ULL(1) << 62)
Signature · 1 line
2.43.2
Anup Patel
AppliedRFC PATCH 1/1 include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
Quoted 9 lines · On Tue, Jul 30, 2024 at 3:00?PM Eric Lin <[email protected]> wrote:
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension.
However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection.
Quoted 5 lines
Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the
MHPMEVENT_SSCOF_MASKto support it.Signed-off-by Eric Lin <[email protected]>
Actually, only the upper 6 bits of mhpmevent CSR are defined as-per Sscofpmf in the integrated Priv spec.
I have updated this patch accordingly at the time of merging this patch.
Applied this patch to the riscv/opensbi repo.
Thanks,
Anup
Quoted 20 lines
--- include/sbi/riscv_encoding.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/sbi/riscv_encoding.h +1
-2@@ -207,7 +207,7 @@#endif -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_SSCOF_MASK _ULL(0xFF00000000000000)#define ENVCFG_STCE (_ULL(1) << 63)#define ENVCFG_PBMTE (_ULL(1) << 62) --2.43.2
RFC PATCH 1/1 include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
Quoted 11 lines · On Thu, Aug 1, 2024 at 7:34?AM Anup Patel <[email protected]> wrote:
Quoted 9 lines · On Tue, Jul 30, 2024 at 3:00?PM Eric Lin <[email protected]> wrote:
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension.
However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection.
Quoted 9 lines
Quoted 5 lines
Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the
MHPMEVENT_SSCOF_MASKto support it.Signed-off-by Eric Lin <[email protected]>Actually, only the upper 6 bits of mhpmevent CSR are defined as-per Sscofpmf in the integrated Priv spec.
That may be the result of an integration issue. I cross checked the ratified spec
which had 8 bits allocated (56:57 are reserved). The Smcntrpmf extension in the integrated spec also have 8 bits citing sscofpmf example. I have filed an issue in isa manual repo for clarification
https://github.com/riscv/riscv-isa-manual/issues/1578
Quoted 29 lines
I have updated this patch accordingly at the time of merging this patch.
Reviewed-by Anup Patel <[email protected]>Applied this patch to the riscv/opensbi repo.
Thanks,
AnupQuoted 20 lines
--- include/sbi/riscv_encoding.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/sbi/riscv_encoding.h +1
-2@@ -207,7 +207,7 @@#endif -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_SSCOF_MASK _ULL(0xFF00000000000000)#define ENVCFG_STCE (_ULL(1) << 63)#define ENVCFG_PBMTE (_ULL(1) << 62) --2.43.2
RFC PATCH 1/1 include: Adjust Sscofpmf mhpmevent mask for upper 8 bits
Quoted 23 lines · On Thu, Aug 1, 2024 at 11:15?PM Atish Kumar Patra <[email protected]> wrote:
Quoted 11 lines · On Thu, Aug 1, 2024 at 7:34?AM Anup Patel <[email protected]> wrote:
Quoted 9 lines · On Tue, Jul 30, 2024 at 3:00?PM Eric Lin <[email protected]> wrote:
Currently, OpenSBI reserves the upper 16 bits in mhpmevent for the Sscofpmf extension.
However, according to the Sscofpmf extension specification[1], it only defines the upper 8 bits in mhpmevent for privilege mode inhibit and counter overflow disable. Other bits are defined by the platform for event selection.
Quoted 9 lines
Quoted 5 lines
Since vendors might define raw event encoding exceeding 48 bits in mhpmevent, we should adjust the
MHPMEVENT_SSCOF_MASKto support it.Signed-off-by Eric Lin <[email protected]>Actually, only the upper 6 bits of mhpmevent CSR are defined as-per Sscofpmf in the integrated Priv spec.
Quoted 7 lines
That may be the result of an integration issue. I cross checked the ratified spec
which had 8 bits allocated (56:57 are reserved). The Smcntrpmf extension in the integrated spec also have 8 bits citing sscofpmf example. I have filed an issue in isa manual repo for clarification
Thanks for confirming, I have kept this patch as-is.
Regards,
Anup
Quoted 30 lines
Quoted 30 lines
I have updated this patch accordingly at the time of merging this patch.
Reviewed-by Anup Patel <[email protected]>Applied this patch to the riscv/opensbi repo.
Thanks,
AnupQuoted 20 lines
--- include/sbi/riscv_encoding.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)include/sbi/riscv_encoding.h +1
-2@@ -207,7 +207,7 @@#endif -#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000) +#define MHPMEVENT_SSCOF_MASK _ULL(0xFF00000000000000)#define ENVCFG_STCE (_ULL(1) << 63)#define ENVCFG_PBMTE (_ULL(1) << 62) --2.43.2