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FAILED: patch "[PATCH] clk: qcom: gcc-sc8180x: Add GPLL9 support" failed to apply to 5.15-stable tree

PATCH [email protected] 1 participant 1 message Oct 7, 2024

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The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.15.y
git checkout FETCH_HEAD
git cherry-pick -x 818a2f8d5e4ad2c1e39a4290158fe8e39a744c70
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2024100727-starved-makeover-291c@gregkh' --subject-prefix 'PATCH 5.15.y' HEAD^..

Possible dependencies:

818a2f8d5e4a ("clk: qcom: gcc-sc8180x: Add GPLL9 support")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 818a2f8d5e4ad2c1e39a4290158fe8e39a744c70 Mon Sep 17 00:00:00 2001
From: Satya Priya Kakitapalli <[email protected]>
Date: Mon, 12 Aug 2024 10:43:03 +0530
Subject: [PATCH] clk: qcom: gcc-sc8180x: Add GPLL9 support

Add the missing GPLL9 pll and fix the gcc_parents_7 data to use the correct pll hw.

Fixes 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc [email protected]
Reviewed-by Dmitry Baryshkov <[email protected]>
Signed-off-by Satya Priya Kakitapalli <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
Signed-off-by Bjorn Andersson <[email protected]>
drivers/clk/qcom/gcc-sc8180x.c +19 -1
index d25c5dc37f91..0596427f8922 100644
@@ -142,6 +142,23 @@ static struct clk_alpha_pll gpll7 = {
 	},
 };
 
+static struct clk_alpha_pll gpll9 = {
+	.offset = 0x1c000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+	.clkr = {
+		.enable_reg = 0x52000,
+		.enable_mask = BIT(9),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gpll9",
+			.parent_data = &(const struct clk_parent_data) {
+				.fw_name = "bi_tcxo",
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_fixed_trion_ops,
+		},
+	},
+};
+
 static const struct parent_map gcc_parent_map_0[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPLL0_OUT_MAIN, 1 },

@@ -241,7 +258,7 @@ static const struct parent_map gcc_parent_map_7[] = {
 static const struct clk_parent_data gcc_parents_7[] = {
 	{ .fw_name = "bi_tcxo", },
 	{ .hw = &gpll0.clkr.hw },
-	{ .name = "gppl9" },
+	{ .hw = &gpll9.clkr.hw },
 	{ .hw = &gpll4.clkr.hw },
 	{ .hw = &gpll0_out_even.clkr.hw },
 };

@@ -4552,6 +4569,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
 	[GPLL1] = &gpll1.clkr,
 	[GPLL4] = &gpll4.clkr,
 	[GPLL7] = &gpll7.clkr,
+	[GPLL9] = &gpll9.clkr,
 };
 
 static const struct qcom_reset_map gcc_sc8180x_resets[] = {