DC Patches October 14, 2024

This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation

---

Aric Cyr (1):
drm/amd/display: 3.2.306

Aurabindo Pillai (3):
drm/amd/display: temp w/a for dGPU to enter idle optimizations drm/amd/display: Reuse subvp enable check for DCN401 drm/amd/display: temp w/a for DP Link Layer compliance

Bhuvanachandra Pinninti (1):
drm/amd/display: To change dcn301_init.h guard.

Dillon Varone (1):
drm/amd/display: Recalculate SubVP Phantom VBlank End in dml21

Fangzhi Zuo (1):
drm/amd/display: Add a Precise Delay Routine

Leo Chen (1):
drm/amd/display: Adding array index check to prevent memory corruption

Samson Tam (1):
drm/amd/display: update fullscreen status to SPL

Yihan Zhu (1):
drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++-
 .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 +++++++++++
 .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  |  6 +++--
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  5 +++++
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../gpu/drm/amd/display/dc/dc_spl_translate.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  3 +++
 .../dc/dml2/dml21/dml21_translation_helper.c  |  1 -
 .../dml2/dml21/src/dml2_core/dml2_core_dcn4.c |  1 +
 .../dml21/src/dml2_core/dml2_core_utils.c     |  1 +
 .../drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h  |  1 +
 .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h  |  1 +
 .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c  | 22 +++++++++++++++----
 .../amd/display/dc/hwss/dcn301/dcn301_init.h  |  4 ++--
 .../dc/link/protocols/link_dp_training.c      |  2 +-
 .../dc/resource/dcn401/dcn401_resource.c      |  3 ++-
 16 files changed, 56 insertions(+), 14 deletions(-)

2.37.3

From: Aurabindo Pillai <[email protected]>

[Why&How]
vblank immediate disable currently does not work for all asics. On DCN401, the vblank interrupts never stop coming, and hence we never get a chance to trigger idle optimizations.

Add a workaround to enable immediate disable only on APUs for now. This adds a 2-frame delay for triggering idle optimization, which is a negligible overhead.

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index a4882b16ace2..6ea54eb5d68d 100644
@@ -8379,7 +8379,8 @@ static void manage_dm_interrupts(struct amdgpu_device *adev,
 		if (amdgpu_ip_version(adev, DCE_HWIP, 0) <
 		    IP_VERSION(3, 5, 0) ||
 		    acrtc_state->stream->link->psr_settings.psr_version <
-		    DC_PSR_VERSION_UNSUPPORTED) {
+		    DC_PSR_VERSION_UNSUPPORTED ||
+		    !(adev->flags & AMD_IS_APU)) {
 			timing = &acrtc_state->stream->timing;
 
 			/* at least 2 frames */

2.37.3

[Public]

Hi Mario,

Hamza is working on the reported issue and appears to be due to a different root cause. Hence, we're expecting that the fix for that issue is likely going to be different, with what we know so far. While that issue is being debugged, this patch will allow us to have better idle power consumption on dGPUs

--

Regards,
Jay
________________________________
From: Limonciello, Mario <[email protected]>
Sent: Tuesday, October 15, 2024 9:14 AM
To: Lin, Wayne <[email protected]>; [email protected] <[email protected]>
Cc: Wentland, Harry <[email protected]>; Li, Sun peng (Leo) <[email protected]>; Siqueira, Rodrigo <[email protected]>; Mahfooz, Hamza <[email protected]>; Pillai, Aurabindo <[email protected]>; Li, Roman <[email protected]>; Chung, ChiaHsuan (Tom) <[email protected]>; Zuo, Jerry <[email protected]>; Mohamed, Zaeem <[email protected]>; Chiu, Solomon <[email protected]>; Wheeler, Daniel <[email protected]>; Deucher, Alexander <[email protected]>; [email protected] <[email protected]>
Subject: Re: [PATCH 01/10] drm/amd/display: temp w/a for dGPU to enter idle optimizations

Jay,

Got it, thanks for confirming.

Thanks,

From: Yihan Zhu <[email protected]>

[WHY & HOW]
Cursor corruption observed on USBC display with specific system setup with a reboot. Cursor memory might still in the lightsleep state due to voltage issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on DCN35.

---
 .../drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h  |  1 +
 .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h  |  1 +
 .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c  | 22 +++++++++++++++----
 3 files changed, 20 insertions(+), 4 deletions(-)

index cd1706d301e7..f09cba8e29cc 100644
@@ -690,6 +690,7 @@ struct dcn20_dpp {
 	int lb_memory_size;
 	int lb_bits_per_entry;
 	bool is_write_to_ram_a_safe;
+	bool dispclk_r_gate_disable;
 	struct scaler_data scl_data;
 	struct pwl_params pwl_data;
 };

index b110f35ef66b..f236824126e9 100644
@@ -572,6 +572,7 @@ struct dcn3_dpp {
 	int lb_memory_size;
 	int lb_bits_per_entry;
 	bool is_write_to_ram_a_safe;
+	bool dispclk_r_gate_disable;
 	struct scaler_data scl_data;
 	struct pwl_params pwl_data;
 };

index 9f885a03eec6..62b7012cda43 100644
@@ -50,11 +50,21 @@ void dpp35_dppclk_control(
 				DPPCLK_RATE_CONTROL, dppclk_div,
 				DPP_CLOCK_ENABLE, 1);
 		else
-			REG_UPDATE(DPP_CONTROL,
-					DPP_CLOCK_ENABLE, 1);
+			if (dpp->dispclk_r_gate_disable)
+				REG_UPDATE_2(DPP_CONTROL,
+					DPP_CLOCK_ENABLE, 1,
+					DISPCLK_R_GATE_DISABLE, 1);
+			else
+				REG_UPDATE(DPP_CONTROL,
+						DPP_CLOCK_ENABLE, 1);
 	} else
-		REG_UPDATE(DPP_CONTROL,
-				DPP_CLOCK_ENABLE, 0);
+		if (dpp->dispclk_r_gate_disable)
+			REG_UPDATE_2(DPP_CONTROL,
+				DPP_CLOCK_ENABLE, 0,
+				DISPCLK_R_GATE_DISABLE, 0);
+		else
+			REG_UPDATE(DPP_CONTROL,
+					DPP_CLOCK_ENABLE, 0);
 }
 
 void dpp35_program_bias_and_scale_fcnv(

@@ -126,6 +136,10 @@ bool dpp35_construct(
 			      (const struct dcn3_dpp_mask *)(tf_mask));
 
 	dpp->base.funcs = &dcn35_dpp_funcs;
+
+	// w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs
+	if (dpp->base.ctx->asic_id.hw_internal_rev <= 0x10)
+		dpp->dispclk_r_gate_disable = true;
 	return ret;
 }
 

2.37.3

From: Aurabindo Pillai <[email protected]>

Reuse subvp enable check from DCN32 for IGT testing of Sub-Viewport feature on DCN401

---
 .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c   | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index 46feff9348d9..b2e59e97818a 100644
@@ -1579,7 +1579,8 @@ static void dcn401_destroy_resource_pool(struct resource_pool **pool)
 }
 
 static struct dc_cap_funcs cap_funcs = {
-	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
+	.get_subvp_en = dcn32_subvp_in_use,
 };
 
 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

2.37.3

From: Leo Chen <[email protected]>

[Why & How]
Array indices out of bound caused memory corruption. Adding checks to ensure that array index stays in bound.

---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c    | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

index b46a3afe48ca..7d68006137a9 100644
@@ -257,11 +257,11 @@ static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
 	int i;
-
 	for (i = 0; i < context->stream_count; ++i) {
 		const struct dc_stream_state *stream = context->streams[i];
 		const struct dc_link *link = stream->link;
-		uint8_t lowest_dpia_index = 0, hr_index = 0;
+		uint8_t lowest_dpia_index = 0;
+		unsigned int hr_index = 0;
 
 		if (!link)
 			continue;

@@ -271,6 +271,8 @@ static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_
 			continue;
 
 		hr_index = (link->link_index - lowest_dpia_index) / 2;
+		if (hr_index >= MAX_HOST_ROUTERS_NUM)
+			continue;
 		host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
 			&stream->timing, dc_link_get_highest_encoding_format(link));
 	}

2.37.3

From: Aurabindo Pillai <[email protected]>

[Why&How]
Disabling P-State support on full updates for DCN401 results in introducing additional communication with SMU. A UCLK hard min message to SMU takes 4 seconds to go through, which was due to DCN not allowing pstate switch, which was caused by incorrect value for TTU watermark before blanking the HUBP prior to DPG on for servicing the test request.

Fix the issue temporarily by disallowing pstate changes for compliance test while test request handler is reworked for a proper fix.

---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c   | 13 +++++++++++++
 1 file changed, 13 insertions(+)

index 8eaf292bc4eb..b0fea0856866 100644
@@ -46,6 +46,7 @@
 
 #include "dm_helpers.h"
 #include "ddc_service_types.h"
+#include "clk_mgr.h"
 
 static u32 edid_extract_panel_id(struct edid *edid)
 {

@@ -1181,6 +1182,8 @@ bool dm_helpers_dp_handle_test_pattern_request(
 	struct pipe_ctx *pipe_ctx = NULL;
 	struct amdgpu_dm_connector *aconnector = link->priv;
 	struct drm_device *dev = aconnector->base.dev;
+	struct dc_state *dc_state = ctx->dc->current_state;
+	struct clk_mgr *clk_mgr = ctx->dc->clk_mgr;
 	int i;
 
 	for (i = 0; i < MAX_PIPES; i++) {

@@ -1281,6 +1284,16 @@ bool dm_helpers_dp_handle_test_pattern_request(
 	pipe_ctx->stream->test_pattern.type = test_pattern;
 	pipe_ctx->stream->test_pattern.color_space = test_pattern_color_space;
 
+	/* Temp W/A for compliance test failure */
+	dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false;
+	dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ?
+		clk_mgr->bw_params->dc_mode_softmax_memclk : clk_mgr->bw_params->max_memclk_mhz;
+	dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz;
+	ctx->dc->clk_mgr->funcs->update_clocks(
+			ctx->dc->clk_mgr,
+			dc_state,
+			false);
+
 	dc_link_dp_set_test_pattern(
 		(struct dc_link *) link,
 		test_pattern,

2.37.3

From: Dillon Varone <[email protected]>

[WHY]
The phantom stream timing is copied from the main stream as most parameters are identical, however some need to be recalculated. Currently VBlank End is not recalculated and copied from the main incorrectly.

[HOW]
Recalculate VBlank End for phantom stream timing.

---
 .../drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 1 +
 .../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c    | 1 +
 2 files changed, 2 insertions(+)

index 0aa4e4d343b0..3d41ffde91c1 100644
@@ -159,6 +159,7 @@ static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters
 	phantom->timing.v_total = meta->v_total;
 	phantom->timing.v_active = meta->v_active;
 	phantom->timing.v_front_porch = meta->v_front_porch;
+	phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;
 	phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
 	phantom->timing.drr_config.enabled = false;
 }

index ab229e1598ae..714b5c39b7e6 100644
@@ -425,6 +425,7 @@ static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters
 	phantom->timing.v_total = meta->v_total;
 	phantom->timing.v_active = meta->v_active;
 	phantom->timing.v_front_porch = meta->v_front_porch;
+	phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active;
 	phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
 	phantom->timing.drr_config.enabled = false;
 }

2.37.3

From: Fangzhi Zuo <[email protected]>

Fix DP compliance failures 4.2.2.12, 4.3.1.21, 4.9.1.19 caused by imprecise delay on fsleep().

---
 .../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index a42c56a57253..754c895e1bfb 100644
@@ -272,7 +272,7 @@ void dp_wait_for_training_aux_rd_interval(
 	struct dc_link *link,
 	uint32_t wait_in_micro_secs)
 {
-	fsleep(wait_in_micro_secs);
+	usleep_range_state(wait_in_micro_secs, wait_in_micro_secs, TASK_UNINTERRUPTIBLE);
 
 	DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
 		__func__,

2.37.3

From: Samson Tam <[email protected]>

[Why]
Current fullscreen check in SPL using dm_helpers is out-of-sync with dc state. This causes an issue during minimal transition where we pick an invalid intermediate state because the pre and post fullscreen status are different.

[How]
Add sharpening_required flag to dc_stream_state. Use this flag to indicate if we are in fullscreen or not. Propagate flag to SPL for fullscreen status. Remove workaround in DML

---
 drivers/gpu/drm/amd/display/dc/core/dc.c                     | 5 +++++
 drivers/gpu/drm/amd/display/dc/dc_spl_translate.c            | 2 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h                   | 3 +++
 .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 1 -
 4 files changed, 9 insertions(+), 2 deletions(-)

index 743f3292d98e..5a12fc75f97f 100644
@@ -2756,6 +2756,9 @@ static enum surface_update_type check_update_surfaces_for_stream(
 		if (stream_update->scaler_sharpener_update)
 			su_flags->bits.scaler_sharpener = 1;
 
+		if (stream_update->sharpening_required)
+			su_flags->bits.sharpening_required = 1;
+
 		if (su_flags->raw != 0)
 			overall_type = UPDATE_TYPE_FULL;
 

@@ -3107,6 +3110,8 @@ static void copy_stream_update_to_stream(struct dc *dc,
 	}
 	if (update->scaler_sharpener_update)
 		stream->scaler_sharpener_update = *update->scaler_sharpener_update;
+	if (update->sharpening_required)
+		stream->sharpening_required = *update->sharpening_required;
 }
 
 static void backup_planes_and_stream_state(

index eeffe44be9e3..24aa9df892f3 100644
@@ -195,7 +195,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
 	/* Check if it is stream is in fullscreen and if its HDR.
 	 * Use this to determine sharpness levels
 	 */
-	spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream);
+	spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required;
 	spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);
 	spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits;
 }

index 14ea47eda0c8..413970588a26 100644
@@ -143,6 +143,7 @@ union stream_update_flags {
 		uint32_t crtc_timing_adjust : 1;
 		uint32_t fams_changed : 1;
 		uint32_t scaler_sharpener : 1;
+		uint32_t sharpening_required : 1;
 	} bits;
 
 	uint32_t raw;

@@ -310,6 +311,7 @@ struct dc_stream_state {
 
 	struct luminance_data lumin_data;
 	bool scaler_sharpener_update;
+	bool sharpening_required;
 };
 
 #define ABM_LEVEL_IMMEDIATE_DISABLE 255

@@ -356,6 +358,7 @@ struct dc_stream_update {
 	struct dc_cursor_position *cursor_position;
 	bool *hw_cursor_req;
 	bool *scaler_sharpener_update;
+	bool *sharpening_required;
 };
 
 bool dc_is_stream_unchanged(

index d901b9f7bc6a..7a01a956e4bb 100644
@@ -514,7 +514,6 @@ static void populate_dml21_stream_overrides_from_stream_state(
 		break;
 	}
 	if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy ||
-			((stream->ctx->dc->debug.force_sharpness > 1) && stream->ctx->dc->config.use_spl) ||
 			stream->debug.force_odm_combine_segments > 0)
 		stream_desc->overrides.disable_dynamic_odm = true;
 	stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req;

2.37.3

From: Bhuvanachandra Pinninti <[email protected]>

[why & How]
The original guard is wrongly to be set as for dcn30. Changed it from 30 to 301.

---
 drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index 0bca48ccbfa2..a6e0115a53ee 100644
@@ -23,8 +23,8 @@
  *
  */
 
-#ifndef __DC_DCN30_INIT_H__
-#define __DC_DCN30_INIT_H__
+#ifndef __DC_DCN301_INIT_H__
+#define __DC_DCN301_INIT_H__
 
 struct dc;
 

2.37.3

From: Aric Cyr <[email protected]>

This version brings along following fixes:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation

---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index 6ba167d4c785..6d76dc110d38 100644
@@ -55,7 +55,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.305"
+#define DC_VER "3.2.306"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6

2.37.3

[Public]

Hi all,

This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.

APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Single Display DP -> 4k144hz, 4k240hz
* Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
* Thunderbolt -> LG Ultrafine 5k
* DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 3x 4k60hz displays (2x DP, 1x USB-C)
* USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
* PCON -> Club3D CAC-1085 + 1x 4k 144hz

DGPU
* Single Display DP -> 4k144hz, 4k240hz
* Multiple Display DP -> 4k240hz + 4k144hz
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
* DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)

The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
* Changing display configurations and settings
* Video/Audio playback
* Benchmark testing
* Suspend/Resume testing
* Feature testing (Freesync, HDCP, etc.)

Automated testing includes (but is not limited to)
* Script testing (scripts to automate some of the manual checks)
* IGT testing

The testing is mainly tested on the following displays, but occasionally there are tests with other displays
* Samsung G8 Neo 4k240hz
* Samsung QN55QN95B 4k 120hz
* Acer XV322QKKV 4k144hz
* HP U27 4k Wireless 4k60hz
* LG 27UD58B 4k60hz
* LG 32UN650WA 4k60hz
* LG Ultrafine 5k 5k60hz
* AU Optronics B140HAN01.1 1080p 60hz eDP
* AU Optronics B160UAN01.J 1920x1200 165hz eDP
* AU Optronics B160QAN02.L 2560x1600 120hz eDP

The patchset consists of the amd-staging-drm-next branch (Head commit - 3631f572ee38bed4c3d0a9003570c63eaa9fd4e3 -> drm/amdgpu/swsmu: add automatic parameter to set_soft_freq_range) with new patches added on top of it.

Tested on Ubuntu 24.04.1, on Wayland and X11, using KDE Plasma and Gnome.

Thank you,

Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com

-----Original Message-----
From: Wayne Lin <[email protected]>
Sent: Tuesday, October 15, 2024 4:17 AM
To: [email protected]
Cc: Wentland, Harry <[email protected]>; Li, Sun peng (Leo) <[email protected]>; Siqueira, Rodrigo <[email protected]>; Mahfooz, Hamza <[email protected]>; Pillai, Aurabindo <[email protected]>; Li, Roman <[email protected]>; Lin, Wayne <[email protected]>; Chung, ChiaHsuan (Tom) <[email protected]>; Zuo, Jerry <[email protected]>; Mohamed, Zaeem <[email protected]>; Chiu, Solomon <[email protected]>; Wheeler, Daniel <[email protected]>; Lin, Wayne <[email protected]>
Subject: [PATCH 00/10] DC Patches October 14, 2024

This DC patchset brings improvements in multiple areas. In summary, we have:
- Fix dcn401 idle optimization problem
- Fix cursor corruption on dcn35
- Fix DP LL compliance failures
- Fix SubVP Phantom VBlank End calculation

---

Aric Cyr (1):
drm/amd/display: 3.2.306

Aurabindo Pillai (3):
drm/amd/display: temp w/a for dGPU to enter idle optimizations drm/amd/display: Reuse subvp enable check for DCN401 drm/amd/display: temp w/a for DP Link Layer compliance

Bhuvanachandra Pinninti (1):
drm/amd/display: To change dcn301_init.h guard.

Dillon Varone (1):
drm/amd/display: Recalculate SubVP Phantom VBlank End in dml21

Fangzhi Zuo (1):
drm/amd/display: Add a Precise Delay Routine

Leo Chen (1):
drm/amd/display: Adding array index check to prevent memory corruption

Samson Tam (1):
drm/amd/display: update fullscreen status to SPL

Yihan Zhu (1):
drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++-  .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 +++++++++++  .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  |  6 +++--
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  5 +++++
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../gpu/drm/amd/display/dc/dc_spl_translate.c |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h    |  3 +++
 .../dc/dml2/dml21/dml21_translation_helper.c  |  1 -  .../dml2/dml21/src/dml2_core/dml2_core_dcn4.c |  1 +
 .../dml21/src/dml2_core/dml2_core_utils.c     |  1 +
 .../drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h  |  1 +  .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h  |  1 +  .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c  | 22 +++++++++++++++----  .../amd/display/dc/hwss/dcn301/dcn301_init.h  |  4 ++--
 .../dc/link/protocols/link_dp_training.c      |  2 +-
 .../dc/resource/dcn401/dcn401_resource.c      |  3 ++-
 16 files changed, 56 insertions(+), 14 deletions(-)

--
2.37.3