riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI
Subsystems (4)
v3 cover riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI
New version of T-HEAD C920 implement a fully featured ACLINT[1] device (This core is used by Sophgo SG2044). This ACLINT device provides a SSWI field to support fast S-mode IPI. This SSWI device is like the MSWI device in CLINT/ACLINT, but for S-mode. The only thing is different from the draft is that the T-HEAD version SSWI needs to write 0 on the SSWI address to clear the IPI.
Add full support for T-HEAD C900 SSWI device.
[1] https://github.com/riscv/riscv-aclint
Changed from v1:
1. patch 2: use computed reg offset to avoid uncessary reg additions when setting/clearing irq.
2. patch 2: fix mulitple format issues and improve some comments.
3. patch 2: disable cpu irq when CPU is stopped.
Changed from v2:
1. patch 2: add SXSTATUS.CLINTEE check for T-HEAD cores.
2. patch 2: add select GENERIC_IRQ_IPI_MUX in Kconfig
Inochi Amaoto (3):
dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI
irqchip: add T-HEAD C900 ACLINT SSWI driver
riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers
.../thead,c900-aclint-sswi.yaml | 58 ++++++ arch/riscv/configs/defconfig | 1 + drivers/irqchip/Kconfig | 11 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-thead-c900-aclint-sswi.c | 176 ++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 6 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c
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2.47.0
PATCH v3 1/3 dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI
Sophgo SG2044 has a new version of T-HEAD C920, which implement a fully featured ACLINT device. This ACLINT has an extra SSWI field to support fast S-mode IPI.
Add necessary compatible string for the T-HEAD ACLINT sswi device.
--- .../thead,c900-aclint-sswi.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml new file +58 -0
@@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device + +maintainers: + - Inochi Amaoto <[email protected]> + +description: + The SSWI device is a part of the riscv ACLINT device. It provides + supervisor-level IPI functionality for a set of HARTs on a RISC-V + platform. It provides a register to set an IPI (SETSSIP) for each + HART connected to the SSWI device. + +properties: + compatible: + items: + - enum: + - sophgo,sg2044-aclint-sswi + - const: thead,c900-aclint-sswi + + reg: + maxItems: 1 + + "#interrupt-cells": + const: 0 + + interrupt-controller: true + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - "#interrupt-cells" + - interrupt-controller + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi"; + reg = <0x94000000 0x00004000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu1intc 1>, + <&cpu2intc 1>, + <&cpu3intc 1>, + <&cpu4intc 1>; + }; +...
Signature · 1 line
2.47.0
PATCH v3 2/3 irqchip: add T-HEAD C900 ACLINT SSWI driver
In reply to Inochi AmaotoAdd a driver for the T-HEAD C900 ACLINT SSWI device, which is an enhanced implementation of the RISC-V ACLINT SSWI specification. This device allows the system to send ipi via fast device interface.
--- drivers/irqchip/Kconfig | 11 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-thead-c900-aclint-sswi.c | 176 +++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 4 files changed, 189 insertions(+) create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c
drivers/irqchip/Kconfig +11 -0
@@ -611,6 +611,17 @@ config STARFIVE_JH8100_INTC If you don't know what to do here, say Y. +config THEAD_C900_ACLINT_SSWI + bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller" + depends on RISCV + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_IPI_MUX + help + This enables support for T-HEAD specific ACLINT SSWI device + support. + + If you don't know what to do here, say Y. + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
drivers/irqchip/Makefile +1 -0
@@ -101,6 +101,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI) += irq-riscv-aplic-msi.o obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_STARFIVE_JH8100_INTC) += irq-starfive-jh8100-intc.o +obj-$(CONFIG_THEAD_C900_ACLINT_SSWI) += irq-thead-c900-aclint-sswi.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o
drivers/irqchip/irq-thead-c900-aclint-sswi.c new file +176 -0
176 lines not on this page · raw message
include/linux/cpuhotplug.h +1 -0
@@ -147,6 +147,7 @@ enum cpuhp_state {CPUHP_AP_IRQ_EIOINTC_STARTING ,CPUHP_AP_IRQ_AVECINTC_STARTING ,CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING , +CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING ,CPUHP_AP_IRQ_RISCV_IMSIC_STARTING ,CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING , CPUHP_AP_ARM_MVEBU_COHERENCY,
Signature · 1 line
2.47.0
kernel test robot
build botRe: [PATCH v3 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver
kernel test robot noticed the following build warnings:
Hi Inochi,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tip/irq/core]
[also build test WARNING on sophgo/for-next sophgo/fixes tip/smp/core robh/for-next linus/master v6.12-rc4 next-20241018] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Inochi-Amaoto/dt-bindings-interrupt-controller-Add-Sophgo-SG2044-ACLINT-SSWI/20241020-201209 base: tip/irq/core patch link: https://lore.kernel.org/r/20241020121030.1012572-3-inochiama%40gmail.com patch subject: [PATCH v3 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver config: riscv-kismet-CONFIG_GENERIC_IRQ_IPI_MUX-CONFIG_THEAD_C900_ACLINT_SSWI-0-0 (https://download.01.org/0day-ci/archive/20241021/[email protected]/config) reproduce: (https://download.01.org/0day-ci/archive/20241021/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for GENERIC_IRQ_IPI_MUX when selected by THEAD_C900_ACLINT_SSWI
WARNING: unmet direct dependencies detected for GENERIC_IRQ_IPI_MUX
Depends on [n]: SMP [=n]
Selected by [y]:
- THEAD_C900_ACLINT_SSWI [=y] && RISCV [=y]
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
PATCH v3 3/3 riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers
In reply to Inochi AmaotoAdd support for T-HEAD C900 ACLINT SSWI irqchip.
--- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/riscv/configs/defconfig +1 -0
@@ -256,6 +256,7 @@ CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_VIRTIO=y CONFIG_PM_DEVFREQ=y CONFIG_IIO=y +CONFIG_THEAD_C900_ACLINT_SSWI=y CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m CONFIG_PHY_STARFIVE_JH7110_PCIE=m
Signature · 1 line
2.47.0