KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status

kvm_pmu_overflow_status() currently checks if the PMCs are enabled for evaluating the PMU overflow condition. However, ARM ARM D13.1.1 states that a global enable control (PMCR.E), PMOVSSET<n>, and PMINTENSET<n> are sufficent to consider that the overflow condition is met. Hence, ignore the check for PMCNTENSET<n>.

The bug was discovered while running the SBSA PMU test, which only sets PMCR.E, PMOVSSET<0>, PMINTENSET<0>, and expects an overflow interrupt.

---
 arch/arm64/kvm/pmu-emul.c | 1 -
 1 file changed, 1 deletion(-)

index ac36c438b8c1..3940fe893783 100644
@@ -342,7 +342,6 @@ static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
 
 	if ((kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) {
 		reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
-		reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 		reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
 	}
 

base-commit: adc218676eef25575469234709c2d87185ca223a

2.47.0.338.g60cca15819-goog

Hi Raghu,

Thanks for finding this!

It's more than sufficient, evaluating E, PMOVSSET<n>, and PMINTENSET<n> is the *only* correct implementation of the architecture.

Also, ARM ARM section numbering is subject to change between revisions, so it's always best to use a fully-qualified citation, like 'DDI0487K D13.1.1'.

So I may rewrite this as:

DDI0487K D13.1.1 describes the PMU overflow condition, which evaluates to true if any counter's global enable (PMCR_EL0.E), overflow flag (PMOVSSET_EL0[n]), and interrupt enable (PMINTENSET_EL1[n]) are all 1. Of note, this does not require a counter to be enabled (i.e. PMCNTENSET_EL0[n] = 1) to generate an overflow.

Align kvm_pmu_overflow_status() with the reality of the architecture and stop using PMCNTENSET_EL0 as part of the overflow condition.

We've got yet another bug lurking here as of 6.13, since the hypervisor range of counters isn't observing the correct global enable (MDCR_EL2.HPME).

Let me fiddle with this and send out a combined set of fixes.

We should be sending this to stable too.

Thanks,
Oliver