dt-bindings: cpufreq: Document support for Airoha EN7581 CPUFreq
Subsystems (2)
PATCH v4 1/2 dt-bindings: cpufreq: Document support for Airoha EN7581 CPUFreq
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
---
Changes v4:
- Add this patch
.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +259 -0
@@ -0,0 +1,259 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 CPUFreq + +maintainers: + - Christian Marangi <[email protected]> + +description: | + On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands + to ATF and no clocks are exposed to the OS. + + The SoC have performance state described by ID for each OPP, for this a + Power Domain is used that sets the performance state ID according to the + required OPPs defined in the CPU OPP tables. + +properties: + compatible: + const: airoha,en7581-cpufreq + + '#clock-cells': + const: 0 + + '#power-domain-cells': + const: 0 + + operating-points-v2: true + +required: + - compatible + - '#clock-cells' + - '#power-domain-cells' + - operating-points-v2 + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; + }; + + opp-7000000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; + }; + + opp-7500000000 { + opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; + }; + + opp-8000000000 { + opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; + }; + + opp-8500000000 { + opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; + }; + + opp-9000000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; + }; + + opp-9500000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; + }; + + opp-10000000000 { + opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; + }; + + opp-10500000000 { + opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; + }; + + opp-11000000000 { + opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; + }; + + opp-11500000000 { + opp-hz = /bits/ 64 <1150000000>; + required-opps = <&smcc_opp13>; + }; + + opp-12000000000 { + opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-cpu-smcc { + compatible = "operating-points-v2"; + + smcc_opp0: opp0 { + opp-level = <0>; + }; + + smcc_opp1: opp1 { + opp-level = <1>; + }; + + smcc_opp2: opp2 { + opp-level = <2>; + }; + + smcc_opp3: opp3 { + opp-level = <3>; + }; + + smcc_opp4: opp4 { + opp-level = <4>; + }; + + smcc_opp5: opp5 { + opp-level = <5>; + }; + + smcc_opp6: opp6 { + opp-level = <6>; + }; + + smcc_opp7: opp7 { + opp-level = <7>; + }; + + smcc_opp8: opp8 { + opp-level = <8>; + }; + + smcc_opp9: opp9 { + opp-level = <9>; + }; + + smcc_opp10: opp10 { + opp-level = <10>; + }; + + smcc_opp11: opp11 { + opp-level = <11>; + }; + + smcc_opp12: opp12 { + opp-level = <12>; + }; + + smcc_opp13: opp13 { + opp-level = <13>; + }; + + smcc_opp14: opp14 { + opp-level = <14>; + }; + }; + + cpufreq: cpufreq { + compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + };
Signature · 1 line
2.45.2
PATCH v4 2/2 cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Add simple CPU Freq driver for Airoha EN7581 SoC that control CPU frequency scaling with SMC APIs and register a generic "cpufreq-dt" device.
CPUFreq driver registers a get-only clock to get the current global CPU frequency from SMC and a Power Domain to configure the performance state for each OPP to apply the requested frequency from cpufreq-dt. This is needed as SMC use index instead of raw frequency.
All CPU share the same frequency and can't be controlled independently. Current shared CPU frequency is returned by the related SMC command.
Add SoC compatible to cpufreq-dt-plat block list as a dedicated cpufreq driver is needed with OPP v2 nodes declared in DTS.
---
Changes v4:
- Rework to clk-only + PM set_performance_state implementation Changes v3:
- Adapt to new cpufreq-dt APIs
- Register cpufreq-dt instead of custom freq driver Changes v2:
- Fix kernel bot error with missing slab.h and bitfield.h header
- Limit COMPILE_TEST to ARM64 due to smcc 1.2
drivers/cpufreq/Kconfig.arm | 9 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/airoha-cpufreq.c | 222 +++++++++++++++++++++++++++ drivers/cpufreq/cpufreq-dt-platdev.c | 2 + 4 files changed, 234 insertions(+) create mode 100644 drivers/cpufreq/airoha-cpufreq.c
drivers/cpufreq/Kconfig.arm +9 -0
@@ -15,6 +15,15 @@ config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM To compile this driver as a module, choose M here: the module will be called sun50i-cpufreq-nvmem. +config ARM_AIROHA_SOC_CPUFREQ + tristate "Airoha EN7581 SoC CPUFreq support" + depends on ARCH_AIROHA || (COMPILE_TEST && ARM64) + select PM_OPP + select PM_GENERIC_DOMAINS + default ARCH_AIROHA + help + This adds the CPUFreq driver for Airoha EN7581 SoCs. + config ARM_APPLE_SOC_CPUFREQ tristate "Apple Silicon SoC CPUFreq support" depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
drivers/cpufreq/Makefile +1 -0
@@ -52,6 +52,7 @@ obj-$(CONFIG_X86_AMD_FREQ_SENSITIVITY) += amd_freq_sensitivity.o ################################################################################## # ARM SoC drivers +obj-$(CONFIG_ARM_AIROHA_SOC_CPUFREQ) += airoha-cpufreq.o obj-$(CONFIG_ARM_APPLE_SOC_CPUFREQ) += apple-soc-cpufreq.o obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o
drivers/cpufreq/airoha-cpufreq.c new file +222 -0
222 lines not on this page · raw message
drivers/cpufreq/cpufreq-dt-platdev.c +2 -0
@@ -103,6 +103,8 @@ static const struct of_device_id allowlist[] __initconst = {* platforms using "operating-points-v2" property. */ static const struct of_device_id blocklist[]__initconst = { + { .compatible ="airoha,en7581" , }, + { .compatible ="allwinner,sun50i-h6" , }, { .compatible ="allwinner,sun50i-h616" , }, { .compatible ="allwinner,sun50i-h618" , },
Signature · 1 line
2.45.2
Re: [PATCH v4 2/2] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
hello,
drivers/cpufreq/airoha-cpufreq.c line 212
Quoted 3 lines · Christian Marangi
drivers/cpufreq/airoha-cpufreq.c new file +3
-0+static struct platform_driver airoha_cpufreq_driver = { + .probe = airoha_cpufreq_probe, + .remove_new = airoha_cpufreq_remove,
That doesn't build on top of mainline since commit e70140ba0d2b ("Get rid of 'remove_new' relic from platform driver struct")
Please use .remove.
Best regards
Uwe
Re: [PATCH v4 2/2] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Quoted 11 lines · Uwe Kleine-König
hello,
drivers/cpufreq/airoha-cpufreq.c line 212
Quoted 3 lines · Christian Marangi
drivers/cpufreq/airoha-cpufreq.c new file +3
-0+static struct platform_driver airoha_cpufreq_driver = { + .probe = airoha_cpufreq_probe, + .remove_new = airoha_cpufreq_remove,That doesn't build on top of mainline since commit
e70140ba0d2b("Get rid of 'remove_new' relic from platform driver struct")Please use .remove.
Hi Uwe,
I rebased this on top of next and still compiled but yes sorry it's a leftover from testing this also on my OpenWrt buildroot. (seems the commit still needs to be merged)
Maybe you can point me what branch/repository I should target?
Did you notice other problem with the changes? I notice the PD implementation changed recently.
Signature · 1 line
Ansuel
Re: [PATCH v4 2/2] cpufreq: airoha: Add EN7581 CPUFreq SMCCC driver
Hello,
Quoted 10 lines · Christian Marangi
Quoted 9 lines · Uwe Kleine-König
hello,
drivers/cpufreq/airoha-cpufreq.c line 212
Quoted 3 lines · Christian Marangi
drivers/cpufreq/airoha-cpufreq.c new file +3
-0+static struct platform_driver airoha_cpufreq_driver = { + .probe = airoha_cpufreq_probe, + .remove_new = airoha_cpufreq_remove,That doesn't build on top of mainline since commit
e70140ba0d2b("Get rid of 'remove_new' relic from platform driver struct")
Quoted 6 lines
Quoted 1 line
Please use .remove.
Hi Uwe,
I rebased this on top of next and still compiled but yes sorry it's a leftover from testing this also on my OpenWrt buildroot. (seems the commit still needs to be merged)
The relevant commits are:
- Since v6.3-rc1~106^2~108 ("platform: Provide a remove callback that returns no value") there is .remove_new()
- Since v6.11-rc1~49^2~37^2 ("platform: Make platform_driver::remove() return void") the prototype of .remove() changed to return void
- Since e70140ba0d2b ("Get rid of 'remove_new' relic from platform driver struct") (which is currently only in Linus Torvalds repo and probably in next starting today) .remove_new is gone.
Best regards
Uwe
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0
[...]
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; +
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";
Nitpick: Perhaps clarify the name to be "perf" or "cpu_perf", to indicate it's a power-domain with performance scaling support.
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 63
Quoted 4 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +4
-0+ next-level-cache = <&l2>; + #cooling-cells = <2>; + }; +
[...]
Other than the very minor thing above, feel free to add:
Kind regards
Uffe
Quoted 43 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 15 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +15
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>;
Quoted 9 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 5 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +5
-0+ enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.
Will change to cpu_perf. Thanks a lot for the review!
Quoted 13 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 63
Quoted 4 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +4
-0+ next-level-cache = <&l2>; + #cooling-cells = <2>; + }; +[...]
Other than the very minor thing above, feel free to add:
Reviewed-by Ulf Hansson <[email protected]>Kind regards
Uffe
Signature · 1 line
Ansuel
Rob Herring
maintainerQuoted 54 lines · Christian Marangi
Quoted 43 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 15 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +15
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>;Quoted 9 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 5 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +5
-0+ enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.
Quoted 1 line
Will change to
cpu_perf. Thanks a lot for the review!
Is that defined in arm/cpus.yaml? No.
The current choices are perf or psci though those aren't enforced (yet). Or nothing which is my preference if there is only 1 power domain.
Rob
Quoted 55 lines · Rob Herring
Quoted 54 lines · Christian Marangi
Quoted 52 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; +Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.
Quoted 7 lines
Quoted 1 line
Will change to
cpu_perf. Thanks a lot for the review!Is that defined in
arm/cpus.yaml? No.The current choices are perf or psci though those aren't enforced (yet). Or nothing which is my preference if there is only 1 power domain.
I would also prefer not having to define the names property but I guess that is mandatory for the PD APIs? Maybe Ulf can confirm.
Signature · 1 line
Ansuel
Quoted 59 lines · Christian Marangi
Quoted 57 lines · Rob Herring
Quoted 55 lines · Christian Marangi
Quoted 43 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 15 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +15
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>;Quoted 9 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 5 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +5
-0+ enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.Will change to
cpu_perf. Thanks a lot for the review!
Quoted 8 lines
Quoted 5 lines
Is that defined in
arm/cpus.yaml? No.The current choices are perf or psci though those aren't enforced (yet). Or nothing which is my preference if there is only 1 power domain.
I would also prefer not having to define the names property but I guess that is mandatory for the PD APIs? Maybe Ulf can confirm.
No, that's not needed.
dev_pm_domain_attach() attaches a single PM domain, without requiring a name.
But as stated in the other thread, to be future proof, I would suggest using a name already at this point. Even if it's not required.
Kind regards
Uffe
Quoted 56 lines · Rob Herring
Quoted 54 lines · Christian Marangi
Quoted 52 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; +Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.
Quoted 6 lines
Quoted 1 line
Will change to
cpu_perf. Thanks a lot for the review!Is that defined in
arm/cpus.yaml? No.The current choices are perf or psci though those aren't enforced (yet). Or nothing which is my preference if there is only 1 power domain.
Right. It's not really clear in arm/cpus.yaml what name to use for a perf domain, except for "perf" for SCMI.
If we want to move towards some alignment, perhaps we should update the DT doc to make "perf" the common suggestion? I can send a patch if you think it makes sense?
Even if there is only 1 power-domain at this point, we never know if another one turns up later, for whatever reasons. That said, isn't it better to be specific about a name, already at this point?
Kind regards
Uffe
Quoted 67 lines · Ulf Hansson
Quoted 56 lines · Rob Herring
Quoted 54 lines · Christian Marangi
Quoted 52 lines · Ulf Hansson
Quoted 24 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +0
-0[...]
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; +Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 59
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd";Nitpick: Perhaps clarify the name to be "perf" or "
cpu_perf", to indicate it's a power-domain with performance scaling support.Quoted 6 lines
Quoted 1 line
Will change to
cpu_perf. Thanks a lot for the review!Is that defined in
arm/cpus.yaml? No.The current choices are perf or psci though those aren't enforced (yet). Or nothing which is my preference if there is only 1 power domain.
Right. It's not really clear in
arm/cpus.yamlwhat name to use for a perf domain, except for "perf" for SCMI.
Quoted 8 lines
If we want to move towards some alignment, perhaps we should update the DT doc to make "perf" the common suggestion? I can send a patch if you think it makes sense?
Even if there is only 1 power-domain at this point, we never know if another one turns up later, for whatever reasons. That said, isn't it better to be specific about a name, already at this point?
Ok to summarize
- cpu node: use perf for PD
- cpufreq node change node name to power-domain
- Fix OPP format (already done)
Did I miss anything? It's strange these case weren't catch by dt_binding_check. Sorry, wasn't aware of all these common name.
Signature · 1 line
Ansuel
Viresh Kumar
maintainerQuoted 8 lines · Christian Marangi
Ok to summarize
- cpu node: use perf for PD
- cpufreq node change node name to power-domain
- Fix OPP format (already done)Did I miss anything? It's strange these case weren't catch by
dt_binding_check. Sorry, wasn't aware of all these common name.
Please also run "scripts/checkpatch.pl --strict" if you haven't already, I think I saw some inconsistencies in the second patch.
Signature · 1 line
viresh
Rob Herring (Arm)
maintainerQuoted 9 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Quoted 9 lines
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.example.dtb: /: 'compatible' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.example.dtb: /: 'model' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.example.dtb: opp-table-cpu-smcc: $nodename:0: 'opp-table-cpu-smcc' does not match '^opp-table(-[a-z0-9]+)?$'
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.example.dtb: opp-table-cpu-smcc: Unevaluated properties are not allowed ('opp0', 'opp1', 'opp10', 'opp11', 'opp12', 'opp13', 'opp14', 'opp2', 'opp3', 'opp4', 'opp5', 'opp6', 'opp7', 'opp8', 'opp9' were unexpected)
from schema $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Viresh Kumar
maintainer+Ulf,
Quoted 127 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +103
-0@@ -0,0 +1,259 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 CPUFreq + +maintainers: + - Christian Marangi <[email protected]> + +description: | + On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands + to ATF and no clocks are exposed to the OS. + + The SoC have performance state described by ID for each OPP, for this a + Power Domain is used that sets the performance state ID according to the + required OPPs defined in the CPU OPP tables. + +properties: + compatible: + const: airoha,en7581-cpufreq + + '#clock-cells': + const: 0 + + '#power-domain-cells': + const: 0 + + operating-points-v2: true + +required: + - compatible + - '#clock-cells' + - '#power-domain-cells' + - operating-points-v2 + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>;
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 113
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>;
In your case I think you can simply mention opp-level here itself and remove the OPP table for the genpd. Right Ulf ?
Quoted 64 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +64
-0+ }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; + }; + + opp-7000000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; + }; + + opp-7500000000 { + opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; + }; + + opp-8000000000 { + opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; + }; + + opp-8500000000 { + opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; + }; + + opp-9000000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; + }; + + opp-9500000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; + }; + + opp-10000000000 { + opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; + }; + + opp-10500000000 { + opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; + }; + + opp-11000000000 { + opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; + }; + + opp-11500000000 { + opp-hz = /bits/ 64 <1150000000>;
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 187
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ required-opps = <&smcc_opp13>; + }; + + opp-12000000000 { + opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-cpu-smcc {
So this won't be required I guess.
Quoted 54 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +54
-0+ compatible = "operating-points-v2"; + + smcc_opp0: opp0 { + opp-level = <0>; + }; + + smcc_opp1: opp1 { + opp-level = <1>; + }; + + smcc_opp2: opp2 { + opp-level = <2>; + }; + + smcc_opp3: opp3 { + opp-level = <3>; + }; + + smcc_opp4: opp4 { + opp-level = <4>; + }; + + smcc_opp5: opp5 { + opp-level = <5>; + }; + + smcc_opp6: opp6 { + opp-level = <6>; + }; + + smcc_opp7: opp7 { + opp-level = <7>; + }; + + smcc_opp8: opp8 { + opp-level = <8>; + }; + + smcc_opp9: opp9 { + opp-level = <9>; + }; + + smcc_opp10: opp10 { + opp-level = <10>; + }; + + smcc_opp11: opp11 { + opp-level = <11>; + }; + + smcc_opp12: opp12 { + opp-level = <12>; + }; +
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 251
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +10
-0+ smcc_opp13: opp13 { + opp-level = <13>; + }; + + smcc_opp14: opp14 { + opp-level = <14>; + }; + }; + + cpufreq: cpufreq {
And I would name it like a genpd, instead of cpufreq. But I am not sure what's the right name is..
Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +8
-0+ compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + };Signature · 1 line
2.45.2
Signature · 1 line
viresh
Quoted 136 lines · Viresh Kumar
+Ulf,
Quoted 132 lines · Christian Marangi
Document required property for Airoha EN7581 CPUFreq .
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands to ATF and no clocks are exposed to the OS.
The SoC have performance state described by ID for each OPP, for this a Power Domain is used that sets the performance state ID according to the required OPPs defined in the CPU OPP tables.
Signed-off-by Christian Marangi <[email protected]>---
Changes v4:
- Add this patch.../cpufreq/airoha,en7581-cpufreq.yaml | 259 ++++++++++++++++++ 1 file changed, 259 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yamlDocumentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +108
-0@@ -0,0 +1,259 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 CPUFreq + +maintainers: + - Christian Marangi <[email protected]> + +description: | + On newer Airoha SoC, CPU Frequency is scaled indirectly with SMCCC commands + to ATF and no clocks are exposed to the OS. + + The SoC have performance state described by ID for each OPP, for this a + Power Domain is used that sets the performance state ID according to the + required OPPs defined in the CPU OPP tables. + +properties: + compatible: + const: airoha,en7581-cpufreq + + '#clock-cells': + const: 0 + + '#power-domain-cells': + const: 0 + + operating-points-v2: true + +required: + - compatible + - '#clock-cells' + - '#power-domain-cells' + - operating-points-v2 + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clocks = <&cpufreq>; + clock-names = "cpu"; + power-domains = <&cpufreq>; + power-domain-names = "cpu_pd"; + next-level-cache = <&l2>; + #cooling-cells = <2>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2";
Quoted 8 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 113
Quoted 5 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +5
-0+ opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&smcc_opp0>;In your case I think you can simply mention opp-level here itself and remove the OPP table for the genpd. Right Ulf ?
No, that would not be the correct thing to do, I think.
The power-domain described here is modeling a performance-domain, hence it needs an opp-table associated with it.
Quoted 69 lines
Quoted 69 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +68
-0+ }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + required-opps = <&smcc_opp1>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&smcc_opp2>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&smcc_opp3>; + }; + + opp-7000000000 { + opp-hz = /bits/ 64 <700000000>; + required-opps = <&smcc_opp4>; + }; + + opp-7500000000 { + opp-hz = /bits/ 64 <750000000>; + required-opps = <&smcc_opp5>; + }; + + opp-8000000000 { + opp-hz = /bits/ 64 <800000000>; + required-opps = <&smcc_opp6>; + }; + + opp-8500000000 { + opp-hz = /bits/ 64 <850000000>; + required-opps = <&smcc_opp7>; + }; + + opp-9000000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&smcc_opp8>; + }; + + opp-9500000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&smcc_opp9>; + }; + + opp-10000000000 { + opp-hz = /bits/ 64 <1000000000>; + required-opps = <&smcc_opp10>; + }; + + opp-10500000000 { + opp-hz = /bits/ 64 <1050000000>; + required-opps = <&smcc_opp11>; + }; + + opp-11000000000 { + opp-hz = /bits/ 64 <1100000000>; + required-opps = <&smcc_opp12>; + }; + + opp-11500000000 { + opp-hz = /bits/ 64 <1150000000>; + required-opps = <&smcc_opp13>; + }; + + opp-12000000000 {
Quoted 8 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 187
Quoted 6 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +6
-0+ opp-hz = /bits/ 64 <1200000000>; + required-opps = <&smcc_opp14>; + }; + }; + + cpu_smcc_opp_table: opp-table-cpu-smcc {So this won't be required I guess.
See above, I think the OPP table here is the correct way to describe it.
Quoted 60 lines
Quoted 60 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +59
-0+ compatible = "operating-points-v2"; + + smcc_opp0: opp0 { + opp-level = <0>; + }; + + smcc_opp1: opp1 { + opp-level = <1>; + }; + + smcc_opp2: opp2 { + opp-level = <2>; + }; + + smcc_opp3: opp3 { + opp-level = <3>; + }; + + smcc_opp4: opp4 { + opp-level = <4>; + }; + + smcc_opp5: opp5 { + opp-level = <5>; + }; + + smcc_opp6: opp6 { + opp-level = <6>; + }; + + smcc_opp7: opp7 { + opp-level = <7>; + }; + + smcc_opp8: opp8 { + opp-level = <8>; + }; + + smcc_opp9: opp9 { + opp-level = <9>; + }; + + smcc_opp10: opp10 { + opp-level = <10>; + }; + + smcc_opp11: opp11 { + opp-level = <11>; + }; + + smcc_opp12: opp12 { + opp-level = <12>; + }; + + smcc_opp13: opp13 { + opp-level = <13>; + }; + + smcc_opp14: opp14 {
Quoted 8 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml line 251
Quoted 5 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +5
-0+ opp-level = <14>; + }; + }; + + cpufreq: cpufreq {And I would name it like a genpd, instead of cpufreq. But I am not sure what's the right name is..
Good point!
The node name should follow Documentation/devicetree/bindings/power/power-domain.yaml, which states:
pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
Quoted 12 lines
Quoted 11 lines
Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml new file +8
-1+ compatible = "airoha,en7581-cpufreq"; + + operating-points-v2 = <&cpu_smcc_opp_table>; + + #power-domain-cells = <0>; + #clock-cells = <0>; + }; + }; --2.45.2
Kind regards
Uffe