arm64: dts: qcom: sc8280xp: correct usb phy power supply

On this platform, according to dsdt tables, usb{0,1} phy consume the following regulators. usb2 phy should be corrected also, usb2 in dsdt is a little complicated, so correct usb{0,1} only for now.

usb0 usb1 voltage consumer
hsphy:

	l1c	l1c	1.8v	vdda18-supply
	l9d	l4b	0.912v	vdda-pll-supply
	l7d	l13c	3.072v	vdda33-supply
qmpphy:
	l4d	l3b	1.2v	vdda-phy-supply
	l6d	l6b	0.88v	vdda-pll-supply

base-commit: 2b88851f583d3c4e40bcd40cfe1965241ec229dd

---
 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts                 | 8 ++++----
 arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts      | 8 ++++----
 .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 ++++----
 arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts    | 8 ++++----
 arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 4 ++--
 5 files changed, 18 insertions(+), 18 deletions(-)

index 75adaa19d..ad61bb206 100644
@@ -815,8 +815,8 @@ &usb_0_hsphy {
 };
 
 &usb_0_qmpphy {
-	vdda-phy-supply = <&vreg_l9d>;
-	vdda-pll-supply = <&vreg_l4d>;
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
 
 	orientation-switch;
 

@@ -852,8 +852,8 @@ &usb_1_hsphy {
 };
 
 &usb_1_qmpphy {
-	vdda-phy-supply = <&vreg_l4b>;
-	vdda-pll-supply = <&vreg_l3b>;
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
 
 	orientation-switch;
 

index 09b95f89e..e46f24c3f 100644
@@ -1013,8 +1013,8 @@ &usb_0_hsphy {
 };
 
 &usb_0_qmpphy {
-	vdda-phy-supply = <&vreg_l9d>;
-	vdda-pll-supply = <&vreg_l4d>;
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
 
 	orientation-switch;
 

@@ -1042,8 +1042,8 @@ &usb_1_hsphy {
 };
 
 &usb_1_qmpphy {
-	vdda-phy-supply = <&vreg_l4b>;
-	vdda-pll-supply = <&vreg_l3b>;
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
 
 	orientation-switch;
 

index f3190f408..5bf43050d 100644
@@ -1363,8 +1363,8 @@ &usb_0_hsphy {
 };
 
 &usb_0_qmpphy {
-	vdda-phy-supply = <&vreg_l9d>;
-	vdda-pll-supply = <&vreg_l4d>;
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
 
 	orientation-switch;
 

@@ -1400,8 +1400,8 @@ &usb_1_hsphy {
 };
 
 &usb_1_qmpphy {
-	vdda-phy-supply = <&vreg_l4b>;
-	vdda-pll-supply = <&vreg_l3b>;
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
 
 	orientation-switch;
 

index ae5daeac8..179c944a6 100644
@@ -769,8 +769,8 @@ &usb_0_hsphy {
 };
 
 &usb_0_qmpphy {
-	vdda-phy-supply = <&vreg_l9d>;
-	vdda-pll-supply = <&vreg_l4d>;
+	vdda-phy-supply = <&vreg_l4d>;
+	vdda-pll-supply = <&vreg_l6d>;
 
 	orientation-switch;
 

@@ -806,8 +806,8 @@ &usb_1_hsphy {
 };
 
 &usb_1_qmpphy {
-	vdda-phy-supply = <&vreg_l4b>;
-	vdda-pll-supply = <&vreg_l3b>;
+	vdda-phy-supply = <&vreg_l3b>;
+	vdda-pll-supply = <&vreg_l6b>;
 
 	orientation-switch;
 

index fa9d94105..d73b45d54 100644
@@ -1003,7 +1003,7 @@ &usb_0_hsphy {
 
 &usb_0_qmpphy {
 	vdda-phy-supply = <&vreg_l4d>;
-	vdda-pll-supply = <&vreg_l9d>;
+	vdda-pll-supply = <&vreg_l6d>;
 
 	orientation-switch;
 

@@ -1040,7 +1040,7 @@ &usb_1_hsphy {
 
 &usb_1_qmpphy {
 	vdda-phy-supply = <&vreg_l3b>;
-	vdda-pll-supply = <&vreg_l4b>;
+	vdda-pll-supply = <&vreg_l6b>;
 
 	orientation-switch;
 

2.47.1

Looking at the CRD schematics, it should instead be:

USB0 USB1 VOLT NAME
L1B L8D 0.9ish PHY
L4D L4D 1.2 PLL

I'm hoping I'm reading those right, it's not super obvious

Konrad

Yes, right.

Yours is correspond to usb2 qmpphy(internal usb)

this is from sc8280xp-crd:

&usb_2_qmpphy0 {
        vdda-phy-supply = <&vreg_l1b>;
        vdda-pll-supply = <&vreg_l4d>;

        status = "okay";
};

&usb_2_qmpphy1 {
        vdda-phy-supply = <&vreg_l8d>;
        vdda-pll-supply = <&vreg_l4d>;

        status = "okay";
};

I had checked many dsdt tables of sc8280xp-based devices, they are

Name (LPCC, Package (0x07)
{
...
Package (0x08)

{
	"\\_SB.URS0.USB0",
	...
	"PPP_RESOURCE_ID_LDO1_C" // 1.8v
	...
	"PPP_RESOURCE_ID_LDO9_D" // 0.912v
	...
	"PPP_RESOURCE_ID_LDO7_D" // 3.072v
	...
	"PPP_RESOURCE_ID_LDO4_D" // 1.2v
	...
	"PPP_RESOURCE_ID_LDO6_D" // 0.88v
	...
}
...
Package (0x08)
{
	"\\_SB.URS1.USB1",
	...
	"PPP_RESOURCE_ID_LDO1_C" // 1.8v
	...
	"PPP_RESOURCE_ID_LDO4_B" // 0.912v
	...
	"PPP_RESOURCE_ID_LDO13_C" // 3.072v
	...
	"PPP_RESOURCE_ID_LDO3_B" // 1.2v
	...
	"PPP_RESOURCE_ID_LDO6_B" // 0.88v
	...
}

...
}

On many platforms, such as sm8350-hdk, sc8180x-primus, x1e80100-crd, which also support qmp phy, their PHY consumes a 1.2v vreg, their PLL consumes a 0.88v(approx) vreg. So I wirite this patch.

Best wishes,
Pengyu

Can confirm that this works on blackrock and x13s. And I went a different route when I tried to verify vregs for blackrock and noticed that the vdd voltages didn't match the layer of logic schematic in the dwc3 block (some TI documentation), so I switched them already for blackrock.

with best regards

Jens

I think they might take the power sequence into account when they were introducing the devices, vdda-phy(~0.9v) first and vdda-pll(1.2v) later in the upstream while vdd(0.912v) first and core(1.2v) later in the downstream. BTW, the DSDT is unreliable. On my platform, it describes that several components are consuming several LDOs, but these components work well with these LDOs manually disabled via rpmh.

Best wishes,
Pengyu

Hmm looks like schematics would trump these speculations. Maybe wait until this can be confirmed.

My previous reply was wrong.

via CRD8280X schematics:

                USB0    USB1    USB2    USB3    USB4    USB5
HSPHY   0p9     L9D     L4B     L1B     L8D     [L10D   L10D]
HSPHY   1p8     L1C     L1C     [L1C    L1C]    [L8C    L8C]
HSPHY   3p1     L7D     L13C    [L7D    L7D]    [L2D    L2D]

SSPHY   0p9     L9D     L4B     L1B     L8D     N/A     N/A
SSPHY   1p2     L4D     L3B     L4D     L4D     N/A     N/A

USB0 - usb@a600000
USB1 - usb@a800000
USB2/3 - usb@a400000 ports 0/1
USB4/5 - usb@a400000 ports 2/3

Regulators in square brackets share a single input pin on the SoC

Konrad