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arm64: dts: socfpga: agilex5: fix gpio0 address

PATCH Superseded [email protected] 2 participants 3 messages Feb 12, 2025

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PATCH 1/1 arm64: dts: socfpga: agilex5: fix gpio0 address

From: Niravkumar L Rabara <[email protected]>

Fix gpio0 controller address for Agilex5.

Fixes 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id")
Cc [email protected]
Signed-off-by Niravkumar L Rabara <[email protected]>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -1
index 51c6e19e40b8..9e4ef24c8318 100644
@@ -222,7 +222,7 @@ i3c1: i3c@10da1000 {
 			status = "disabled";
 		};
 
-		gpio0: gpio@ffc03200 {
+		gpio0: gpio@10c03200 {
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc03200 0x100>;
 			#address-cells = <1>;
Signature · 1 line
2.25.1
#1 lore raw
Quoted 3 lines · On 12/02/2025 11:01, [email protected] wrote:

From: Niravkumar L Rabara <[email protected]>

Fix gpio0 controller address for Agilex5.

How do you fix it exactly?

Quoted 13 lines
Fixes 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and spi dma handshake id")
Cc [email protected]
Signed-off-by Niravkumar L Rabara <[email protected]>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
index 51c6e19e40b8..9e4ef24c8318 100644

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi i3c1: i3c@10da1000 { · line 225

Quoted 5 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -1
@@ -222,7 +222,7 @@ i3c1: i3c@10da1000 {
 			status = "disabled";
 		};
 
-		gpio0: gpio@ffc03200 {
+		gpio0: gpio@10c03200 {

I see now warning. Are you sure you tested it according to maintainer-soc-clean-dts profile?

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi i3c1: i3c@10da1000 { · line 228

Quoted 3 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
 			compatible = "snps,dw-apb-gpio";
 			reg = <0xffc03200 0x100>;
 			#address-cells = <1>;

Best regards,
Krzysztof

author
#2 lore raw
Quoted 13 lines

-----Original Message-----
From: Krzysztof Kozlowski <[email protected]>
Sent: Wednesday, 12 February, 2025 11:32 PM
To: Rabara, Niravkumar L <[email protected]>; Dinh Nguyen <[email protected]>; Rob Herring <[email protected]>; Krzysztof Kozlowski <[email protected]>; Conor Dooley <[email protected]>; [email protected]; [email protected]; linux- [email protected]
Cc: [email protected]
Subject: Re: [PATCH] arm64: dts: socfpga: agilex5: fix gpio0 address

Quoted 6 lines
Quoted 3 lines · On 12/02/2025 11:01, [email protected] wrote:

From: Niravkumar L Rabara <[email protected]>

Fix gpio0 controller address for Agilex5.

How do you fix it exactly?

gpio0 address is incorrect here. 0xffc03200 address is for Agilex7 not for Agilex5. 0x10c03200 is correct address for Agilex5.

I will update the commit message.
"Fix incorrect gpio0 address for Agilex5".

Quoted 19 lines
Quoted 19 lines
Fixes 3f7c869e143a ("arm64: dts: socfpga: agilex5: Add gpio0 node and

spi dma handshake id")

Cc [email protected]
Signed-off-by Niravkumar L Rabara <[email protected]>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
index 51c6e19e40b8..9e4ef24c8318 100644
@@ -222,7 +222,7 @@ i3c1: i3c@10da1000 {
 			status = "disabled";
 		};
Quoted 6 lines

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi i3c1: i3c@10da1000 { · line 225

Quoted 2 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -1
-		gpio0: gpio@ffc03200 {
+		gpio0: gpio@10c03200 {

I see now warning. Are you sure you tested it according to maintainer-soc- clean-dts profile?

My bad, I have submitted incorrect patch.
It supposes to have these changes, I will update in v2.

- gpio0: gpio@ffc03200 {

+               gpio0: gpio@10c03200 {
                        compatible = "snps,dw-apb-gpio";

- reg = <0xffc03200 0x100>;
+ reg = <0x10c03200 0x100>;

Thanks,
Nirav