arm64: dts: nuvoton: Add EDAC controller
Subsystems (2)
PATCH 1/1 arm64: dts: nuvoton: Add EDAC controller
We have the driver support but need a common node for all the 8xx platforms that contain this device.
--- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +7 -0
@@ -56,6 +56,13 @@ clk: rstc: reset-controller@f0801000 { #clock-cells = <1>; }; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm845-memory-controller"; + reg = <0x0 0xf0824000 0x0 0x2000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>;
Signature · 1 line
2.49.0.604.gff1f9ca942-goog
Quoted 5 lines · William A. Kennington III
We have the driver support but need a common node for all the 8xx platforms that contain this device.
Signed-off-by William A. Kennington III <[email protected]>---
You just sent it, so this is v2? If so, then use v2 in subject (see other patches) and provide changelog under ---.
Quoted 8 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0
-0
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 63
Quoted 8 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5
-0@@ -56,6 +56,13 @@ clk: rstc: reset-controller@f0801000 { #clock-cells = <1>; }; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm845-memory-controller"; + reg = <0x0 0xf0824000 0x0 0x2000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled";
Why is this disabled? What resources are missing?
Best regards,
Krzysztof
Quoted 22 lines · Krzysztof Kozlowski
Quoted 5 lines · William A. Kennington III
We have the driver support but need a common node for all the 8xx platforms that contain this device.
Signed-off-by William A. Kennington III <[email protected]>---
You just sent it, so this is v2? If so, then use v2 in subject (see other patches) and provide changelog under ---.
Quoted 11 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0
-0@@ -56,6 +56,13 @@ clk: rstc: reset-controller@f0801000 { #clock-cells = <1>; };
Quoted 8 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 63
Quoted 5 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5
-0+ mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm845-memory-controller"; + reg = <0x0 0xf0824000 0x0 0x2000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled";Why is this disabled? What resources are missing?
I was avoiding enabling anything would not be used in the most minimal kernel configuration (Kdump). Anyone actually using the EDAC data from the memory controller could enable it. The np]cm7xx common dts also has this node disabled, so it would be consistent with that SoC.
Quoted 3 lines
Best regards,
Krzysztof
Quoted 32 lines · William Kennington
Quoted 22 lines · Krzysztof Kozlowski
Quoted 5 lines · William A. Kennington III
We have the driver support but need a common node for all the 8xx platforms that contain this device.
Signed-off-by William A. Kennington III <[email protected]>---
You just sent it, so this is v2? If so, then use v2 in subject (see other patches) and provide changelog under ---.
Quoted 11 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0
-0@@ -56,6 +56,13 @@ clk: rstc: reset-controller@f0801000 { #clock-cells = <1>; };Quoted 8 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 63
Quoted 5 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5
-0+ mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm845-memory-controller"; + reg = <0x0 0xf0824000 0x0 0x2000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled";Why is this disabled? What resources are missing?
Quoted 4 lines
I was avoiding enabling anything would not be used in the most minimal kernel configuration (Kdump). Anyone actually using the EDAC data from the memory controller could enable it. The np]cm7xx common dts also has this node disabled, so it would be consistent with that SoC.
DTS is nowwhere relatd to your kernel configuration, so that's wrong assumption and wrong goals. DTSI should have disabled only devices which need board-level resources. It seems not the case here, so drop it.
Best regards,
Krzysztof