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clk: meson-g12a: add missing fclk_div2 to spicc

PATCH Applied Da Xue 4 participants 5 messages May 12, 2025 – May 15, 2025

Subsystems (4)
Stable branch Arm/Amlogic Meson SoC support Common clk Arm/Amlogic Meson SoC clock framework
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Da Xue

author
#0 lore raw

PATCH v3 1/1 clk: meson-g12a: add missing fclk_div2 to spicc

SPICC is missing fclk_div2 which causes the spicc module to output sclk at 2.5x the expected rate. Adding the missing fclk_div2 resolves this.

Fixes a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc <[email protected]> # 6.1
Signed-off-by Da Xue <[email protected]>

---
Changelog:

v2 -> v3: remove gp0
v1 -> v2: add Fixes as an older version of the patch was sent as v1

---
 drivers/clk/meson/g12a.c | 1 +
 1 file changed, 1 insertion(+)
drivers/clk/meson/g12a.c +1 -0
index 4f92b83965d5a..b72eebd0fa474 100644
@@ -4099,6 +4099,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
 	{ .hw = &g12a_clk81.hw },
 	{ .hw = &g12a_fclk_div4.hw },
 	{ .hw = &g12a_fclk_div3.hw },
+	{ .hw = &g12a_fclk_div2.hw },
 	{ .hw = &g12a_fclk_div5.hw },
 	{ .hw = &g12a_fclk_div7.hw },
 };
Signature · 1 line
2.39.5
maintainer
#2 lore raw
In reply to Da Xue
Quoted 2 lines · Da Xue

SPICC is missing fclk_div2 which causes the spicc module to output sclk at 2.5x the expected rate. Adding the missing fclk_div2 resolves this.

I had to re-read that a few times to get the what the actual problem is. If you don't mind, I'll amend the commit message with

'''
SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes are wrong on this clock. This causes the spicc module to output sclk at 2.5x the expected rate when clock index 3 is picked.

Adding the missing fclk_div2 resolves this.
'''

Is that OK with you Da ?

Quoted 25 lines
Fixes a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc <[email protected]> # 6.1
Signed-off-by Da Xue <[email protected]>

---
Changelog:

v2 -> v3: remove gp0
v1 -> v2: add Fixes as an older version of the patch was sent as v1

---
 drivers/clk/meson/g12a.c | 1 +
 1 file changed, 1 insertion(+)
drivers/clk/meson/g12a.c +1 -0
index 4f92b83965d5a..b72eebd0fa474 100644
@@ -4099,6 +4099,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
 	{ .hw = &g12a_clk81.hw },
 	{ .hw = &g12a_fclk_div4.hw },
 	{ .hw = &g12a_fclk_div3.hw },
+	{ .hw = &g12a_fclk_div2.hw },
 	{ .hw = &g12a_fclk_div5.hw },
 	{ .hw = &g12a_fclk_div7.hw },
 };
Signature · 1 line
Jerome
#3 lore raw
Quoted 14 lines · Jerome Brunet
Quoted 2 lines · Da Xue

SPICC is missing fclk_div2 which causes the spicc module to output sclk at 2.5x the expected rate. Adding the missing fclk_div2 resolves this.

I had to re-read that a few times to get the what the actual problem is. If you don't mind, I'll amend the commit message with

'''
SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes are wrong on this clock. This causes the spicc module to output sclk at 2.5x the expected rate when clock index 3 is picked.

Quoted 4 lines

Adding the missing fclk_div2 resolves this.
'''

Is that OK with you Da ?

Feel free. Your description is better.

Quoted 34 lines
Quoted 19 lines
Fixes a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks")
Cc <[email protected]> # 6.1
Signed-off-by Da Xue <[email protected]>

---
Changelog:

v2 -> v3: remove gp0
v1 -> v2: add Fixes as an older version of the patch was sent as v1

---
 drivers/clk/meson/g12a.c | 1 +
 1 file changed, 1 insertion(+)
drivers/clk/meson/g12a.c +0 -0
index 4f92b83965d5a..b72eebd0fa474 100644

drivers/clk/meson/g12a.c static const struct clk_parent_data spicc_sclk_parent_data[] = { · line 4105

Quoted 7 lines
drivers/clk/meson/g12a.c +1 -0
@@ -4099,6 +4099,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = {
      { .hw = &g12a_clk81.hw },
      { .hw = &g12a_fclk_div4.hw },
      { .hw = &g12a_fclk_div3.hw },
+     { .hw = &g12a_fclk_div2.hw },
      { .hw = &g12a_fclk_div5.hw },
      { .hw = &g12a_fclk_div7.hw },
 };

--
Jerome

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