dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
Subsystems (2)
Rob Herring (Arm)
maintainerPATCH 1/1 dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
Convert the Marvell Dove PLL divider clock binding to DT schema format. It's a straight forward conversion.
Signed-off-by Rob Herring (Arm) <[email protected]>
--- .../bindings/clock/dove-divider-clock.txt | 28 ----------- .../clock/marvell,dove-divider-clock.yaml | 50 +++++++++++++++++++ 2 files changed, 50 insertions(+), 28 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/dove-divider-clock.txt create mode 100644 Documentation/devicetree/bindings/clock/marvell,dove-divider-clock.yaml
Documentation/devicetree/bindings/clock/dove-divider-clock.txt deleted +0 -28
@@ -1,28 +0,0 @@ -PLL divider based Dove clocks - -Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide -high speed clocks for a number of peripherals. These dividers are part of -the PMU, and thus this node should be a child of the PMU node. - -The following clocks are provided: - -ID Clock -------------- -0 AXI bus clock -1 GPU clock -2 VMeta clock -3 LCD clock - -Required properties: -- compatible : shall be "marvell,dove-divider-clock" -- reg : shall be the register address of the Core PLL and Clock Divider - Control 0 register. This will cover that register, as well as the - Core PLL and Clock Divider Control 1 register. Thus, it will have - a size of 8. -- #clock-cells : from common clock binding; shall be set to 1 - -divider_clk: core-clock@64 { - compatible = "marvell,dove-divider-clock"; - reg = <0x0064 0x8>; - #clock-cells = <1>; -};
Documentation/devicetree/bindings/clock/marvell,dove-divider-clock.yaml new file +50 -0
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Signature · 1 line
2.47.2
Quoting Rob Herring (Arm) (2025-05-21 14:08:31)
Quoted 5 lines
Convert the Marvell Dove PLL divider clock binding to DT schema format. It's a straight forward conversion.
Signed-off-by Rob Herring (Arm) <[email protected]>---
Applied to clk-next