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NPCM845 reset and clock device tree updates

PATCH Superseded Tomer Maimon 2 participants 4 messages Jul 6, 2025 – Jul 21, 2025

Subsystems (2)
Device tree bindings Arm/nuvoton npcm architecture

v1 of 2 Superseded Latest is v2 →

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Tomer Maimon

author maintainer
#0 lore raw

cover NPCM845 reset and clock device tree updates

This series updates the NPCM845 device tree for the integrated reset and clock controller using the auxiliary device framework.
Patch 1 combines the reset and clock nodes into nuvoton,npcm845-reset. Patch 2 adds a 25 MHz refclk and updates peripherals to use it.

Tested on NPCM845 evaluation board.

Tomer Maimon (2):
arm64: dts: nuvoton: combine NPCM845 reset and clk nodes
arm64: dts: nuvoton: add refclk and update peripheral clocks for

    NPCM845
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 20 ++++++++-----------
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  |  6 ++++++
 2 files changed, 14 insertions(+), 12 deletions(-)
Signature · 1 line
2.34.1
author maintainer
#1 lore raw

PATCH 1/2 arm64: dts: nuvoton: combine NPCM845 reset and clk nodes

Combine the NPCM845 reset and clock controller nodes into a single node with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi, using the auxiliary device framework to provide clock functionality.

Update the register range to 0xC4 to cover the shared reset and clock registers at 0xf0801000.

Remove the separate nuvoton,npcm845-clk node, as the reset driver now handles clocks via an auxiliary device.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi      | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +3 -8
index fead4dde590d..2a36d0b2824e 100644
@@ -47,17 +47,12 @@ ahb {
 		interrupt-parent = <&gic>;
 		ranges;
 
-		rstc: reset-controller@f0801000 {
+		clk: rstc: reset-controller@f0801000 {
 			compatible = "nuvoton,npcm845-reset";
-			reg = <0x0 0xf0801000 0x0 0x78>;
-			#reset-cells = <2>;
+			reg = <0x0 0xf0801000 0x0 0xC4>;
 			nuvoton,sysgcr = <&gcr>;
-		};
-
-		clk: clock-controller@f0801000 {
-			compatible = "nuvoton,npcm845-clk";
+			#reset-cells = <2>;
 			#clock-cells = <1>;
-			reg = <0x0 0xf0801000 0x0 0x1000>;
 		};
 
 		apb {
Signature · 1 line
2.34.1
author maintainer
#2 lore raw

PATCH 2/2 arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845

In reply to Tomer Maimon

Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device tree to represent the external reference clock used by the NPCM845 reset and clock controller.

Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to reference this refclk directly instead of the previous clock controller output (NPCM8XX_CLK_REFCLK).

Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes

Signed-off-by Tomer Maimon <[email protected]>
---
 arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++----
 arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts     | 6 ++++++
 2 files changed, 11 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5 -4
index 2a36d0b2824e..04a5029bfc7e 100644
@@ -52,6 +52,7 @@ clk: rstc: reset-controller@f0801000 {
 			reg = <0x0 0xf0801000 0x0 0xC4>;
 			nuvoton,sysgcr = <&gcr>;
 			#reset-cells = <2>;
+			clocks = <&refclk>;
 			#clock-cells = <1>;
 		};
 

@@ -76,7 +77,7 @@ timer0: timer@8000 {
 				compatible = "nuvoton,npcm845-timer";
 				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0x8000 0x1C>;
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
+				clocks = <&refclk>;
 				clock-names = "refclk";
 			};
 

@@ -148,7 +149,7 @@ watchdog0: watchdog@801c {
 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0x801c 0x4>;
 				status = "disabled";
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
+				clocks = <&refclk>;
 				syscon = <&gcr>;
 			};
 

@@ -157,7 +158,7 @@ watchdog1: watchdog@901c {
 				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0x901c 0x4>;
 				status = "disabled";
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
+				clocks = <&refclk>;
 				syscon = <&gcr>;
 			};
 

@@ -166,7 +167,7 @@ watchdog2: watchdog@a01c {
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xa01c 0x4>;
 				status = "disabled";
-				clocks = <&clk NPCM8XX_CLK_REFCLK>;
+				clocks = <&refclk>;
 				syscon = <&gcr>;
 			};
 		};
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +6 -0
index eeceb5b292a8..2638ee1c3846 100644
@@ -19,6 +19,12 @@ chosen {
 	memory@0 {
 		reg = <0x0 0x0 0x0 0x40000000>;
 	};
+
+	refclk: refclk-25mhz {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		#clock-cells = <0>;
+	};
 };
 
 &serial0 {
Signature · 1 line
2.34.1
maintainer
#3 lore raw
In reply to Tomer Maimon
Quoted 8 lines · Tomer Maimon

This series updates the NPCM845 device tree for the integrated reset and clock controller using the auxiliary device framework.
Patch 1 combines the reset and clock nodes into nuvoton,npcm845-reset. Patch 2 adds a 25 MHz refclk and updates peripherals to use it.

Tested on NPCM845 evaluation board.

[...]

Thanks, I've applied this to be picked up through the BMC tree.

Signature · 1 line
Andrew Jeffery <[email protected]>