reset: bcm6345: add support for internal ephy resets on bcm63xx

bcm63xx SoCs have a register in the gpio controller that controls some of the phy functionality. Some of the bits reset individual phys and need a driver to set.

The other fields in the register configure phy power and will be set by the network device driver.

v2:
- Drop SoC specific patches since bits are sequential

v1: https://lore.kernel.org/all/[email protected]/

Kyle Hendry (2):
reset: bcm6345: add support for bcm63xx ephy control register
dt-bindings: reset: add compatible for bcm63xx ephy control

 .../devicetree/bindings/reset/brcm,bcm6345-reset.yaml         | 4 +++-
 drivers/reset/reset-bcm6345.c                                 | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

2.43.0

The ephy control register on bcm63xx SoCs contain bits for resetting individual internal phys. Use the existing bcm6345-reset driver to set bits.

---
 drivers/reset/reset-bcm6345.c | 1 +
 1 file changed, 1 insertion(+)

index aa9353439e70..56518f7bfbb3 100644
@@ -119,6 +119,7 @@ static int bcm6345_reset_probe(struct platform_device *pdev)
 
 static const struct of_device_id bcm6345_reset_of_match[] = {
 	{ .compatible = "brcm,bcm6345-reset" },
+	{ .compatible = "brcm,bcm63xx-ephy-ctrl" },
 	{ /* sentinel */ },
 };
 

2.43.0

Add compatible string for bcm63xx ephy control.

---
 .../devicetree/bindings/reset/brcm,bcm6345-reset.yaml         | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

index 00150b93fca0..b8a320bb1776 100644
@@ -13,7 +13,9 @@ maintainers:
 
 properties:
   compatible:
-    const: brcm,bcm6345-reset
+    enum:
+      - brcm,bcm6345-reset
+      - brcm,bcm63xx-ephy-ctrl
 
   reg:
     maxItems: 1

2.43.0