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arm: crypto: add a check for crypto extensions support.

PATCH Applied [email protected] 3 participants 3 messages Aug 27, 2025 – Aug 28, 2025

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Arm (32-bit) Crypto API
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PATCH 1/1 arm: crypto: add a check for crypto extensions support.

From: Chali Anis <[email protected]>

In some configuration the CPU may raise an exception bacause of an unknown instruction if it does not support Crypto Extensions for example in some BCM281X (RPi3B in my case) when running barebox as an EFI Payload, where the EFI stops with a synchronous execption See bellow:
Synchronous Exception at 0x0000000037BFF548
SP 0x0000000037F798C0 ELR 0x0000000037BFF548
SPSR 0x20000209 FPSR 0x00000000
ESR 0x02000000 FAR 0x14F64325185430BF
ESR : EC 0x00 IL 0x1 ISS 0x00000000

Signed-off-by Chali Anis <[email protected]>
---
 arch/arm/crypto/sha1-ce-glue.c | 7 +++++++
 arch/arm/crypto/sha2-ce-glue.c | 9 +++++++--
 arch/arm/include/asm/sysreg.h  | 6 ++++++
 3 files changed, 20 insertions(+), 2 deletions(-)
arch/arm/crypto/sha1-ce-glue.c +7 -0
index 5b49237573fa..fea15f295a00 100644
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/byteorder.h>
 #include <asm/neon.h>
+#include <asm/sysreg.h>
 
 MODULE_DESCRIPTION("SHA1 secure hash using ARMv8 Crypto Extensions");
 MODULE_AUTHOR("Ard Biesheuvel <[email protected]>");

@@ -88,6 +89,12 @@ static struct digest_algo m = {
 
 static int sha1_ce_mod_init(void)
 {
+	uint64_t isar0;
+
+	isar0 = read_sysreg(ID_AA64ISAR0_EL1);
+	if (!(isar0 & ID_AA64ISAR0_EL1_SHA1_MASK))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&m);
 }
 coredevice_initcall(sha1_ce_mod_init);
arch/arm/crypto/sha2-ce-glue.c +7 -2
index 88cbc7993dac..8479b3c60cb3 100644
@@ -14,8 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/byteorder.h>
 #include <asm/neon.h>
-
-#include <asm/neon.h>
+#include <asm/sysreg.h>
 
 MODULE_DESCRIPTION("SHA-224/SHA-256 secure hash using ARMv8 Crypto Extensions");
 MODULE_AUTHOR("Ard Biesheuvel <[email protected]>");

@@ -116,6 +115,12 @@ static struct digest_algo sha256 = {
 
 static int sha256_ce_digest_register(void)
 {
+	uint64_t isar0;
+
+	isar0 = read_sysreg(ID_AA64ISAR0_EL1);
+	if (!(isar0 & ID_AA64ISAR0_EL1_SHA2_MASK))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&sha256);
 }
 coredevice_initcall(sha256_ce_digest_register);
arch/arm/include/asm/sysreg.h +6 -0
index 7d567e08d8b7..6f47016e54e8 100644
@@ -12,6 +12,12 @@
 #include <asm/system.h>
 #include <linux/stringify.h>
 
+/*
+ *	ARM64 registers
+ */
+#define ID_AA64ISAR0_EL1_SHA1_MASK      0xF00UL
+#define ID_AA64ISAR0_EL1_SHA2_MASK      0xF000UL
+
 /*
  * Unlike read_cpuid, calls to read_sysreg are never expected to be
  * optimized away or replaced with synthetic values.
Signature · 1 line
2.34.1
Applied
#1 lore raw
Quoted 11 lines · On Wed, 27 Aug 2025 11:53:07 -0400, [email protected] wrote:

In some configuration the CPU may raise an exception bacause of an unknown instruction if it does not support Crypto Extensions for example in some BCM281X (RPi3B in my case) when running barebox as an EFI Payload, where the EFI stops with a synchronous execption See bellow:
Synchronous Exception at 0x0000000037BFF548
SP 0x0000000037F798C0 ELR 0x0000000037BFF548
SPSR 0x20000209 FPSR 0x00000000
ESR 0x02000000 FAR 0x14F64325185430BF
ESR : EC 0x00 IL 0x1 ISS 0x00000000

Quoted 1 line

[...]

Applied, thanks!

[1/1] arm: crypto: add a check for crypto extensions support.
https://git.pengutronix.de/cgit/barebox/commit/?id=20d75a6f932f (link may not be stable)

Best regards,

Signature · 1 line
Sascha Hauer <[email protected]>
#2 lore raw
In reply to [email protected]

Hi,

Quoted 12 lines · On 27.08.25 17:53, [email protected] wrote:

From: Chali Anis <[email protected]>

In some configuration the CPU may raise an exception bacause of an unknown instruction if it does not support Crypto Extensions for example in some BCM281X (RPi3B in my case) when running barebox as an EFI Payload, where the EFI stops with a synchronous execption See bellow:
Synchronous Exception at 0x0000000037BFF548
SP 0x0000000037F798C0 ELR 0x0000000037BFF548
SPSR 0x20000209 FPSR 0x00000000
ESR 0x02000000 FAR 0x14F64325185430BF
ESR : EC 0x00 IL 0x1 ISS 0x00000000

Thanks for your patch. It's good to have the check, but are you sure you don't have the ARMv8.0 Crypto Extensions?

arm_cpu_lowlevel_init() enables SIMD, so maybe not calling that is the reason you got the crash?

For EFI payloads in particular, I don't think we should call
the whole arm_cpu_lowlevel_init(), but maybe there is an argument to be made that FP/SIMD at least should be enabled. I am not sure if that alone could lead to issues affecting the EFI loader though.

Cheers,
Ahmad

Quoted 77 lines
Signed-off-by Chali Anis <[email protected]>
---
 arch/arm/crypto/sha1-ce-glue.c | 7 +++++++
 arch/arm/crypto/sha2-ce-glue.c | 9 +++++++--
 arch/arm/include/asm/sysreg.h  | 6 ++++++
 3 files changed, 20 insertions(+), 2 deletions(-)
arch/arm/crypto/sha1-ce-glue.c +7 -0
index 5b49237573fa..fea15f295a00 100644
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/byteorder.h>
 #include <asm/neon.h>
+#include <asm/sysreg.h>
 
 MODULE_DESCRIPTION("SHA1 secure hash using ARMv8 Crypto Extensions");
 MODULE_AUTHOR("Ard Biesheuvel <[email protected]>");

@@ -88,6 +89,12 @@ static struct digest_algo m = {
 
 static int sha1_ce_mod_init(void)
 {
+	uint64_t isar0;
+
+	isar0 = read_sysreg(ID_AA64ISAR0_EL1);
+	if (!(isar0 & ID_AA64ISAR0_EL1_SHA1_MASK))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&m);
 }
 coredevice_initcall(sha1_ce_mod_init);
arch/arm/crypto/sha2-ce-glue.c +7 -2
index 88cbc7993dac..8479b3c60cb3 100644
@@ -14,8 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/byteorder.h>
 #include <asm/neon.h>
-
-#include <asm/neon.h>
+#include <asm/sysreg.h>
 
 MODULE_DESCRIPTION("SHA-224/SHA-256 secure hash using ARMv8 Crypto Extensions");
 MODULE_AUTHOR("Ard Biesheuvel <[email protected]>");

@@ -116,6 +115,12 @@ static struct digest_algo sha256 = {
 
 static int sha256_ce_digest_register(void)
 {
+	uint64_t isar0;
+
+	isar0 = read_sysreg(ID_AA64ISAR0_EL1);
+	if (!(isar0 & ID_AA64ISAR0_EL1_SHA2_MASK))
+		return -EOPNOTSUPP;
+
 	return digest_algo_register(&sha256);
 }
 coredevice_initcall(sha256_ce_digest_register);
arch/arm/include/asm/sysreg.h +6 -0
index 7d567e08d8b7..6f47016e54e8 100644
@@ -12,6 +12,12 @@
 #include <asm/system.h>
 #include <linux/stringify.h>
 
+/*
+ *	ARM64 registers
+ */
+#define ID_AA64ISAR0_EL1_SHA1_MASK      0xF00UL
+#define ID_AA64ISAR0_EL1_SHA2_MASK      0xF000UL
+
 /*
  * Unlike read_cpuid, calls to read_sysreg are never expected to be
  * optimized away or replaced with synthetic values.
Signature · 4 lines
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