DC Patches for September 8, 2025

PATCH In review waynelin 2 participants 13 messages Sep 2, 2025 – Sep 8, 2025

Subsystems (4)

Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core

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waynelin

author

2025-09-02 00:46 UTC #0 lore raw

cover DC Patches for September 8, 2025

This DC patchset brings improvements in multiple areas. In summary, we highlight:

- Disable stutter when programming watermarks on dcn32
- Fix pbn_div Calculation Error
- Correct sequences and delays for DCN35 PG & RCG
- Define interfaces for hubbub perfmance monitoring support
- Extend to read eDP general capability 2
- Indicate when custom brightness curves are in use
- Dont wait for pipe update during medupdate/highirq
- Add HDCP retry_limit control parameter

Cc Dan Wheeler <[email protected]>

---

Allen Li (1):
drm/amd/display: Read DPCD to obtain eDP capability information.

Ausef Yousof (1):
drm/amd/display: dont wait for pipe update during medupdate/highirq

Cruise Hung (1):
drm/amd/display: Add link index in AUX and dpms

Dillon Varone (1):
drm/amd/display: Disable stutter when programming watermarks on dcn32

Fangzhi Zuo (1):
drm/amd/display: Fix pbn_div Calculation Error

Mario Limonciello (1):
drm/amd/display: Indicate when custom brightness curves are in use

Oleh Kuzhylnyi (1):
drm/amd/display: Add HDCP policy control

Ovidiu Bunea (1):
drm/amd/display: Correct sequences and delays for DCN35 PG & RCG

Roman Li (1):
drm/amd/display: Refine error message for vblank init failure

Taimur Hassan (1):
drm/amd/display: Promote DC to 3.2.349

Wenjing Liu (1):
drm/amd/display: Update dchubbub.h for hubbub perfmon support

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   9 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |   2 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  13 +-
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   |   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |   2 +-
 drivers/gpu/drm/amd/display/dc/dc.h           |   4 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   1 +
 .../amd/display/dc/dccg/dcn35/dcn35_dccg.c    |  74 +++++------
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  17 ++-
 .../display/dc/hubbub/dcn32/dcn32_hubbub.c    |  37 +++++-
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 115 +++---------------
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |   3 -
 .../amd/display/dc/hwss/dcn351/dcn351_init.c  |   3 -
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |  22 ++++
 .../gpu/drm/amd/display/dc/inc/hw/pg_cntl.h   |   1 +
 .../drm/amd/display/dc/link/link_detection.c  |   2 +-
 .../gpu/drm/amd/display/dc/link/link_dpms.c   |   9 +-
 .../dc/link/protocols/link_dp_capability.c    |   6 +
 .../amd/display/dc/pg/dcn35/dcn35_pg_cntl.c   |  78 +++++++-----
 .../dc/resource/dcn32/dcn32_resource.c        |   1 +
 .../dc/resource/dcn32/dcn32_resource.h        |   3 +-
 .../gpu/drm/amd/display/modules/hdcp/hdcp.c   |   5 +-
 .../drm/amd/display/modules/inc/mod_hdcp.h    |   1 +
 23 files changed, 220 insertions(+), 190 deletions(-)

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #1 lore raw

PATCH 1/11 drm/amd/display: Add HDCP policy control

From: Oleh Kuzhylnyi <[email protected]>

[Why]
DM should be able to control HDCP retry limit via configurable parameter.

[How]
Expose a retry_limit parameter for controlling the maximum number of retries and lift the hardcode out to DM.

Reviewed-by Nicholas Kazlauskas <[email protected]>

Reviewed-by Aric Cyr <[email protected]>

Signed-off-by Oleh Kuzhylnyi <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++
 drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c        | 5 +++--
 drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h     | 1 +
 3 files changed, 6 insertions(+), 2 deletions(-)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +2 -0

index d1c853732c2e..5aae5c25e785 100644
@@ -223,6 +223,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
 		display_adjust.disable = MOD_HDCP_DISPLAY_NOT_DISABLE;
 
 		link_adjust.auth_delay = 2;
+		link_adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
 
 		if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0) {
 			link_adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;

@@ -572,6 +573,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->dp.usb4_enabled = config->usb4_enabled;
 	display->adjust.disable = MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
 	link->adjust.auth_delay = 2;
+	link->adjust.retry_limit = MAX_NUM_OF_ATTEMPTS;
 	link->adjust.hdcp1.disable = 0;
 	hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;

drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c +3 -2

index 5e01c6e24cbc..c760216a6240 100644
@@ -29,6 +29,7 @@ static void push_error_status(struct mod_hdcp *hdcp,
 		enum mod_hdcp_status status)
 {
 	struct mod_hdcp_trace *trace = &hdcp->connection.trace;
+	const uint8_t retry_limit = hdcp->connection.link.adjust.retry_limit;
 
 	if (trace->error_count < MAX_NUM_OF_ERROR_TRACE) {
 		trace->errors[trace->error_count].status = status;

@@ -39,11 +40,11 @@ static void push_error_status(struct mod_hdcp *hdcp,
 
 	if (is_hdcp1(hdcp)) {
 		hdcp->connection.hdcp1_retry_count++;
-		if (hdcp->connection.hdcp1_retry_count == MAX_NUM_OF_ATTEMPTS)
+		if (hdcp->connection.hdcp1_retry_count == retry_limit)
 			hdcp->connection.link.adjust.hdcp1.disable = 1;
 	} else if (is_hdcp2(hdcp)) {
 		hdcp->connection.hdcp2_retry_count++;
-		if (hdcp->connection.hdcp2_retry_count == MAX_NUM_OF_ATTEMPTS)
+		if (hdcp->connection.hdcp2_retry_count == retry_limit)
 			hdcp->connection.link.adjust.hdcp2.disable = 1;
 	}
 }

drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +1 -0

index c42468bb70ac..b51ddf2846df 100644
@@ -220,6 +220,7 @@ struct mod_hdcp_link_adjustment_hdcp2 {
 
 struct mod_hdcp_link_adjustment {
 	uint8_t auth_delay;
+	uint8_t retry_limit;
 	struct mod_hdcp_link_adjustment_hdcp1 hdcp1;
 	struct mod_hdcp_link_adjustment_hdcp2 hdcp2;
 };

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #2 lore raw

PATCH 2/11 drm/amd/display: Add link index in AUX and dpms

In reply to waynelin

From: Cruise Hung <[email protected]>

[Why & How]
Add the link index in DP AUX transfer and DPMS functions.

Reviewed-by Wenjing Liu <[email protected]>

Signed-off-by Cruise Hung <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c    | 17 +++++++++++++----
 .../drm/amd/display/dc/link/link_detection.c    |  2 +-
 drivers/gpu/drm/amd/display/dc/link/link_dpms.c |  9 +++++----
 3 files changed, 19 insertions(+), 9 deletions(-)

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +13 -4

index bb4ac5042c80..673bb87d2c17 100644
@@ -725,14 +725,18 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 	for (i = 0; i < AUX_MAX_RETRIES; i++) {
 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
 					LOG_FLAG_I2cAux_DceAux,
-					"dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: address=0x%04x length=%u write=%d mot=%d",
+					"dce_aux_transfer_with_retries: link_index=%u: START: retry %d of %d: "
+					"address=0x%04x length=%u write=%d mot=%d is_i2c=%d is_dpia=%d ddc_hw_inst=%d",
 					ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
 					i + 1,
 					(int)AUX_MAX_RETRIES,
 					payload->address,
 					payload->length,
 					(unsigned int) payload->write,
-					(unsigned int) payload->mot);
+					(unsigned int) payload->mot,
+					payload->i2c_over_aux,
+					(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,
+					ddc->link->ddc_hw_inst);
 		if (payload->write)
 			dce_aux_log_payload("  write", payload->data, payload->length, 16);

@@ -746,7 +750,9 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 
 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
 					LOG_FLAG_I2cAux_DceAux,
-					"dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d payload->reply=%u",
+					"dce_aux_transfer_with_retries: link_index=%u: END: retry %d of %d: "
+					"address=0x%04x length=%u write=%d mot=%d: ret=%d operation_result=%d "
+					"payload->reply=%u  is_i2c=%d is_dpia=%d ddc_hw_inst=%d",
 					ddc && ddc->link ? ddc->link->link_index : UINT_MAX,
 					i + 1,
 					(int)AUX_MAX_RETRIES,

@@ -756,7 +762,10 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
 					(unsigned int) payload->mot,
 					ret,
 					(int)operation_result,
-					(unsigned int) *payload->reply);
+					(unsigned int) *payload->reply,
+					payload->i2c_over_aux,
+					(ddc->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? true : false,
+					ddc->link->ddc_hw_inst);
 		if (!payload->write)
 			dce_aux_log_payload("  read", payload->data, ret > 0 ? ret : 0, 16);

drivers/gpu/drm/amd/display/dc/link/link_detection.c +1 -1

index 827b630daf49..b717e430051a 100644
@@ -656,7 +656,7 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 		return true;
 
 	is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
-	DC_LOG_DC("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
+	DC_LOG_DC("DP Alt mode state on HPD: %d  Link=%d\n", is_in_alt_mode, link->link_index);
 
 	if (is_in_alt_mode)
 		return true;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c +5 -4

index cb80b4599936..08ee8d2f777b 100644
@@ -2358,9 +2358,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx)
 	if (pipe_ctx->stream->sink) {
 		if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
 			pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
-			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
+			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__,
 			pipe_ctx->stream->sink->edid_caps.display_name,
-			pipe_ctx->stream->signal);
+			pipe_ctx->stream->signal, link->link_index);
 		}
 	}

@@ -2473,9 +2473,10 @@ void link_set_dpms_on(
 	if (pipe_ctx->stream->sink) {
 		if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
 			pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
-			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
+			DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__,
 			pipe_ctx->stream->sink->edid_caps.display_name,
-			pipe_ctx->stream->signal);
+			pipe_ctx->stream->signal,
+			link->link_index);
 		}
 	}

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #3 lore raw

PATCH 3/11 drm/amd/display: dont wait for pipe update during medupdate/highirq

In reply to waynelin

From: Ausef Yousof <[email protected]>

[why&how]
control flag for the wait during pipe update wait for vupdate should be set if update type is not fast or med to prevent an invalid sleep operation

Reviewed-by Alvin Lee <[email protected]>

Signed-off-by Ausef Yousof <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/drm/amd/display/dc/core/dc.c +1 -1

index 261b7d43e91d..5963019d1e74 100644
@@ -4169,7 +4169,7 @@ static void commit_planes_for_stream(struct dc *dc,
 	}
 
 	if (dc->hwseq->funcs.wait_for_pipe_update_if_needed)
-		dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type == UPDATE_TYPE_FAST);
+		dc->hwseq->funcs.wait_for_pipe_update_if_needed(dc, top_pipe_to_program, update_type < UPDATE_TYPE_FULL);
 
 	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
 		if (dc->hwss.subvp_pipe_control_lock)

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #4 lore raw

PATCH 4/11 drm/amd/display: Indicate when custom brightness curves are in use

In reply to waynelin

From: Mario Limonciello <[email protected]>

[Why]
There is a scale sysfs attribute that can be used to indicate when non-linear brightness scaling is in use. As Custom brightness curves work by linear interpolation of points the scale is no longer linear.

[How]
Indicate non-linear scaling when custom brightness curves in use and linear scaling otherwise.

Reviewed-by Alex Hung <[email protected]>

Signed-off-by Mario Limonciello <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +4 -1

index 242f98564261..7470e1a21279 100644
@@ -5049,8 +5049,11 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
 	} else
 		props.brightness = props.max_brightness = MAX_BACKLIGHT_LEVEL;
 
-	if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE))
+	if (caps->data_points && !(amdgpu_dc_debug_mask & DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE)) {
 		drm_info(drm, "Using custom brightness curve\n");
+		props.scale = BACKLIGHT_SCALE_NON_LINEAR;
+	} else
+		props.scale = BACKLIGHT_SCALE_LINEAR;
 	props.type = BACKLIGHT_RAW;
 
 	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #5 lore raw

PATCH 5/11 drm/amd/display: Read DPCD to obtain eDP capability information.

In reply to waynelin

From: Allen Li <[email protected]>

[Why & How]
Extend to read eDP general capability 2 in detect_edp_sink_caps().

Reviewed-by Robin Chen <[email protected]>

Reviewed-by Wenjing Liu <[email protected]>

Signed-off-by Allen Li <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h                | 1 +
 .../drm/amd/display/dc/link/protocols/link_dp_capability.c  | 6 ++++++
 2 files changed, 7 insertions(+)

drivers/gpu/drm/amd/display/dc/dc_dp_types.h +1 -0

index 3a3ec38cdf8b..db669ccb1d58 100644
@@ -1284,6 +1284,7 @@ struct dpcd_caps {
 	union dp_receive_port0_cap receive_port0_cap;
 	/* Indicates the number of SST links supported by MSO (Multi-Stream Output) */
 	uint8_t mso_cap_sst_links_supported;
+	uint8_t dp_edp_general_cap_2;
 };
 
 union dpcd_sink_ext_caps {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +6 -0

index caddb7dfb133..b12c11bd6a14 100644
@@ -2195,6 +2195,12 @@ void detect_edp_sink_caps(struct dc_link *link)
 			DP_EDP_MSO_LINK_CAPABILITIES,
 			(uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported,
 			sizeof(link->dpcd_caps.mso_cap_sst_links_supported));
+	/*
+	 * Read eDP general capability 2
+	 */
+	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2,
+			(uint8_t *)&link->dpcd_caps.dp_edp_general_cap_2,
+			sizeof(link->dpcd_caps.dp_edp_general_cap_2));
 }
 
 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #6 lore raw

PATCH 6/11 drm/amd/display: Update dchubbub.h for hubbub perfmon support

In reply to waynelin

From: Wenjing Liu <[email protected]>

[why]
dchubbub supports performance monitoring for hubbub. The interfaces define the performance monitoring events and their attributes.

Reviewed-by Alvin Lee <[email protected]>

Signed-off-by Wenjing Liu <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +22 -0

index 9bee45b36629..843a18287c83 100644
@@ -137,6 +137,19 @@ struct dcn_hubbub_state {
 	uint32_t dram_state_cntl;
 };
 
+struct hubbub_system_latencies {
+	uint32_t max_latency_ns;
+	uint32_t avg_latency_ns;
+	uint32_t min_latency_ns;
+};
+
+struct hubbub_urgent_latency_params {
+	uint32_t refclk_mhz;
+	uint32_t t_win_ns;
+	uint32_t bandwidth_mbps;
+	uint32_t bw_factor_x1000;
+};
+
 struct hubbub_funcs {
 	void (*update_dchub)(
 			struct hubbub *hubbub,

@@ -231,6 +244,15 @@ struct hubbub_funcs {
 	bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower);
 	void (*get_det_sizes)(struct hubbub *hubbub, uint32_t *curr_det_sizes, uint32_t *target_det_sizes);
 	uint32_t (*compbuf_config_error)(struct hubbub *hubbub);
+	struct hubbub_perfmon_funcs{
+		void (*start_system_latency_measurement)(struct hubbub *hubbub);
+		void (*get_system_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, struct hubbub_system_latencies *latencies);
+		void (*start_in_order_bandwidth_measurement)(struct hubbub *hubbub);
+		void (*get_in_order_bandwidth_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *bandwidth_mbps);
+		void (*start_urgent_ramp_latency_measurement)(struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params);
+		void (*get_urgent_ramp_latency_result)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *latency_ns);
+		void (*reset)(struct hubbub *hubbub);
+	} perfmon;
 };
 
 struct hubbub {

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:46 UTC #7 lore raw

PATCH 7/11 drm/amd/display: Refine error message for vblank init failure

In reply to waynelin

From: Roman Li <[email protected]>

[Why]
The error message "failed to initialize sw for display support" is used for both DRM device and vblank initialization failures, making it difficult to identify the specific failure during troubleshooting.

[How]
Update the vblank initialization error message to "failed to initialize vblank for display support" to distinguish it from the DRM device init failure.

Reviewed-by Aurabindo Pillai <[email protected]>

Signed-off-by Roman Li <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 -1

index 7470e1a21279..9273bc3849f1 100644
@@ -2186,7 +2186,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 
 	if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
 		drm_err(adev_to_drm(adev),
-		"failed to initialize sw for display support.\n");
+		"failed to initialize vblank for display support.\n");
 		goto error;
 	}

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:47 UTC #8 lore raw

PATCH 8/11 drm/amd/display: Correct sequences and delays for DCN35 PG & RCG

In reply to waynelin

From: Ovidiu Bunea <[email protected]>

[why]
The current PG & RCG programming in driver has some gaps and incorrect sequences.

[how]
Added delays after ungating clocks to allow ramp up, increased polling to allow more time for power up, and removed the incorrect sequences.

Cc Mario Limonciello <[email protected]>

Cc Alex Deucher <[email protected]>

Cc [email protected]

Reviewed-by Charlene Liu <[email protected]>

Signed-off-by Ovidiu Bunea <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dc.h           |   1 +
 .../amd/display/dc/dccg/dcn35/dcn35_dccg.c    |  74 +++++------
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 115 +++---------------
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |   3 -
 .../amd/display/dc/hwss/dcn351/dcn351_init.c  |   3 -
 .../gpu/drm/amd/display/dc/inc/hw/pg_cntl.h   |   1 +
 .../amd/display/dc/pg/dcn35/dcn35_pg_cntl.c   |  78 +++++++-----
 7 files changed, 111 insertions(+), 164 deletions(-)

drivers/gpu/drm/amd/display/dc/dc.h +1 -0

index b41e66c31e6a..09d705cf5c9b 100644
@@ -1162,6 +1162,7 @@ struct dc_debug_options {
 	unsigned int auxless_alpm_lfps_silence_ns;
 	unsigned int auxless_alpm_lfps_t1t2_us;
 	short auxless_alpm_lfps_t1t2_offset_us;
+	bool enable_pg_cntl_debug_logs;
 };

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +39 ~~-35~~

190 lines not on this page · raw message

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +20 ~~-95~~

169 lines not on this page · raw message

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +0 -3

index 52cc488416ac..f2f16a0bdb4f 100644
@@ -115,7 +115,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = {
 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
 	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
-	.update_dsc_pg = dcn32_update_dsc_pg,
 	.calc_blocks_to_gate = dcn35_calc_blocks_to_gate,
 	.calc_blocks_to_ungate = dcn35_calc_blocks_to_ungate,
 	.hw_block_power_up = dcn35_hw_block_power_up,

@@ -151,7 +150,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
 	.plane_atomic_disable = dcn35_plane_atomic_disable,
 	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/
 	//.hubp_pg_control = dcn35_hubp_pg_control,
-	.enable_power_gating_plane = dcn35_enable_power_gating_plane,
 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
 	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,

@@ -166,7 +164,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
 	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
 	.resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio,
 	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,
-	.dsc_pg_control = dcn35_dsc_pg_control,
 	.dsc_pg_status = dcn32_dsc_pg_status,
 	.enable_plane = dcn35_enable_plane,
 	.wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,

drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +0 -3

index e34efcb7bde5..09e60158f0b5 100644
@@ -114,7 +114,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = {
 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
 	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
 	.apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations,
-	.update_dsc_pg = dcn32_update_dsc_pg,
 	.calc_blocks_to_gate = dcn351_calc_blocks_to_gate,
 	.calc_blocks_to_ungate = dcn351_calc_blocks_to_ungate,
 	.hw_block_power_up = dcn351_hw_block_power_up,

@@ -146,7 +145,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
 	.plane_atomic_disable = dcn35_plane_atomic_disable,
 	//.plane_atomic_disable = dcn20_plane_atomic_disable,/*todo*/
 	//.hubp_pg_control = dcn35_hubp_pg_control,
-	.enable_power_gating_plane = dcn35_enable_power_gating_plane,
 	.dpp_root_clock_control = dcn35_dpp_root_clock_control,
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
 	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,

@@ -160,7 +158,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
 	.setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
 	.calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,
 	.is_dp_dig_pixel_rate_div_policy = dcn35_is_dp_dig_pixel_rate_div_policy,
-	.dsc_pg_control = dcn35_dsc_pg_control,
 	.dsc_pg_status = dcn32_dsc_pg_status,
 	.enable_plane = dcn35_enable_plane,
 	.wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed,

drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h +1 -0

index 44f86cc2d1d6..227e3f8d7e5f 100644
@@ -49,6 +49,7 @@ struct pg_cntl_funcs {
 	void (*mem_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
 	void (*dio_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
 	void (*init_pg_status)(struct pg_cntl *pg_cntl);
+	void (*print_pg_status)(struct pg_cntl *pg_cntl, const char *debug_func, const char *debug_log);
 };
 
 #endif //__DC_PG_CNTL_H__

drivers/gpu/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c +50 ~~-28~~

152 lines not on this page · raw message

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:47 UTC #9 lore raw

PATCH 9/11 drm/amd/display: Fix pbn_div Calculation Error

In reply to waynelin

From: Fangzhi Zuo <[email protected]>

[Why]
dm_mst_get_pbn_divider() returns value integer coming from
the cast from fixed point, but the casted integer will then be used in dfixed_const to be multiplied by 4096. The cast from fixed point to integer causes the calculation error becomes bigger when multiplied by 4096.

That makes the calculated pbn_div value becomes smaller than it should be, which leads to the req_slot number becomes bigger.

Such error is getting reflected in 8k30 timing,
where the correct and incorrect calculated req_slot 62.9 Vs 63.1. That makes the wrong calculation failed to light up 8k30 after a dock under HBR3 x 4.

[How]
Restore the accuracy by keeping the fraction part
calculated for the left shift operation.

Reviewed-by Aurabindo Pillai <[email protected]>

Signed-off-by Fangzhi Zuo <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   |  2 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 ++++++++++---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h |  2 +-
 3 files changed, 12 insertions(+), 5 deletions(-)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 -1

index 9273bc3849f1..6a9d4545e8e7 100644
@@ -8004,7 +8004,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
 	if (IS_ERR(mst_state))
 		return PTR_ERR(mst_state);
 
-	mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
+	mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
 
 	if (!state->duplicated) {
 		int max_bpc = conn_state->max_requested_bpc;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +10 -3

index 6a817508c826..2cf8f80f3764 100644
@@ -853,13 +853,20 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 	drm_connector_attach_dp_subconnector_property(&aconnector->base);
 }
 
-int dm_mst_get_pbn_divider(struct dc_link *link)
+uint32_t dm_mst_get_pbn_divider(struct dc_link *link)
 {
+	uint32_t pbn_div_x100;
+	uint64_t dividend, divisor;
+
 	if (!link)
 		return 0;
 
-	return dc_link_bandwidth_kbps(link,
-			dc_link_get_link_cap(link)) / (8 * 1000 * 54);
+	dividend = (uint64_t)dc_link_bandwidth_kbps(link, dc_link_get_link_cap(link)) * 100;
+	divisor = 8 * 1000 * 54;
+
+	pbn_div_x100 = div64_u64(dividend, divisor);
+
+	return dfixed_const(pbn_div_x100) / 100;
 }
 
 struct dsc_mst_fairness_params {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +1 -1

index 65f76a7d00db..6f7ea684b555 100644
@@ -60,7 +60,7 @@ enum mst_msg_ready_type {
 struct amdgpu_display_manager;
 struct amdgpu_dm_connector;
 
-int dm_mst_get_pbn_divider(struct dc_link *link);
+uint32_t dm_mst_get_pbn_divider(struct dc_link *link);
 
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 				       struct amdgpu_dm_connector *aconnector,

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:47 UTC #10 lore raw

PATCH 10/11 drm/amd/display: Disable stutter when programming watermarks on dcn32

In reply to waynelin

From: Dillon Varone <[email protected]>

[WHY&HOW]
Reprogramming watermarks with stutter allowed can cause instability on some ASICs. Disable it prior to raising watermarks (prepare bandwidth), then re-enable after lowering (optimize bandwidth).

Reviewed-by Alvin Lee <[email protected]>

Signed-off-by Dillon Varone <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 .../display/dc/hubbub/dcn32/dcn32_hubbub.c    | 37 ++++++++++++++++---
 .../dc/resource/dcn32/dcn32_resource.c        |  1 +
 .../dc/resource/dcn32/dcn32_resource.h        |  3 +-
 4 files changed, 36 insertions(+), 6 deletions(-)

drivers/gpu/drm/amd/display/dc/dc.h +1 -0

index 09d705cf5c9b..d32304443abc 100644
@@ -1163,6 +1163,7 @@ struct dc_debug_options {
 	unsigned int auxless_alpm_lfps_t1t2_us;
 	short auxless_alpm_lfps_t1t2_offset_us;
 	bool enable_pg_cntl_debug_logs;
+	bool disable_stutter_for_wm_program;
 };

drivers/gpu/drm/amd/display/dc/hubbub/dcn32/dcn32_hubbub.c +32 -5

index 92957398ac0a..3b71bfaca291 100644
@@ -28,6 +28,7 @@
 #include "dcn32_hubbub.h"
 #include "dm_services.h"
 #include "reg_helper.h"
+#include "dal_asic_id.h"
 
 
 #define CTX \

@@ -72,6 +73,14 @@ static void dcn32_init_crb(struct hubbub *hubbub)
 	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x47F);
 }
 
+static void hubbub32_set_sdp_control(struct hubbub *hubbub, bool dc_control)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,
+			SDPIF_PORT_CONTROL, dc_control);
+}
+
 void hubbub32_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel)
 {
 	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);

@@ -754,8 +763,17 @@ static bool hubbub32_program_watermarks(
 		unsigned int refclk_mhz,
 		bool safe_to_lower)
 {
+	struct dc *dc = hubbub->ctx->dc;
 	bool wm_pending = false;
 
+	if (!safe_to_lower && dc->debug.disable_stutter_for_wm_program &&
+			(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||
+			ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {
+		/* before raising watermarks, SDP control give to DF, stutter must be disabled */
+		hubbub32_set_sdp_control(hubbub, false);
+		hubbub1_allow_self_refresh_control(hubbub, false);
+	}
+
 	if (hubbub32_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
 		wm_pending = true;

@@ -786,10 +804,20 @@ static bool hubbub32_program_watermarks(
 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
 
-	if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter)
-		hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+	if (safe_to_lower) {
+		/* after lowering watermarks, stutter setting is restored, SDP control given to DC */
+		hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);
+
+		if (dc->debug.disable_stutter_for_wm_program &&
+				(ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev) ||
+				ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev))) {
+			hubbub32_set_sdp_control(hubbub, true);
+		}
+	} else if (dc->debug.disable_stutter) {
+		hubbub1_allow_self_refresh_control(hubbub, !dc->debug.disable_stutter);
+	}
 
-	hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow);
+	hubbub32_force_usr_retraining_allow(hubbub, dc->debug.force_usr_allow);
 
 	return wm_pending;
 }

@@ -974,8 +1002,7 @@ void hubbub32_init(struct hubbub *hubbub)
 	ignore the "df_pre_cstate_req" from the SDP port control.
 	only the DCN will determine when to connect the SDP port
 	*/
-	REG_UPDATE(DCHUBBUB_SDPIF_CFG0,
-			SDPIF_PORT_CONTROL, 1);
+	hubbub32_set_sdp_control(hubbub, true);
 	/*Set SDP's max outstanding request to 512
 	must set the register back to 0 (max outstanding = 256) in zero frame buffer mode*/
 	REG_UPDATE(DCHUBBUB_SDPIF_CFG1,

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +1 -0

index 9917b366f00c..e81b9a0499d2 100644
@@ -739,6 +739,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.fpo_vactive_min_active_margin_us = 200,
 	.fpo_vactive_max_blank_us = 1000,
 	.enable_legacy_fast_update = false,
+	.disable_stutter_for_wm_program = true
 };
 
 static struct dce_aux *dcn32_aux_engine_create(

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +2 -1

index 20d714596021..99f0432288b4 100644
@@ -1230,7 +1230,8 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
       SR(DCHUBBUB_ARB_MALL_CNTL),                                              \
       SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \
       SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS),                          \
-      SR(SDPIF_REQUEST_RATE_LIMIT)
+      SR(SDPIF_REQUEST_RATE_LIMIT),                                            \
+      SR(DCHUBBUB_SDPIF_CFG0)
 
 /* DCCG */

Signature · 1 line

2.43.0

waynelin

author

2025-09-02 00:47 UTC #11 lore raw

PATCH 11/11 drm/amd/display: Promote DC to 3.2.349

In reply to waynelin

From: Taimur Hassan <[email protected]>

This version brings along following updates:

Acked-by Tom Chung <[email protected]>

Signed-off-by Taimur Hassan <[email protected]>

Signed-off-by Wayne Lin <[email protected]>

---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/gpu/drm/amd/display/dc/dc.h +1 -1

index d32304443abc..fec056d43535 100644
@@ -55,7 +55,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.348"
+#define DC_VER "3.2.349"
 
 /**
  * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC

Signature · 1 line

2.43.0

Wheeler, Daniel

Tested-by on the v1 series

2025-09-08 13:59 UTC #12 lore raw

In reply to waynelin

[Public]

Hi all,

This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.

APU
* Single Display eDP -> 1080p 60hz, 1920x1200 165hz, 3840x2400 60hz
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
* Thunderbolt -> LG Ultrafine 5k
* MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
* USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
* SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
* MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.

DGPU
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multiple Display DP -> 4k240hz + 4k144hz
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
* MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)

The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
* Changing display configurations and settings
* Video/Audio playback
* Benchmark testing
* Suspend/Resume testing
* Feature testing (Freesync, HDCP, etc.)

Automated testing includes (but is not limited to)
* Script testing (scripts to automate some of the manual checks)
* IGT testing

The testing is mainly tested on the following displays, but occasionally there are tests with other displays
* Samsung G8 Neo 4k240hz
* Samsung QN55QN95B 4k 120hz
* Acer XV322QKKV 4k144hz
* HP U27 4k Wireless 4k60hz
* LG 27UD58B 4k60hz
* LG 32UN650WA 4k60hz
* LG Ultrafine 5k 5k60hz
* AU Optronics B140HAN01.1 1080p 60hz eDP
* AU Optronics B160UAN01.J 1920x1200 165hz eDP
* Samsung ATNA60YV02-0 3840x2400 60Hz OLED eDP

The patchset consists of the amd-staging-drm-next branch (Head commit - bb12c5af081eb863715b4d11bcf6d4ec2d7af896 -> drm/amd/pm: Remove wm_low and wm_high fields from amdgpu_crtc (v2)) with new patches added on top of it.

Tested on Ubuntu 24.04.3, on Wayland and X11, using Gnome.

Tested-by Dan Wheeler <[email protected]>

Thank you,

Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
amd.com

-----Original Message-----
From: waynelin <[email protected]>
Sent: Monday, September 1, 2025 8:43 PM
To: [email protected]
Cc: Wentland, Harry <[email protected]>; Li, Sun peng (Leo) <[email protected]>; Pillai, Aurabindo <[email protected]>; Li, Roman <[email protected]>; Lin, Wayne <[email protected]>; Chung, ChiaHsuan (Tom) <[email protected]>; Zuo, Jerry <[email protected]>; Wheeler, Daniel <[email protected]>; Wu, Ray <[email protected]>; LIPSKI, IVAN <[email protected]>; Hung, Alex <[email protected]>; Lin, Wayne <[email protected]>
Subject: [PATCH 00/11] DC Patches for September 8, 2025