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gpio: tegra186: Use generic macro for port definitions

PATCH Superseded Kartik Rajput 2 participants 5 messages Oct 10, 2025

Subsystems (2)
GPIO Tegra architecture support

v3 of 4 Superseded Latest is v4 →

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Kartik Rajput

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#0 lore raw

PATCH v3 1/2 gpio: tegra186: Use generic macro for port definitions

Introduce a generic macro TEGRA_GPIO_PORT to define SoC specific ports macros. This simplifies the code and avoids unnecessary duplication.

Suggested-by Jon Hunter <[email protected]>
Signed-off-by Kartik Rajput <[email protected]>
---
 drivers/gpio/gpio-tegra186.c | 87 +++++++++++-------------------------
 1 file changed, 25 insertions(+), 62 deletions(-)
drivers/gpio/gpio-tegra186.c +25 -62
index 4d3db6e06eeb..7ea541d6d537 100644
@@ -1002,14 +1002,17 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
 	return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
 }
 
-#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA186_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
+#define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \
+	[_prefix##_GPIO_PORT_##_name] = { \
+		.name = #_name, \
+		.bank = _bank, \
+		.port = _port, \
+		.pins = _pins, \
 	}
 
+#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins)
+
 static const struct tegra_gpio_port tegra186_main_ports[] = {
 	TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
 	TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),

@@ -1045,13 +1048,8 @@ static const struct tegra_gpio_soc tegra186_main_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA186_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra186_aon_ports[] = {
 	TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),

@@ -1073,13 +1071,8 @@ static const struct tegra_gpio_soc tegra186_aon_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA194_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra194_main_ports[] = {
 	TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),

@@ -1129,13 +1122,8 @@ static const struct tegra_gpio_soc tegra194_main_soc = {
 	.has_vm_support = true,
 };
 
-#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA194_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra194_aon_ports[] = {
 	TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),

@@ -1155,13 +1143,8 @@ static const struct tegra_gpio_soc tegra194_aon_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA234_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra234_main_ports[] = {
 	TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),

@@ -1200,13 +1183,8 @@ static const struct tegra_gpio_soc tegra234_main_soc = {
 	.has_vm_support = true,
 };
 
-#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA234_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra234_aon_ports[] = {
 	TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),

@@ -1227,13 +1205,8 @@ static const struct tegra_gpio_soc tegra234_aon_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA241_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra241_main_ports[] = {
 	TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),

@@ -1258,13 +1231,8 @@ static const struct tegra_gpio_soc tegra241_main_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA241_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra241_aon_ports[] = {
 	TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),

@@ -1280,13 +1248,8 @@ static const struct tegra_gpio_soc tegra241_aon_soc = {
 	.has_vm_support = false,
 };
 
-#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA256_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
 
 static const struct tegra_gpio_port tegra256_main_ports[] = {
 	TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8),
Signature · 1 line
2.43.0
author
#1 lore raw

PATCH v3 2/2 gpio: tegra186: Add support for Tegra410

From: Prathamesh Shete <[email protected]>

Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra410. Tegra410 supports two GPIO controllers referred to as 'COMPUTE' and 'SYSTEM'.

Co-developed-by Nathan Hartman <[email protected]>
Signed-off-by Nathan Hartman <[email protected]>
Signed-off-by Prathamesh Shete <[email protected]>
Signed-off-by Kartik Rajput <[email protected]>

---
v2 -> v3:
* Add a generic TEGRA_GPIO_PORT macro and use it to define TEGRA410_COMPUTE_GPIO_PORT and TEGRA410_SYSTEM_GPIO_PORT.
v1 -> v2:
* Move Tegra410 GPIO Ports definition to gpio-tegra186.c
* Rename Tegra410 Main GPIO as System GPIO.
* Add Compute GPIOs.
* Update ACPI IDs.
* Set instance ID as 0 for SYSTEM and COMPUTE GPIOs.
* Added Nathan as co-author for adding compute GPIO support and renaming MAIN GPIOs as SYSTEM GPIOs.

---
 drivers/gpio/gpio-tegra186.c | 82 +++++++++++++++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)
drivers/gpio/gpio-tegra186.c +81 -1
index 7ea541d6d537..c6ebe29f9cf1 100644
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2022 NVIDIA Corporation
+ * Copyright (c) 2016-2025 NVIDIA Corporation
  *
  * Author: Thierry Reding <[email protected]>
  *	   Dipen Patel <[email protected]>

@@ -69,6 +69,36 @@
 
 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
 
+/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */
+#define TEGRA410_COMPUTE_GPIO_PORT_A 0
+#define TEGRA410_COMPUTE_GPIO_PORT_B 1
+#define TEGRA410_COMPUTE_GPIO_PORT_C 2
+#define TEGRA410_COMPUTE_GPIO_PORT_D 3
+#define TEGRA410_COMPUTE_GPIO_PORT_E 4
+
+#define TEGRA410_COMPUTE_GPIO(port, offset) \
+	((TEGRA410_COMPUTE_GPIO_PORT_##port * 8) + (offset))
+
+/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */
+#define TEGRA410_SYSTEM_GPIO_PORT_A 0
+#define TEGRA410_SYSTEM_GPIO_PORT_B 1
+#define TEGRA410_SYSTEM_GPIO_PORT_C 2
+#define TEGRA410_SYSTEM_GPIO_PORT_D 3
+#define TEGRA410_SYSTEM_GPIO_PORT_E 4
+#define TEGRA410_SYSTEM_GPIO_PORT_I 5
+#define TEGRA410_SYSTEM_GPIO_PORT_J 6
+#define TEGRA410_SYSTEM_GPIO_PORT_K 7
+#define TEGRA410_SYSTEM_GPIO_PORT_L 8
+#define TEGRA410_SYSTEM_GPIO_PORT_M 9
+#define TEGRA410_SYSTEM_GPIO_PORT_N 10
+#define TEGRA410_SYSTEM_GPIO_PORT_P 11
+#define TEGRA410_SYSTEM_GPIO_PORT_Q 12
+#define TEGRA410_SYSTEM_GPIO_PORT_R 13
+#define TEGRA410_SYSTEM_GPIO_PORT_V 14
+
+#define TEGRA410_SYSTEM_GPIO(port, offset) \
+	((TEGRA410_SYSTEM_GPIO_PORT_##port * 8) + (offset))
+
 struct tegra_gpio_port {
 	const char *name;
 	unsigned int bank;

@@ -1267,6 +1297,54 @@ static const struct tegra_gpio_soc tegra256_main_soc = {
 	.has_vm_support = true,
 };
 
+#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins)	\
+	TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra410_compute_ports[] = {
+	TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3),
+	TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8),
+	TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3),
+	TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8),
+	TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8),
+};
+
+static const struct tegra_gpio_soc tegra410_compute_soc = {
+	.num_ports = ARRAY_SIZE(tegra410_compute_ports),
+	.ports = tegra410_compute_ports,
+	.name = "tegra410-gpio-compute",
+	.num_irqs_per_bank = 8,
+	.instance = 0,
+};
+
+#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins)	\
+	TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra410_system_ports[] = {
+	TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7),
+	TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8),
+	TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8),
+	TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8),
+	TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6),
+	TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8),
+	TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7),
+	TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7),
+	TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7),
+	TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7),
+	TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6),
+	TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8),
+	TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3),
+	TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2),
+	TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2),
+};
+
+static const struct tegra_gpio_soc tegra410_system_soc = {
+	.num_ports = ARRAY_SIZE(tegra410_system_ports),
+	.ports = tegra410_system_ports,
+	.name = "tegra410-gpio-system",
+	.num_irqs_per_bank = 8,
+	.instance = 0,
+};
+
 static const struct of_device_id tegra186_gpio_of_match[] = {
 	{
 		.compatible = "nvidia,tegra186-gpio",

@@ -1302,6 +1380,8 @@ static const struct acpi_device_id  tegra186_gpio_acpi_match[] = {
 	{ .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
 	{ .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
 	{ .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
+	{ .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc },
+	{ .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc },
 	{}
 };
 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
Signature · 1 line
2.43.0
maintainer
#2 lore raw

Re: [PATCH v3 2/2] gpio: tegra186: Add support for Tegra410

Quoted 41 lines · Kartik Rajput

From: Prathamesh Shete <[email protected]>

Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra410. Tegra410 supports two GPIO controllers referred to as 'COMPUTE' and 'SYSTEM'.

Co-developed-by Nathan Hartman <[email protected]>
Signed-off-by Nathan Hartman <[email protected]>
Signed-off-by Prathamesh Shete <[email protected]>
Signed-off-by Kartik Rajput <[email protected]>

---
v2 -> v3:
* Add a generic TEGRA_GPIO_PORT macro and use it to define TEGRA410_COMPUTE_GPIO_PORT and TEGRA410_SYSTEM_GPIO_PORT.
v1 -> v2:
* Move Tegra410 GPIO Ports definition to gpio-tegra186.c
* Rename Tegra410 Main GPIO as System GPIO.
* Add Compute GPIOs.
* Update ACPI IDs.
* Set instance ID as 0 for SYSTEM and COMPUTE GPIOs.
* Added Nathan as co-author for adding compute GPIO support and renaming MAIN GPIOs as SYSTEM GPIOs.

---
  drivers/gpio/gpio-tegra186.c | 82 +++++++++++++++++++++++++++++++++++-
  1 file changed, 81 insertions(+), 1 deletion(-)
drivers/gpio/gpio-tegra186.c +1 -1
index 7ea541d6d537..c6ebe29f9cf1 100644
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0-only
  /*
- * Copyright (c) 2016-2022 NVIDIA Corporation
+ * Copyright (c) 2016-2025 NVIDIA Corporation
   *
   * Author: Thierry Reding <[email protected]>
   *	   Dipen Patel <[email protected]>

@@ -69,6 +69,36 @@
 
  #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)

drivers/gpio/gpio-tegra186.c line 80

Quoted 10 lines
drivers/gpio/gpio-tegra186.c +9 -0
 
+/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */
+#define TEGRA410_COMPUTE_GPIO_PORT_A 0
+#define TEGRA410_COMPUTE_GPIO_PORT_B 1
+#define TEGRA410_COMPUTE_GPIO_PORT_C 2
+#define TEGRA410_COMPUTE_GPIO_PORT_D 3
+#define TEGRA410_COMPUTE_GPIO_PORT_E 4
+
+#define TEGRA410_COMPUTE_GPIO(port, offset) \
+	((TEGRA410_COMPUTE_GPIO_PORT_##port * 8) + (offset))

This macro does not appear to be used anywhere.

Quoted 9 lines
drivers/gpio/gpio-tegra186.c +9 -0
+/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */
+#define TEGRA410_SYSTEM_GPIO_PORT_A 0
+#define TEGRA410_SYSTEM_GPIO_PORT_B 1
+#define TEGRA410_SYSTEM_GPIO_PORT_C 2
+#define TEGRA410_SYSTEM_GPIO_PORT_D 3
+#define TEGRA410_SYSTEM_GPIO_PORT_E 4
+#define TEGRA410_SYSTEM_GPIO_PORT_I 5
+#define TEGRA410_SYSTEM_GPIO_PORT_J 6
+#define TEGRA410_SYSTEM_GPIO_PORT_K 7

drivers/gpio/gpio-tegra186.c line 100

Quoted 10 lines
drivers/gpio/gpio-tegra186.c +10 -0
+#define TEGRA410_SYSTEM_GPIO_PORT_L 8
+#define TEGRA410_SYSTEM_GPIO_PORT_M 9
+#define TEGRA410_SYSTEM_GPIO_PORT_N 10
+#define TEGRA410_SYSTEM_GPIO_PORT_P 11
+#define TEGRA410_SYSTEM_GPIO_PORT_Q 12
+#define TEGRA410_SYSTEM_GPIO_PORT_R 13
+#define TEGRA410_SYSTEM_GPIO_PORT_V 14
+
+#define TEGRA410_SYSTEM_GPIO(port, offset) \
+	((TEGRA410_SYSTEM_GPIO_PORT_##port * 8) + (offset))

Same here.

Jon

Signature · 1 line
nvpublic
author
#3 lore raw

Re: [PATCH v3 2/2] gpio: tegra186: Add support for Tegra410

Quoted 76 lines · Jon Hunter
Quoted 39 lines · Kartik Rajput

From: Prathamesh Shete <[email protected]>

Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra410. Tegra410 supports two GPIO controllers referred to as 'COMPUTE' and 'SYSTEM'.

Co-developed-by Nathan Hartman <[email protected]>
Signed-off-by Nathan Hartman <[email protected]>
Signed-off-by Prathamesh Shete <[email protected]>
Signed-off-by Kartik Rajput <[email protected]>

---
v2 -> v3:
         * Add a generic TEGRA_GPIO_PORT macro and use it to define TEGRA410_COMPUTE_GPIO_PORT and TEGRA410_SYSTEM_GPIO_PORT. v1 -> v2:
         * Move Tegra410 GPIO Ports definition to gpio-tegra186.c
         * Rename Tegra410 Main GPIO as System GPIO.
         * Add Compute GPIOs.
         * Update ACPI IDs.
         * Set instance ID as 0 for SYSTEM and COMPUTE GPIOs.
         * Added Nathan as co-author for adding compute GPIO support and renaming MAIN GPIOs as SYSTEM GPIOs.
---
  drivers/gpio/gpio-tegra186.c | 82 +++++++++++++++++++++++++++++++++++-

  1 file changed, 81 insertions(+), 1 deletion(-)
drivers/gpio/gpio-tegra186.c +1 -1
index 7ea541d6d537..c6ebe29f9cf1 100644
@@ -1,6 +1,6 @@
   // SPDX-License-Identifier: GPL-2.0-only
   /*
- * Copyright (c) 2016-2022 NVIDIA Corporation
+ * Copyright (c) 2016-2025 NVIDIA Corporation
    *
    * Author: Thierry Reding <[email protected]>
    *       Dipen Patel <[email protected]>

drivers/gpio/gpio-tegra186.c line 78

Quoted 10 lines
drivers/gpio/gpio-tegra186.c +9 -0
@@ -69,6 +69,36 @@
   #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
+/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */
+#define TEGRA410_COMPUTE_GPIO_PORT_A 0
+#define TEGRA410_COMPUTE_GPIO_PORT_B 1
+#define TEGRA410_COMPUTE_GPIO_PORT_C 2
+#define TEGRA410_COMPUTE_GPIO_PORT_D 3
+#define TEGRA410_COMPUTE_GPIO_PORT_E 4
+
+#define TEGRA410_COMPUTE_GPIO(port, offset) \
+    ((TEGRA410_COMPUTE_GPIO_PORT_##port * 8) + (offset))

This macro does not appear to be used anywhere.

Quoted 9 lines
drivers/gpio/gpio-tegra186.c +9 -0
+/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */
+#define TEGRA410_SYSTEM_GPIO_PORT_A 0
+#define TEGRA410_SYSTEM_GPIO_PORT_B 1
+#define TEGRA410_SYSTEM_GPIO_PORT_C 2
+#define TEGRA410_SYSTEM_GPIO_PORT_D 3
+#define TEGRA410_SYSTEM_GPIO_PORT_E 4
+#define TEGRA410_SYSTEM_GPIO_PORT_I 5
+#define TEGRA410_SYSTEM_GPIO_PORT_J 6
+#define TEGRA410_SYSTEM_GPIO_PORT_K 7

drivers/gpio/gpio-tegra186.c line 100

Quoted 10 lines
drivers/gpio/gpio-tegra186.c +10 -0
+#define TEGRA410_SYSTEM_GPIO_PORT_L 8
+#define TEGRA410_SYSTEM_GPIO_PORT_M 9
+#define TEGRA410_SYSTEM_GPIO_PORT_N 10
+#define TEGRA410_SYSTEM_GPIO_PORT_P 11
+#define TEGRA410_SYSTEM_GPIO_PORT_Q 12
+#define TEGRA410_SYSTEM_GPIO_PORT_R 13
+#define TEGRA410_SYSTEM_GPIO_PORT_V 14
+
+#define TEGRA410_SYSTEM_GPIO(port, offset) \
+    ((TEGRA410_SYSTEM_GPIO_PORT_##port * 8) + (offset))

Same here.

Quoted 2 lines

Jon

Hi Jon,

You're right, TEGRA410_COMPUTE_GPIO() and TEGRA410_SYSTEM_GPIO() macros aren't used. I will remove these two in v4.

Thanks,
Kartik

maintainer Reviewed-by on v3 1/2
#4 lore raw
In reply to Kartik Rajput
Quoted 156 lines · Kartik Rajput

Introduce a generic macro TEGRA_GPIO_PORT to define SoC specific ports macros. This simplifies the code and avoids unnecessary duplication.

Suggested-by Jon Hunter <[email protected]>
Signed-off-by Kartik Rajput <[email protected]>
---
  drivers/gpio/gpio-tegra186.c | 87 +++++++++++-------------------------
  1 file changed, 25 insertions(+), 62 deletions(-)
drivers/gpio/gpio-tegra186.c +23 -57
index 4d3db6e06eeb..7ea541d6d537 100644
@@ -1002,14 +1002,17 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
  	return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
  }
 
-#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA186_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
+#define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \
+	[_prefix##_GPIO_PORT_##_name] = { \
+		.name = #_name, \
+		.bank = _bank, \
+		.port = _port, \
+		.pins = _pins, \
  	}
 
+#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins)
+
  static const struct tegra_gpio_port tegra186_main_ports[] = {
  	TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
  	TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),

@@ -1045,13 +1048,8 @@ static const struct tegra_gpio_soc tegra186_main_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA186_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra186_aon_ports[] = {
  	TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),

@@ -1073,13 +1071,8 @@ static const struct tegra_gpio_soc tegra186_aon_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA194_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra194_main_ports[] = {
  	TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),

@@ -1129,13 +1122,8 @@ static const struct tegra_gpio_soc tegra194_main_soc = {
  	.has_vm_support = true,
  };
 
-#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA194_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra194_aon_ports[] = {
  	TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),

@@ -1155,13 +1143,8 @@ static const struct tegra_gpio_soc tegra194_aon_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA234_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra234_main_ports[] = {
  	TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),

@@ -1200,13 +1183,8 @@ static const struct tegra_gpio_soc tegra234_main_soc = {
  	.has_vm_support = true,
  };
 
-#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA234_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra234_aon_ports[] = {
  	TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),

@@ -1227,13 +1205,8 @@ static const struct tegra_gpio_soc tegra234_aon_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA241_MAIN_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra241_main_ports[] = {
  	TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),

@@ -1258,13 +1231,8 @@ static const struct tegra_gpio_soc tegra241_main_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA241_AON_GPIO_PORT_##_name] = {			\
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra241_aon_ports[] = {
  	TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),

@@ -1280,13 +1248,8 @@ static const struct tegra_gpio_soc tegra241_aon_soc = {
  	.has_vm_support = false,
  };
 
-#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins)	\
-	[TEGRA256_MAIN_GPIO_PORT_##_name] = {			\

drivers/gpio/gpio-tegra186.c static const struct tegra_gpio_soc tegra241_aon_soc = { · line 1255

Quoted 10 lines
drivers/gpio/gpio-tegra186.c +2 -5
-		.name = #_name,					\
-		.bank = _bank,					\
-		.port = _port,					\
-		.pins = _pins,					\
-	}
+#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+	TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
 
  static const struct tegra_gpio_port tegra256_main_ports[] = {
  	TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8),

Thanks! Looks good to me ...

Reviewed-by Jon Hunter <[email protected]>

Jon

Signature · 1 line
nvpublic