net/ena: add Rx HW timestamping support

92 lines not on this page · raw message

index 82306aaa9c..bc8e88c7ae 100644
@@ -1155,6 +1155,38 @@ static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_d
 	ena_dev->adaptive_coalescing = false;
 }
 
+/* ena_com_hw_timestamping_supported - query whether HW timestamping is
+ *                                     supported by the device
+ * @ena_dev: ENA communication layer struct
+ *
+ * @return - true if the feature is supported or false otherwise
+ */
+bool ena_com_hw_timestamping_supported(struct ena_com_dev *ena_dev);
+
+/* ena_com_get_hw_timestamping_support - query HW timestamping support options
+ *                                       in the device
+ * @ena_dev: ENA communication layer struct
+ * @tx_support: Will hold the TX side supported options
+ * @rx_support: Will hold the RX side supported options
+ *
+ * @return - 0 on success, negative value on failure.
+ */
+int ena_com_get_hw_timestamping_support(struct ena_com_dev *ena_dev,
+					u8 *tx_support,
+					u8 *rx_support);
+
+/* ena_com_set_hw_timestamping_configuration - set HW timestamping configuration
+ *
+ * @ena_dev: ENA communication layer struct
+ * @tx_enable: Enable/Disable TX HW timestamping
+ * @rx_enable: Enable/Disable RX HW timestamping
+ *
+ * @return - 0 on success, negative value on failure.
+ */
+int ena_com_set_hw_timestamping_configuration(struct ena_com_dev *ena_dev,
+					      u8 tx_enable,
+					      u8 rx_enable);
+
 bool ena_com_indirection_table_config_supported(struct ena_com_dev *ena_dev);
 /* ena_com_get_cap - query whether device supports a capability.
  * @ena_dev: ENA communication layer struct

74 lines not on this page · raw message

index f35bba3202..bae3b85911 100644
@@ -166,9 +166,9 @@ struct ena_eth_io_tx_cdesc {
 struct ena_eth_io_tx_cdesc_ext {
 	struct ena_eth_io_tx_cdesc base;
 
-	uint32_t reserved_w2;
+	uint32_t timestamp_low;
 
-	uint32_t reserved_w3;
+	uint32_t timestamp_high;
 };
 
 struct ena_eth_io_rx_desc {

@@ -263,9 +263,9 @@ struct ena_eth_io_rx_cdesc_ext {
 
 	uint16_t reserved16;
 
-	uint32_t reserved_w6;
+	uint32_t timestamp_low;
 
-	uint32_t reserved_w7;
+	uint32_t timestamp_high;
 };
 
 struct ena_eth_io_intr_reg {

index 212adc7d1f..7d982854c0 100644
@@ -56,6 +56,11 @@ void ena_com_dump_single_rx_cdesc(struct ena_com_io_cq *io_cq,
 				ENA_FIELD_GET(desc->base.status,
 					(uint32_t)ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK,
 					ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT));
+		if (unlikely(ena_com_is_extended_rx_cdesc(io_cq)))
+			ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq),
+				    "RX descriptor timestamp %" ENA_PRIu64 "(nsec)",
+				    (uint64_t)desc->timestamp_low |
+				    (uint64_t)desc->timestamp_high << 32);
 	}
 }
 

@@ -74,6 +79,12 @@ void ena_com_dump_single_tx_cdesc(struct ena_com_io_cq *io_cq,
 			    ENA_FIELD_GET(desc->base.flags,
 				(uint32_t)ENA_ETH_IO_TX_CDESC_MBZ6_MASK,
 				ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT));
+
+		if (unlikely(ena_com_is_extended_tx_cdesc(io_cq)))
+			ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq),
+				    "TX descriptor timestamp %" ENA_PRIu64 "(nsec)",
+				    (uint64_t)desc->timestamp_low |
+				    (uint64_t)desc->timestamp_high << 32);
 	}
 }
 

@@ -683,6 +694,10 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
 	/* Get rx flags from the last pkt */
 	ena_com_rx_set_flags(ena_rx_ctx, cdesc);
 
+	if (unlikely(ena_com_is_extended_rx_cdesc(io_cq)))
+		ena_rx_ctx->timestamp = (u64)cdesc->timestamp_low |
+					(u64)cdesc->timestamp_high << 32;
+
 	ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
 		    "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n",
 		    ena_rx_ctx->l3_proto,

index e56eb2c173..f25e26840d 100644
@@ -60,6 +60,7 @@ struct ena_com_rx_ctx {
 	u16 descs;
 	u16 max_bufs;
 	u8 pkt_offset;
+	u64 timestamp;
 };
 
 int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,

@@ -234,8 +235,9 @@ static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)
 		io_cq->phase ^= 1;
 }
 
-static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
-					     u16 *req_id)
+static inline int ena_com_tx_comp_metadata_get(struct ena_com_io_cq *io_cq,
+					       u16 *req_id,
+					       u64 *hw_timestamp)
 {
 	struct ena_com_dev *dev = ena_com_io_cq_to_ena_dev(io_cq);
 	struct ena_eth_io_tx_cdesc_ext *cdesc;

@@ -279,6 +281,10 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
 		return ENA_COM_INVAL;
 	}
 
+	if (unlikely(ena_com_is_extended_tx_cdesc(io_cq)))
+		*hw_timestamp = (u64)cdesc->timestamp_low |
+				(u64)cdesc->timestamp_high << 32;
+
 	ena_com_cq_inc_head(io_cq);
 
 	return 0;

133 lines not on this page · raw message

index 830135bcfd..6a3b004653 100644
@@ -141,6 +141,18 @@ struct ena_stats_rx {
 	u64 unknown_error;
 };
 
+struct ena_timestamp_config {
+	u8 hw_tx_supported;
+	u8 hw_rx_supported;
+};
+
+struct ena_timestamp_mbuf {
+	/* Dynamic mbuf timestamp flag */
+	uint64_t rx_flag;
+	/* Dynamic mbuf timestamp field offset */
+	int offset;
+};
+
 struct __rte_cache_aligned ena_ring {
 	u16 next_to_use;
 	u16 next_to_clean;

@@ -199,6 +211,9 @@ struct __rte_cache_aligned ena_ring {
 	unsigned int numa_socket_id;
 
 	uint32_t missing_tx_completion_threshold;
+
+	/* Dynamic mbuf params for HW timestamping */
+	struct ena_timestamp_mbuf ts_mbuf;
 };
 
 enum ena_adapter_state {

@@ -350,6 +365,9 @@ struct ena_adapter {
 	uint64_t control_path_poll_interval;
 
 	bool enable_frag_bypass;
+
+	/* HW timestamp support by the device */
+	struct ena_timestamp_config ts;
 	/*
 	 * Helper variables for holding the information about the supported
 	 * metrics.