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dt-bindings: PCI: amlogic,axg-pcie: Fix select schema

PATCH Applied Rob Herring (Arm) 3 participants 3 messages Oct 24, 2025 – Oct 26, 2025

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Rob Herring (Arm)

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#0 lore raw

PATCH 1/1 dt-bindings: PCI: amlogic,axg-pcie: Fix select schema

The amlogic,axg-pcie binding was never enabled as the 'select' schema expects a single compatible value, but the binding has a fallback compatible. Fix the 'select' by adding a 'contains'. With this, several errors in the clock and reset properties are exposed. Some of the names aren't defined in the common DWC schema and the order of clocks entries doesn't match .dts files.

---
 .../bindings/pci/amlogic,axg-pcie.yaml          | 17 +++++++++--------
 .../bindings/pci/snps,dw-pcie-common.yaml       |  6 +++---
 2 files changed, 12 insertions(+), 11 deletions(-)
Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml +9 -8
index 79a21ba0f9fd..bee694ff45f3 100644
@@ -20,9 +20,10 @@ allOf:
 select:
   properties:
     compatible:
-      enum:
-        - amlogic,axg-pcie
-        - amlogic,g12a-pcie
+      contains:
+        enum:
+          - amlogic,axg-pcie
+          - amlogic,g12a-pcie
   required:
     - compatible
 
@@ -51,15 +52,15 @@ properties:
 
   clocks:
     items:
+      - description: PCIe PHY clock
       - description: PCIe GEN 100M PLL clock
       - description: PCIe RC clock gate
-      - description: PCIe PHY clock
 
   clock-names:
     items:
+      - const: general
       - const: pclk
       - const: port
-      - const: general
 
   phys:
     maxItems: 1
@@ -88,7 +89,7 @@ required:
   - reg
   - reg-names
   - interrupts
-  - clock
+  - clocks
   - clock-names
   - "#address-cells"
   - "#size-cells"
@@ -115,8 +116,8 @@ examples:
         reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;
         reg-names = "elbi", "cfg", "config";
         interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
-        clocks = <&pclk>, <&clk_port>, <&clk_phy>;
-        clock-names = "pclk", "port", "general";
+        clocks = <&clk_phy>, <&pclk>, <&clk_port>;
+        clock-names = "general", "pclk", "port";
         resets = <&reset_pcie_port>, <&reset_pcie_apb>;
         reset-names = "port", "apb";
         phys = <&pcie_phy>;
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml +3 -3
index 34594972d8db..6339a76499b2 100644
@@ -115,11 +115,11 @@ properties:
             above for new bindings.
           oneOf:
             - description: See native 'dbi' clock for details
-              enum: [ pcie, pcie_apb_sys, aclk_dbi, reg ]
+              enum: [ pcie, pcie_apb_sys, aclk_dbi, reg, port ]
             - description: See native 'mstr/slv' clock for details
               enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]
             - description: See native 'pipe' clock for details
-              enum: [ pcie_phy, pcie_phy_ref, link ]
+              enum: [ pcie_phy, pcie_phy_ref, link, general ]
             - description: See native 'aux' clock for details
               enum: [ pcie_aux ]
             - description: See native 'ref' clock for details.
@@ -176,7 +176,7 @@ properties:
             - description: See native 'phy' reset for details
               enum: [ pciephy, link ]
             - description: See native 'pwr' reset for details
-              enum: [ turnoff ]
+              enum: [ turnoff, port ]
 
   phys:
     description:
Signature · 1 line
2.51.0
Acked-by on v1 1/1
#1 lore raw
Quoted 8 lines · Rob Herring (Arm)

The amlogic,axg-pcie binding was never enabled as the 'select' schema expects a single compatible value, but the binding has a fallback compatible. Fix the 'select' by adding a 'contains'. With this, several errors in the clock and reset properties are exposed. Some of the names aren't defined in the common DWC schema and the order of clocks entries doesn't match .dts files.

maintainer Applied
#2 lore raw
In reply to Rob Herring (Arm)
Quoted 8 lines · Rob Herring (Arm)

The amlogic,axg-pcie binding was never enabled as the 'select' schema expects a single compatible value, but the binding has a fallback compatible. Fix the 'select' by adding a 'contains'. With this, several errors in the clock and reset properties are exposed. Some of the names aren't defined in the common DWC schema and the order of clocks entries doesn't match .dts files.

[...]

Applied, thanks!

[1/1] dt-bindings: PCI: amlogic,axg-pcie: Fix select schema

      commit: 7411850df8e460d5e8319f3c020d03a88fa2dbc7

Best regards,

Signature · 1 line
Manivannan Sadhasivam <[email protected]>