PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

PATCH Applied Manivannan Sadhasivam 5 participants 9 messages Nov 26, 2025 – Dec 30, 2025

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Arm Qualcomm mailing list PCI PCI native host bridge and endpoint drivers PCIe driver for Qualcomm msm

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Manivannan Sadhasivam

author

2025-11-26 08:17 UTC #0 lore raw

PATCH 1/1 PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

From: Manivannan Sadhasivam <[email protected]>

Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.

Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.

Reported-by Dmitry Baryshkov <[email protected]>

Closes https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf open here

Signed-off-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/pci/controller/dwc/pcie-qcom.c +3 -1

index 805edbbfe7eb..25399d47fc40 100644
@@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
 
-	qcom_pcie_clear_aspm_l0s(pcie->pci);
 	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;

@@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_disable_phy;
 	}
 
+	qcom_pcie_clear_aspm_l0s(pcie->pci);
+
 	qcom_ep_reset_deassert(pcie);
 
 	if (pcie->cfg->ops->config_sid) {

@@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
 
 static const struct qcom_pcie_cfg cfg_2_3_2 = {
 	.ops = &ops_2_3_2,
+	.no_l0s = true,
 };
 
 static const struct qcom_pcie_cfg cfg_2_3_3 = {

Signature · 1 line

2.48.1

Dmitry Baryshkov

Tested-by on v1 1/1

2025-11-26 08:47 UTC #1 lore raw

Quoted 9 lines · Manivannan Sadhasivam

From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.
Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.

Quoted 7 lines

Reported-by Dmitry Baryshkov <[email protected]>
Closes https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf open here
Signed-off-by Manivannan Sadhasivam <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Tested-by Dmitry Baryshkov <[email protected]>

Thanks!

Signature · 2 lines

With best wishes
Dmitry

Konrad Dybcio

2025-11-27 10:55 UTC #2 lore raw

In reply to Manivannan Sadhasivam

Quoted 5 lines · Manivannan Sadhasivam

From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.

FWIW if we trust the downstream DT, we have this hunk:

arch/arm64/boot/dts/qcom/msm8996.dtsi

1431:           qcom,l1-supported;
1432:           qcom,l1ss-supported;
1586:           qcom,l1-supported;
1587:           qcom,l1ss-supported;
1739:           qcom,l1-supported;
1740:           qcom,l1ss-supported;

But also funnily enough, msm8996auto boards specifically manually do a /delete-property/ on those..

(there exists one 'qcom,l0s-supported', but it's NOT set for 8996, 98, or 845)

On msm-4.14, this became "qcom,no-l0s/l1/l1ss-supported". This forbids L0s on at least 8150 and 8250.

Later, both hosts on SM8350 and SM8450-PCIe0 (not 1) forbid L0s.

SM8350-PCIe0 sets 'qcom,l1ss-sleep-disable' which influences some RPMh things, but also prevents some clock ops wrt the CLKREF source

There's probably more platforms affected, this was a quick grep.

Konrad

Manivannan Sadhasivam

maintainer

2025-11-27 13:56 UTC #3 lore raw

Quoted 20 lines · Konrad Dybcio

Quoted 5 lines · Manivannan Sadhasivam
From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.
FWIW if we trust the downstream DT, we have this hunk:
arch/arm64/boot/dts/qcom/msm8996.dtsi
1431:           qcom,l1-supported;
1432:           qcom,l1ss-supported;
1586:           qcom,l1-supported;
1587:           qcom,l1ss-supported;
1739:           qcom,l1-supported;
1740:           qcom,l1ss-supported;
But also funnily enough, msm8996auto boards specifically manually do a /delete-property/ on those..

Quoted 8 lines

(there exists one 'qcom,l0s-supported', but it's NOT set for 8996, 98, or 845)
On msm-4.14, this became "qcom,no-l0s/l1/l1ss-supported". This forbids L0s on at least 8150 and 8250.
Later, both hosts on SM8350 and SM8450-PCIe0 (not 1) forbid L0s.

Thanks for digging in. Unfortunately, I have to rely on word of mouth to get the ASPM capability as there is no proper doc that says which SoC supports which state. And, I'm quite nervous to trust downstream DTS as they were not very accurate in describing the hardware capabilities. But I think we should atleast consider the 'no-l0s' properties seriously.

Let me go through all DTS and build try to build a sane ASPM compatibility table. But just be clear, the above exercise should not block this patch as it fixes a real issue that has been reported.

Quoted 3 lines

SM8350-PCIe0 sets 'qcom,l1ss-sleep-disable' which influences some RPMh things, but also prevents some clock ops wrt the CLKREF source

We can ignore 'qcom,l1ss-sleep-disable' as it is a Qcom low power feature built around PCIe L1ss, which is not yet supported in upstream.

- Mani

Signature · 1 line

மணிவண்ணன் சதாசிவம்

Konrad Dybcio

Reviewed-by

2025-11-27 14:12 UTC #4 lore raw

Quoted 36 lines · Manivannan Sadhasivam

Quoted 20 lines · Konrad Dybcio
Quoted 5 lines · Manivannan Sadhasivam
From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.
FWIW if we trust the downstream DT, we have this hunk:
arch/arm64/boot/dts/qcom/msm8996.dtsi
1431:           qcom,l1-supported;
1432:           qcom,l1ss-supported;
1586:           qcom,l1-supported;
1587:           qcom,l1ss-supported;
1739:           qcom,l1-supported;
1740:           qcom,l1ss-supported;
But also funnily enough, msm8996auto boards specifically manually do a /delete-property/ on those..
Quoted 8 lines
(there exists one 'qcom,l0s-supported', but it's NOT set for 8996, 98, or 845)
On msm-4.14, this became "qcom,no-l0s/l1/l1ss-supported". This forbids L0s on at least 8150 and 8250.
Later, both hosts on SM8350 and SM8450-PCIe0 (not 1) forbid L0s.
Thanks for digging in. Unfortunately, I have to rely on word of mouth to get the ASPM capability as there is no proper doc that says which SoC supports which state. And, I'm quite nervous to trust downstream DTS as they were not very accurate in describing the hardware capabilities. But I think we should atleast consider the 'no-l0s' properties seriously.

Quoted 3 lines

Let me go through all DTS and build try to build a sane ASPM compatibility table. But just be clear, the above exercise should not block this patch as it fixes a real issue that has been reported.

Yeah definitely

fwiw

Reviewed-by Konrad Dybcio <[email protected]>

Quoted 6 lines

Quoted 3 lines
SM8350-PCIe0 sets 'qcom,l1ss-sleep-disable' which influences some RPMh things, but also prevents some clock ops wrt the CLKREF source
We can ignore 'qcom,l1ss-sleep-disable' as it is a Qcom low power feature built around PCIe L1ss, which is not yet supported in upstream.

OK thanks

Konrad

Manivannan Sadhasivam

author Applied

2025-12-23 06:41 UTC #5 lore raw

In reply to Manivannan Sadhasivam

Quoted 8 lines · Manivannan Sadhasivam

Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.
Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.
[...]

Applied, thanks!

[1/1] PCI: qcom: Clear ASPM L0s CAP for MSM8996 SoC

      commit: 91f2fb5fe4735c6c99c000857f2e0bd7ebbddb95

Best regards,

Signature · 1 line

Manivannan Sadhasivam <[email protected]>

Bjorn Helgaas

2025-12-26 23:39 UTC #6 lore raw

In reply to Manivannan Sadhasivam

[+cc Val]

Quoted 5 lines · Manivannan Sadhasivam

From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.

I'm squinting a little bit about a Qcom engineer not being able to confirm whether L0s is known to work on a Qcom part :)

This looks like possible v6.19 material since it's a regression and Dmitry reported random resets that are impossible to debug?

For now I moved this to the beginning of pci/controller/dwc-qcom since it sounds like the PERST# series will be updated.

Quoted 42 lines

Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.

Reported-by Dmitry Baryshkov <[email protected]>

Closes https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf open here

Signed-off-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

drivers/pci/controller/dwc/pcie-qcom.c +3 -1

index 805edbbfe7eb..25399d47fc40 100644
@@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
 
-	qcom_pcie_clear_aspm_l0s(pcie->pci);
 	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;

@@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_disable_phy;
 	}
 
+	qcom_pcie_clear_aspm_l0s(pcie->pci);
+
 	qcom_ep_reset_deassert(pcie);
 
 	if (pcie->cfg->ops->config_sid) {

@@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
 
 static const struct qcom_pcie_cfg cfg_2_3_2 = {
 	.ops = &ops_2_3_2,
+	.no_l0s = true,
 };
 
 static const struct qcom_pcie_cfg cfg_2_3_3 = {

Signature · 1 line

2.48.1

Manivannan Sadhasivam

maintainer

2025-12-27 04:28 UTC #7 lore raw

Quoted 12 lines · Bjorn Helgaas

[+cc Val]
Quoted 5 lines · Manivannan Sadhasivam
From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.
I'm squinting a little bit about a Qcom engineer not being able to confirm whether L0s is known to work on a Qcom part :)

Unfortunately, all the folks who worked on this part no longer work at Qcom. And there is no credible documentation that affirms me that L0s is supported on this SoC.

Quoted 3 lines

This looks like possible v6.19 material since it's a regression and Dmitry reported random resets that are impossible to debug?

Yes. I was about to ping you offline the list of v6.19 materials once you got back from vacation.

- Mani

Quoted 45 lines

For now I moved this to the beginning of pci/controller/dwc-qcom since it sounds like the PERST# series will be updated.
Quoted 42 lines
Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.
Reported-by Dmitry Baryshkov <[email protected]>
Closes https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf open here
Signed-off-by Manivannan Sadhasivam <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/pci/controller/dwc/pcie-qcom.c +3 -1
index 805edbbfe7eb..25399d47fc40 100644
@@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
 
-	qcom_pcie_clear_aspm_l0s(pcie->pci);
 	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
@@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_disable_phy;
 	}
 
+	qcom_pcie_clear_aspm_l0s(pcie->pci);
+
 	qcom_ep_reset_deassert(pcie);
 
 	if (pcie->cfg->ops->config_sid) {
@@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
 
 static const struct qcom_pcie_cfg cfg_2_3_2 = {
 	.ops = &ops_2_3_2,
+	.no_l0s = true,
 };
 
 static const struct qcom_pcie_cfg cfg_2_3_3 = {
Signature · 1 line
2.48.1

Signature · 1 line

மணிவண்ணன் சதாசிவம்

Bjorn Helgaas

2025-12-30 17:14 UTC #8 lore raw

Quoted 9 lines · Manivannan Sadhasivam

Quoted 8 lines · Bjorn Helgaas
[+cc Val]
Quoted 5 lines · Manivannan Sadhasivam
From: Manivannan Sadhasivam <[email protected]>
Though I couldn't confirm the ASPM L0s support with the Qcom hardware team, bug report from Dmitry suggests that L0s is broken on this legacy SoC. Hence, clear the L0s CAP for the Root Ports in this SoC.

Quoted 7 lines

...
Quoted 2 lines
This looks like possible v6.19 material since it's a regression and Dmitry reported random resets that are impossible to debug?
Yes. I was about to ping you offline the list of v6.19 materials once you got back from vacation.

Thanks, I moved this to for-linus for v6.19 and updated pci/controller/dwc-qcom accordingly.

Quoted 48 lines

Quoted 45 lines
For now I moved this to the beginning of pci/controller/dwc-qcom since it sounds like the PERST# series will be updated.
Quoted 42 lines
Since qcom_pcie_clear_aspm_l0s() is now used by more than one SoC config, call it from qcom_pcie_host_init() instead.
Reported-by Dmitry Baryshkov <[email protected]>
Closes https://lore.kernel.org/linux-pci/4cp5pzmlkkht2ni7us6p3edidnk25l45xrp6w3fxguqcvhq2id@wjqqrdpkypkf open here
Signed-off-by Manivannan Sadhasivam <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/pci/controller/dwc/pcie-qcom.c +3 -1
index 805edbbfe7eb..25399d47fc40 100644
@@ -1088,7 +1088,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 		writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);
 
-	qcom_pcie_clear_aspm_l0s(pcie->pci);
 	qcom_pcie_clear_hpc(pcie->pci);
 
 	return 0;
@@ -1350,6 +1349,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
 			goto err_disable_phy;
 	}
 
+	qcom_pcie_clear_aspm_l0s(pcie->pci);
+
 	qcom_ep_reset_deassert(pcie);
 
 	if (pcie->cfg->ops->config_sid) {
@@ -1486,6 +1487,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
 
 static const struct qcom_pcie_cfg cfg_2_3_2 = {
 	.ops = &ops_2_3_2,
+	.no_l0s = true,
 };
 
 static const struct qcom_pcie_cfg cfg_2_3_3 = {
Signature · 1 line
2.48.1
Signature · 1 line
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