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clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock

PATCH In review Chen-Yu Tsai 3 participants 5 messages Feb 17 – Feb 24

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Common clk Arm/Allwinner sunXi SoC support
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Chen-Yu Tsai

author maintainer
#0 lore raw

PATCH 1/1 clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock

When the PRCM clk driver was added, somehow the r-spi module clock was skipped over.

Add it so that r-spi can actually work.

Fixes 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by Chen-Yu Tsai <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +16 -1
index 0339c4af0fe5..db0e36d8838e 100644
@@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
 static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
 			 &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
 
-/* SPI clock is /M/N (same as new MMC?) */
+static const struct clk_parent_data r_spi_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "pll-periph" },
+	{ .name = "pll-periph0-300M" },
+	{ .name = "pll-periph1-300M" },
+	{ .name = "pll-audio" },
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
+				  0, 5,		/* M */
+				  8, 5,		/* P */
+				  24, 3,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
 static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
 			 &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
+
 static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
 			 &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
 static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",

@@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
 	&bus_r_twd_clk.common,
 	&r_pwmctrl_clk.common,
 	&bus_r_pwmctrl_clk.common,
+	&r_spi_clk.common,
 	&bus_r_spi_clk.common,
 	&bus_r_spinlock_clk.common,
 	&bus_r_msgbox_clk.common,

@@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
 		[CLK_BUS_R_TWD]		= &bus_r_twd_clk.common.hw,
 		[CLK_R_PWMCTRL]		= &r_pwmctrl_clk.common.hw,
 		[CLK_BUS_R_PWMCTRL]	= &bus_r_pwmctrl_clk.common.hw,
+		[CLK_R_SPI]		= &r_spi_clk.common.hw,
 		[CLK_BUS_R_SPI]		= &bus_r_spi_clk.common.hw,
 		[CLK_BUS_R_SPINLOCK]	= &bus_r_spinlock_clk.common.hw,
 		[CLK_BUS_R_MSGBOX]	= &bus_r_msgbox_clk.common.hw,
Signature · 1 line
2.47.3
maintainer Reviewed-by on v1 1/1
#1 lore raw

Dne torek, 17. februar 2026 ob 10:30:03 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):

Quoted 7 lines

When the PRCM clk driver was added, somehow the r-spi module clock was skipped over.

Add it so that r-spi can actually work.

Fixes 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by Chen-Yu Tsai <[email protected]>
Reviewed-by Jernej Skrabec <[email protected]>

Best regards,
Jernej

Reviewed-by on v1 1/1
#2 lore raw
In reply to Chen-Yu Tsai

On Tue, 17 Feb 2026 17:30:03 +0800
Chen-Yu Tsai <[email protected]> wrote:

Hi,

Quoted 4 lines

When the PRCM clk driver was added, somehow the r-spi module clock was skipped over.

Add it so that r-spi can actually work.

The patch itself looks fine, compared against the manual, so for that:

Reviewed-by Andre Przywara <[email protected]>

But I noticed one thing below....

Quoted 11 lines
Fixes 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by Chen-Yu Tsai <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +0 -0
index 0339c4af0fe5..db0e36d8838e 100644

drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", · line 86

Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +0 -1
@@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
 static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
 			 &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
 
-/* SPI clock is /M/N (same as new MMC?) */

Ooops, looks like I saw that clock, but someone managed to dodge it :-( Sorry about that.

drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", · line 91

Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +6 -0
+static const struct clk_parent_data r_spi_parents[] = {
+	{ .fw_name = "hosc" },
+	{ .fw_name = "pll-periph" },
+	{ .name = "pll-periph0-300M" },
+	{ .name = "pll-periph1-300M" },
+	{ .name = "pll-audio" },

Looking a bit closer, all the PRCM PLL-AUDIO clocks in the manual refer to AUDIO1PLL4X, which is provided by the MCU CCU, not AUDIO0PLL4X provided by the main CCU. So we would need to change the DT? I wonder if that breaks boots with kernels which didn't know the MCU CCU yet (v6.15-v6.17)?

Cheers,
Andre.

Quoted 29 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +10 -0
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
+				  0, 5,		/* M */
+				  8, 5,		/* P */
+				  24, 3,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
 static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
 			 &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
+
 static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
 			 &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
 static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",

@@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
 	&bus_r_twd_clk.common,
 	&r_pwmctrl_clk.common,
 	&bus_r_pwmctrl_clk.common,
+	&r_spi_clk.common,
 	&bus_r_spi_clk.common,
 	&bus_r_spinlock_clk.common,
 	&bus_r_msgbox_clk.common,

@@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
 		[CLK_BUS_R_TWD]		= &bus_r_twd_clk.common.hw,
 		[CLK_R_PWMCTRL]		= &r_pwmctrl_clk.common.hw,
 		[CLK_BUS_R_PWMCTRL]	= &bus_r_pwmctrl_clk.common.hw,
+		[CLK_R_SPI]		= &r_spi_clk.common.hw,
 		[CLK_BUS_R_SPI]		= &bus_r_spi_clk.common.hw,
 		[CLK_BUS_R_SPINLOCK]	= &bus_r_spinlock_clk.common.hw,
 		[CLK_BUS_R_MSGBOX]	= &bus_r_msgbox_clk.common.hw,
author maintainer
#3 lore raw
Quoted 43 lines · Andre Przywara

On Tue, 17 Feb 2026 17:30:03 +0800
Chen-Yu Tsai <[email protected]> wrote:

Hi,

Quoted 4 lines

When the PRCM clk driver was added, somehow the r-spi module clock was skipped over.

Add it so that r-spi can actually work.

The patch itself looks fine, compared against the manual, so for that:

Reviewed-by Andre Przywara <[email protected]>

But I noticed one thing below....

Quoted 11 lines
Fixes 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Signed-off-by Chen-Yu Tsai <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +0 -0
index 0339c4af0fe5..db0e36d8838e 100644

drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", · line 86

Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +0 -1
@@ -83,9 +83,22 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
 static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
                       &r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
 
-/* SPI clock is /M/N (same as new MMC?) */

Ooops, looks like I saw that clock, but someone managed to dodge it :-( Sorry about that.

drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", · line 91

Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +6 -0
+static const struct clk_parent_data r_spi_parents[] = {
+     { .fw_name = "hosc" },
+     { .fw_name = "pll-periph" },
+     { .name = "pll-periph0-300M" },
+     { .name = "pll-periph1-300M" },
+     { .name = "pll-audio" },
Quoted 2 lines

Looking a bit closer, all the PRCM PLL-AUDIO clocks in the manual refer to AUDIO1PLL4X, which is provided by the MCU CCU, not AUDIO0PLL4X provided by

That's weird though, given that pll-audio1 only has /2 and /5 outputs.

The BSP code from https://github.com/radxa/allwinner-bsp.git also shows pll-audio0-4x as the parent for the r_spi module clock. It does show pll-audio1-4x as the parent for the ahbs clock, but "pll-audio1-4x" is nowhere to be found.

So I think it's an error. Moreover, I think we might have discussed this on IRC at the time?

Quoted 2 lines

the main CCU. So we would need to change the DT? I wonder if that breaks boots with kernels which didn't know the MCU CCU yet (v6.15-v6.17)?

Did you mean new DT with old kernel? I think we don't really support that?

But even if you did do that, AFAIK the clk parent resolution is done opportunistically, so if this one is missing, it would be fine as long as no user is directly trying to select it with clk_set_parent(); and even if they did, it would probably fail?

I could be wrong though.

Anyway, thanks for being thorough.

ChenYu

Quoted 34 lines

Cheers,
Andre.

Quoted 29 lines
drivers/clk/sunxi-ng/ccu-sun55i-a523-r.c +10 -0
+};
+static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150,
+                               0, 5,         /* M */
+                               8, 5,         /* P */
+                               24, 3,        /* mux */
+                               BIT(31),      /* gate */
+                               0);
 static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
                       &r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
+
 static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
                       &r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
 static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",

@@ -138,6 +151,7 @@ static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
      &bus_r_twd_clk.common,
      &r_pwmctrl_clk.common,
      &bus_r_pwmctrl_clk.common,
+     &r_spi_clk.common,
      &bus_r_spi_clk.common,
      &bus_r_spinlock_clk.common,
      &bus_r_msgbox_clk.common,

@@ -169,6 +183,7 @@ static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
              [CLK_BUS_R_TWD]         = &bus_r_twd_clk.common.hw,
              [CLK_R_PWMCTRL]         = &r_pwmctrl_clk.common.hw,
              [CLK_BUS_R_PWMCTRL]     = &bus_r_pwmctrl_clk.common.hw,
+             [CLK_R_SPI]             = &r_spi_clk.common.hw,
              [CLK_BUS_R_SPI]         = &bus_r_spi_clk.common.hw,
              [CLK_BUS_R_SPINLOCK]    = &bus_r_spinlock_clk.common.hw,
              [CLK_BUS_R_MSGBOX]      = &bus_r_msgbox_clk.common.hw,
author maintainer
#4 lore raw
In reply to Chen-Yu Tsai
Quoted 6 lines · Chen-Yu Tsai

When the PRCM clk driver was added, somehow the r-spi module clock was skipped over.

Add it so that r-spi can actually work.

Applied to sunxi/clk-for-7.1 in local tree, thanks!

[1/1] clk: sunxi-ng: sun55i-a523-r: Add missing r-spi module clock

      commit: fb20ccf70cf695f178d7c32e2d33b376560df0ff

Best regards,

Signature · 1 line
Chen-Yu Tsai <[email protected]>