Add DSI display support for SC8280XP
Subsystems (6)
cover Add DSI display support for SC8280XP
Add DSI display support for SC8280XP.
Pengyu Luo (4):
dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
dt-bindings: display: msm: Document DSI controller and DSI PHY on
SC8280XP
drm/msm/dsi: Add DSI PHY configuration on SC8280XP
arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
.../display/msm/dsi-controller-main.yaml | 2 + .../bindings/display/msm/dsi-phy-7nm.yaml | 1 + .../display/msm/qcom,sc8280xp-mdss.yaml | 30 ++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 425 +++++++++++++++++- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + 5 files changed, 452 insertions(+), 8 deletions(-)
Signature · 1 line
2.53.0
PATCH 1/5 dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Document DSI PHY on SC8280XP Platform.
--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1 -0
@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nm - qcom,sm6375-dsi-phy-7nm - qcom,sm8350-dsi-phy-5nm - qcom,sm8450-dsi-phy-5nm
Signature · 1 line
2.53.0
Re: [PATCH 1/5] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Quoted 12 lines · Pengyu Luo
Document DSI PHY on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +0
-0
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml properties: · line 26
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1
-0@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nm
Your other commit claims it is compatible with sa8775p, just like some other devices here.
Best regards,
Krzysztof
Re: [PATCH 1/5] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Quoted 8 lines · Krzysztof Kozlowski
Quoted 7 lines · Pengyu Luo
Document DSI PHY on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)
Quoted 12 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml properties: · line 26
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1
-0@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nmYour other commit claims it is compatible with sa8775p, just like some other devices here.
If that helps, they do have the same values for the REVISION_ID registers
Konrad
Re: [PATCH 1/5] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Quoted 23 lines · Konrad Dybcio
Quoted 8 lines · Krzysztof Kozlowski
Quoted 7 lines · Pengyu Luo
Document DSI PHY on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)Quoted 12 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml properties: · line 26
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1
-0@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nmYour other commit claims it is compatible with sa8775p, just like some other devices here.
Quoted 2 lines
If that helps, they do have the same values for the
REVISION_IDregisters
Thanks for confirming this,I will add this to the commit message and fallback to sa8775 then.
I am curious, do the PHY QUIRKs in dsi_phy_7nm.c reflect PHY revision? I notice
REG_DSI_7nm_PHY_CMN_REVISION_ID0 QUIRK
SM8250: 0x00000014 4.1 SM8650: 0x00000025 5.2 SC8280XP: 0x00000024 4.2 SM8750: 0x00000027 7.0(*)
(*) SM8750 is 7.2 in the downstream.
Best wishes,
Pengyu
Re: [PATCH 1/5] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Quoted 25 lines · Pengyu Luo
Quoted 23 lines · Konrad Dybcio
Quoted 20 lines · Krzysztof Kozlowski
Quoted 12 lines · Pengyu Luo
Document DSI PHY on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +0
-0Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml properties: · line 26
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1
-0@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nmYour other commit claims it is compatible with sa8775p, just like some other devices here.
Quoted 7 lines
Quoted 2 lines
If that helps, they do have the same values for the
REVISION_IDregistersThanks for confirming this,I will add this to the commit message and fallback to sa8775 then.
I am curious, do the PHY QUIRKs in
dsi_phy_7nm.creflect PHY revision?
Yes
Quoted 8 lines
I notice
REG_DSI_7nm_PHY_CMN_REVISION_ID0QUIRKSM8250: 0x00000014 4.1 SM8650: 0x00000025 5.2 SC8280XP: 0x00000024 4.2 SM8750: 0x00000027 7.0(*)(*) SM8750 is 7.2 in the downstream.
Please change SM8750 to 7.2 (and SM8150 to 4.0 FWIW).
Quoted 3 lines
Best wishes,
Pengyu
Signature · 2 lines
With best wishes Dmitry
Re: [PATCH 1/5] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
Quoted 44 lines · Dmitry Baryshkov
Quoted 25 lines · Pengyu Luo
Quoted 23 lines · Konrad Dybcio
Quoted 20 lines · Krzysztof Kozlowski
Quoted 12 lines · Pengyu Luo
Document DSI PHY on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +0
-0Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml properties: · line 26
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +1
-0@@ -23,6 +23,7 @@ properties: - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm + - qcom,sc8280xp-dsi-phy-5nmYour other commit claims it is compatible with sa8775p, just like some other devices here.
Quoted 7 lines
Quoted 2 lines
If that helps, they do have the same values for the
REVISION_IDregistersThanks for confirming this,I will add this to the commit message and fallback to sa8775 then.
I am curious, do the PHY QUIRKs in
dsi_phy_7nm.creflect PHY revision?Yes
Quoted 7 lines
I notice
REG_DSI_7nm_PHY_CMN_REVISION_ID0QUIRKSM8250: 0x00000014 4.1 SM8650: 0x00000025 5.2 SC8280XP: 0x00000024 4.2 SM8750: 0x00000027 7.0(*)
Quoted 4 lines
Quoted 1 line
(*) SM8750 is 7.2 in the downstream.
Please change SM8750 to 7.2 (and SM8150 to 4.0 FWIW).
ACK.
It is exactly 4.0.
https://github.com/OnePlusOSS/android_kernel_oneplus_sm8150/blob/oneplus/SM8150_P_9.0/arch/arm64/boot/dts/qcom/sm8150-sde.dtsi#L518
Best wishes,
Pengyu
PATCH 2/5 dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
In reply to Pengyu LuoDocument DSI controller on SC8280XP Platform.
--- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +2 -0
@@ -29,6 +29,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sc8180x-dsi-ctrl + - qcom,sc8280xp-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl
@@ -340,6 +341,7 @@ allOf: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sc8180x-dsi-ctrl + - qcom,sc8280xp-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl
Signature · 1 line
2.53.0
Re: [PATCH 2/5] dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
Quoted 12 lines · Pengyu Luo
Document DSI controller on SC8280XP Platform.
Signed-off-by Pengyu Luo <[email protected]>--- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +0
-0
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml properties: · line 32
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +1
-0@@ -29,6 +29,7 @@ properties: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sc8180x-dsi-ctrl + - qcom,sc8280xp-dsi-ctrl
The revision registers match for this and 8775 too
The latter seems to have a very slight difference in a single register though.
Konrad
PATCH 3/5 dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP
In reply to Pengyu LuoDocument DSI controller and DSI phy on SC8280XP platform.
--- .../display/msm/qcom,sc8280xp-mdss.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+)
Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml +30 -0
@@ -50,6 +50,22 @@ patternProperties: - qcom,sc8280xp-dp - qcom,sc8280xp-edp + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sc8280xp-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sc8280xp-dsi-phy-5nm + unevaluatedProperties: false examples:
@@ -129,6 +145,20 @@ examples: }; }; + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; + port@4 { reg = <4>; endpoint {
Signature · 1 line
2.53.0
PATCH 4/5 drm/msm/dsi: Add DSI PHY configuration on SC8280XP
In reply to Pengyu LuoAccording to the REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL value(0x3c) on Windows OS, we can confirm that the SC8280XP uses the 5nm (v4.2) DSI PHY.
Since SC8280XP and SA8775P have the same DSI version (v2.5.1), using SA8775P configuration.
--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +2 -0
@@ -565,6 +565,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_5nm_sar2130p_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,sc8280xp-dsi-phy-5nm", + .data = &dsi_phy_5nm_8775p_cfgs }, { .compatible = "qcom,sm6375-dsi-phy-7nm", .data = &dsi_phy_7nm_6375_cfgs }, { .compatible = "qcom,sm8350-dsi-phy-5nm",
Signature · 1 line
2.53.0
Re: [PATCH 4/5] drm/msm/dsi: Add DSI PHY configuration on SC8280XP
Quoted 6 lines · Pengyu Luo
According to the
REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRLvalue(0x3c) on Windows OS, we can confirm that the SC8280XP uses the 5nm (v4.2) DSI PHY.Since SC8280XP and SA8775P have the same DSI version (v2.5.1), using SA8775P configuration.
Then we should not need separate config here. Use sa8775p as a fallback compatible.
Quoted 22 lines
Signed-off-by Pengyu Luo <[email protected]>--- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ 1 file changed, 2 insertions(+)drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +2
-0@@ -565,6 +565,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_5nm_sar2130p_cfgs }, { .compatible = "qcom,sc7280-dsi-phy-7nm", .data = &dsi_phy_7nm_7280_cfgs }, + { .compatible = "qcom,sc8280xp-dsi-phy-5nm", + .data = &dsi_phy_5nm_8775p_cfgs }, { .compatible = "qcom,sm6375-dsi-phy-7nm", .data = &dsi_phy_7nm_6375_cfgs }, { .compatible = "qcom,sm8350-dsi-phy-5nm",Signature · 1 line
2.53.0
Signature · 2 lines
With best wishes Dmitry
PATCH 1/1 arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
In reply to Pengyu LuoThe DT configuration follows other Samsung 5nm-based Qualcomm SOCs, utilizing the same register layouts and clock structures.
However, DSI won't work properly for now (Partial content wrapped to the left side) until we submit dispcc fixes. And some panels require DPU timing calculation fixes too. (hdisplay / width timing round errors cause the fifo error)
--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 423 ++++++++++++++++++++++++- 1 file changed, 415 insertions(+), 8 deletions(-)
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +415 -8
@@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> #include <dt-bindings/clock/qcom,rpmh.h>
@@ -4657,6 +4658,20 @@ mdss0_intf0_out: endpoint { }; }; + port@1 { + reg = <1>; + mdss0_intf1_out: endpoint { + remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + mdss0_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; + port@4 { reg = <4>; mdss0_intf4_out: endpoint {
@@ -4791,6 +4806,195 @@ opp-810000000 { }; }; + mdss0_dsi0: dsi@ae94000 { + compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss0>; + interrupts = <4>; + + clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss0_dsi0_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + phy-names = "dsi"; + + phys = <&mdss0_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi0_in: endpoint { + remote-endpoint = <&mdss0_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi0_out: endpoint { + }; + }; + }; + + mdss0_dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss0_dsi1: dsi@ae96000 { + compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss0>; + interrupts = <5>; + + clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss0_dsi1_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + phys = <&mdss0_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi1_in: endpoint { + remote-endpoint = <&mdss0_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi1_out: endpoint { + }; + }; + }; + + mdss0_dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + mdss0_dp1: displayport-controller@ae98000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae98000 0 0x200>,
@@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 { <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>;
@@ -6008,6 +6212,20 @@ mdss1_intf0_out: endpoint { }; }; + port@1 { + reg = <1>; + mdss1_intf1_out: endpoint { + remote-endpoint = <&mdss1_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + mdss1_intf2_out: endpoint { + remote-endpoint = <&mdss1_dsi1_in>; + }; + }; + port@4 { reg = <4>; mdss1_intf4_out: endpoint {
@@ -6139,6 +6357,195 @@ opp-810000000 { }; }; + mdss1_dsi0: dsi@22094000 { + compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x22094000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss1>; + interrupts = <4>; + + clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss1_dsi0_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + phy-names = "dsi"; + + phys = <&mdss1_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dsi0_in: endpoint { + remote-endpoint = <&mdss1_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss1_dsi0_out: endpoint { + }; + }; + }; + + mdss1_dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss1_dsi0_phy: phy@22094400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm"; + reg = <0 0x22094400 0 0x200>, + <0 0x22094600 0 0x280>, + <0 0x22094900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss1_dsi1: dsi@22096000 { + compatible = "qcom,sc8280xp-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x22096000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss1>; + interrupts = <5>; + + clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss1_dsi1_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + phys = <&mdss1_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dsi1_in: endpoint { + remote-endpoint = <&mdss1_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss1_dsi1_out: endpoint { + }; + }; + }; + + mdss1_dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss1_dsi1_phy: phy@22096400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm"; + reg = <0 0x22096400 0 0x200>, + <0 0x22096600 0 0x280>, + <0 0x22096900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + mdss1_dp1: displayport-controller@22098000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x22098000 0 0x200>,
@@ -6426,10 +6833,10 @@ dispcc1: clock-controller@22100000 { <&mdss1_dp2_phy 1>, <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>;
Signature · 1 line
2.53.0
Re: [PATCH] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
Quoted 13 lines · Pengyu Luo
The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, utilizing the same register layouts and clock structures.
However, DSI won't work properly for now (Partial content wrapped to the left side) until we submit dispcc fixes. And some panels require DPU timing calculation fixes too. (hdisplay / width timing round errors cause the fifo error)
Co-developed-by Tianyu Gao <[email protected]>Signed-off-by Tianyu Gao <[email protected]>Signed-off-by Pengyu Luo <[email protected]>---
[...]
arch/arm64/boot/dts/qcom/sc8280xp.dtsi mdss0_intf0_out: endpoint { · line 4663
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +3
-0+ port@1 { + reg = <1>; + mdss0_intf1_out: endpoint {
style: it's preferable to keep a new line between the last property and the following subnode, i.e.:
port@1 {
reg = <1>;
mdss0_intf1_out: endpoint {
...
}Quoted 15 lines
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +11
-0+ remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + mdss0_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; + port@4 { reg = <4>; mdss0_intf4_out: endpoint {@@ -4791,6 +4806,195 @@ opp-810000000 {
[...]
arch/arm64/boot/dts/qcom/sc8280xp.dtsi opp-810000000 { · line 4840
Quoted 3 lines
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +3
-0+ phy-names = "dsi"; + + phys = <&mdss0_dsi0_phy>;
property
property-names
in this order, please
[...]
arch/arm64/boot/dts/qcom/sc8280xp.dtsi opp-810000000 { · line 4889
Quoted 5 lines
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +5
-0+ mdss0_dsi0_phy: phy@ae94400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>;
last entry: size=0x280, all instances, there's actually a register at +0x27c
[...]
arch/arm64/boot/dts/qcom/sc8280xp.dtsi opp-810000000 { · line 4959
Quoted 1 line
arch/arm64/boot/dts/qcom/sc8280xp.dtsi +1
-0+ mdss0_dsi1_opp_table: opp-table {
You can reference the prior OPP table (and just call it dsi_opp_table) since they're identical
Konrad
Re: [PATCH] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
In reply to Pengyu LuoQuoted 7 lines · Pengyu Luo
The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, utilizing the same register layouts and clock structures.
However, DSI won't work properly for now (Partial content wrapped to the left side) until we submit dispcc fixes. And some panels require DPU timing calculation fixes too. (hdisplay / width timing round errors cause the fifo error)
I'm looking forward to reviewing those patches!
Quoted 1 line
Signature · 2 lines
With best wishes Dmitry