KVM: arm64: Fix SPE and TRBE nVHE world switch
Will Deacon
maintainerv2 cover KVM: arm64: Fix SPE and TRBE nVHE world switch
Hi folks,
This is version two of the patch that I originally sent here:
https://lore.kernel.org/r/[email protected]
Changes since v1 include:
* Add missing memory barriers and comments for each step
* Work around known CPU errata in TRBE draining / enabling sequences
* Fix SPE as well!
* Minor clean up to BRBE so that it smells the same as SPE and TRBE
As before, I've not been able to test this as-is.
Cheers,
Will
--->8
Will Deacon (3):
KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest
context
KVM: arm64: Disable SPE Profiling Buffer when running in guest context
KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines
arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 118 +++++++++++++++++++++++------ arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 96 insertions(+), 26 deletions(-)
Signature · 1 line
2.53.0.473.g4a7958ca14-goog
Will Deacon
maintainerPATCH v2 1/3 KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
The nVHE world-switch code relies on zeroing TRFCR_EL1 to disable trace generation in guest context when self-hosted TRBE is in use by the host.
Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing TRFCR_EL1 means that trace generation is prohibited at EL1 and EL0 but per R_YCHKJ the Trace Buffer Unit will still be enabled if TRBLIMITR_EL1.E is set. R_SJFRQ goes on to state that, when enabled, the Trace Buffer Unit can perform address translation for the "owning exception level" even when it is out of context.
Consequently, we can end up in a state where TRBE performs speculative page-table walks for a host VA/IPA in guest/hypervisor context depending on the value of MDCR_EL2.E2TB, which changes over world-switch. The potential result appears to be a heady mixture of SErrors, data corruption and hardware lockups.
Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after draining the buffer, restoring the register on return to the host. This unfortunately means we need to tackle CPU errata #2064142 and #2038923 which add additional synchronisation requirements around manipulations of the limit register. Hopefully this doesn't need to be fast.
--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 73 ++++++++++++++++++++++++++---- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 66 insertions(+), 10 deletions(-)
arch/arm64/include/asm/kvm_host.h +1 -0
@@ -770,6 +770,7 @@ struct kvm_host_data {u64 pmscr_el1;/* Self-hosted trace */ u64 trfcr_el1; +u64 trblimitr_el1;/* Values of trap registers for the host before guest entry. */ u64 mdcr_el2;u64 brbcr_el1;
arch/arm64/kvm/hyp/nvhe/debug-sr.c +64 -9
91 lines not on this page · raw message
arch/arm64/kvm/hyp/nvhe/switch.c +1 -1
@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE, SPE and TRBE. +* above disabling of BRBE and SPE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements.
Signature · 1 line
2.53.0.473.g4a7958ca14-goog
Re: [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
Quoted 22 lines · Will Deacon
The nVHE world-switch code relies on zeroing
TRFCR_EL1to disable trace generation in guest context when self-hosted TRBE is in use by the host.Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing
TRFCR_EL1means that trace generation is prohibited at EL1 and EL0 but perR_YCHKJthe Trace Buffer Unit will still be enabled if TRBLIMITR_EL1.E is set.R_SJFRQgoes on to state that, when enabled, the Trace Buffer Unit can perform address translation for the "owning exception level" even when it is out of context.Consequently, we can end up in a state where TRBE performs speculative page-table walks for a host VA/IPA in guest/hypervisor context depending on the value of MDCR_EL2.E2TB, which changes over world-switch. The potential result appears to be a heady mixture of SErrors, data corruption and hardware lockups.
Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after draining the buffer, restoring the register on return to the host. This unfortunately means we need to tackle CPU errata #2064142 and #2038923 which add additional synchronisation requirements around manipulations of the limit register. Hopefully this doesn't need to be fast.
Quoted 9 lines
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host")Signed-off-by Will Deacon <[email protected]>
Thanks for fixing this. Looks correct to me,
Quoted 128 lines
--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 73 ++++++++++++++++++++++++++---- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 66 insertions(+), 10 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -770,6 +770,7 @@ struct kvm_host_data {u64 pmscr_el1;/* Self-hosted trace */ u64 trfcr_el1; +u64 trblimitr_el1;/* Values of trap registers for the host before guest entry. */ u64 mdcr_el2;u64 brbcr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +64
-9@@ -57,12 +57,56 @@ static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr)write_sysreg_el1 (new_trfcr,SYS_TRFCR ); } -static bool __trace_needs_drain (void ) +static void __trace_drain_and_disable (void ) { -if (is_protected_kvm_enabled () &&host_data_test_flag (HAS_TRBE )) -return read_sysreg_s (SYS_TRBLIMITR_EL1 ) &TRBLIMITR_EL1_E ; +u64 *trblimitr_el1 =host_data_ptr (host_debug_state.trblimitr_el1); -return host_data_test_flag (TRBE_ENABLED ); + *trblimitr_el1 =0 ; + +if (is_protected_kvm_enabled ()) { +if (!host_data_test_flag (HAS_TRBE )) +return ; + }else { +if (!host_data_test_flag (TRBE_ENABLED )) +return ; + } + + *trblimitr_el1 =read_sysreg_s (SYS_TRBLIMITR_EL1 ); +if (*trblimitr_el1 &TRBLIMITR_EL1_E ) { +/* +* The host has enabled the Trace Buffer Unit so we have +* to beat the CPU with a stick until it stops accessing +* memory. +*/ + +/* First, ensure that our prior write to TRFCR has stuck. */ +isb (); + +/* Now synchronise with the trace and drain the buffer. */ +tsb_csync (); +dsb (nsh); + +/* +* With no more trace being generated, we can disable the +* Trace Buffer Unit. +*/ +write_sysreg_s (0 ,SYS_TRBLIMITR_EL1 ); +if (cpus_have_final_cap (ARM64_WORKAROUND_2064142 )) { +/* +* Some CPUs are so good, we have to drain 'em +* twice. +*/ +tsb_csync (); +dsb (nsh); + } + +/* +* Ensure that the Trace Buffer Unit is disabled before +* we start mucking with the stage-2 and trap +* configuration. +*/ +isb (); + } }static bool __trace_needs_switch (void )@@ -79,15 +123,26 @@ static void __trace_switch_to_guest(void)__trace_do_switch (host_data_ptr (host_debug_state.trfcr_el1), *host_data_ptr (trfcr_while_in_guest)); - -if (__trace_needs_drain ()) { -isb (); -tsb_csync (); - } +__trace_drain_and_disable (); }static void __trace_switch_to_host (void ) { +u64 trblimitr_el1 = *host_data_ptr (host_debug_state.trblimitr_el1); + +if (trblimitr_el1 &TRBLIMITR_EL1_E ) { +/* Re-enable the Trace Buffer Unit for the host. */ +write_sysreg_s (trblimitr_el1,SYS_TRBLIMITR_EL1 ); +isb (); +if (cpus_have_final_cap (ARM64_WORKAROUND_2038923 )) { +/* +* Make sure the unit is re-enabled before we +* poke TRFCR. +*/ +isb (); + } + } +__trace_do_switch (host_data_ptr (trfcr_while_in_guest), *host_data_ptr (host_debug_state.trfcr_el1)); }arch/arm64/kvm/hyp/nvhe/switch.c +1
-1@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE, SPE and TRBE. +* above disabling of BRBE and SPE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements.
Re: [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
In reply to Will DeaconQuoted 22 lines · Will Deacon
The nVHE world-switch code relies on zeroing
TRFCR_EL1to disable trace generation in guest context when self-hosted TRBE is in use by the host.Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing
TRFCR_EL1means that trace generation is prohibited at EL1 and EL0 but perR_YCHKJthe Trace Buffer Unit will still be enabled if TRBLIMITR_EL1.E is set.R_SJFRQgoes on to state that, when enabled, the Trace Buffer Unit can perform address translation for the "owning exception level" even when it is out of context.Consequently, we can end up in a state where TRBE performs speculative page-table walks for a host VA/IPA in guest/hypervisor context depending on the value of MDCR_EL2.E2TB, which changes over world-switch. The potential result appears to be a heady mixture of SErrors, data corruption and hardware lockups.
Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after draining the buffer, restoring the register on return to the host. This unfortunately means we need to tackle CPU errata #2064142 and #2038923 which add additional synchronisation requirements around manipulations of the limit register. Hopefully this doesn't need to be fast.
Quoted 9 lines
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host")Signed-off-by Will Deacon <[email protected]>
I tested this on my Orion6 board in nVHE mode (kvm-arm.mode=nvhe).
I launched a VM with several threads running sleep 0.1 in a loop inside the VM shell. Then, I collected TRBE trace data on the host side:
$ perf record -e cs_etm// -a -- sleep 100 [ perf record: Woken up 74 times to write data ] Warning: Processed 4798137 events and lost 4 chunks!
Check IO/CPU overload!
Warning:
Processed 9608 samples and lost 100.00%!
Failed to open /proc/schedstat
[ perf record: Captured and wrote 42401.333 MB perf.data ]
Re: [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
In reply to Will DeaconHi Will,
Now that I have backported this to various Android versions....
Quoted 65 lines · Will Deacon
The nVHE world-switch code relies on zeroing
TRFCR_EL1to disable trace generation in guest context when self-hosted TRBE is in use by the host.Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing
TRFCR_EL1means that trace generation is prohibited at EL1 and EL0 but perR_YCHKJthe Trace Buffer Unit will still be enabled if TRBLIMITR_EL1.E is set.R_SJFRQgoes on to state that, when enabled, the Trace Buffer Unit can perform address translation for the "owning exception level" even when it is out of context.Consequently, we can end up in a state where TRBE performs speculative page-table walks for a host VA/IPA in guest/hypervisor context depending on the value of MDCR_EL2.E2TB, which changes over world-switch. The potential result appears to be a heady mixture of SErrors, data corruption and hardware lockups.
Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after draining the buffer, restoring the register on return to the host. This unfortunately means we need to tackle CPU errata #2064142 and #2038923 which add additional synchronisation requirements around manipulations of the limit register. Hopefully this doesn't need to be fast.
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host")Signed-off-by Will Deacon <[email protected]>--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 73 ++++++++++++++++++++++++++---- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 66 insertions(+), 10 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -770,6 +770,7 @@ struct kvm_host_data {u64 pmscr_el1;/* Self-hosted trace */ u64 trfcr_el1; +u64 trblimitr_el1;/* Values of trap registers for the host before guest entry. */ u64 mdcr_el2;u64 brbcr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +2
-3@@ -57,12 +57,56 @@ static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr)write_sysreg_el1 (new_trfcr,SYS_TRFCR ); } -static bool __trace_needs_drain (void ) +static void __trace_drain_and_disable (void ) { -if (is_protected_kvm_enabled () &&host_data_test_flag (HAS_TRBE )) -return read_sysreg_s (SYS_TRBLIMITR_EL1 ) &TRBLIMITR_EL1_E ; +u64 *trblimitr_el1 =host_data_ptr (host_debug_state.trblimitr_el1);
arch/arm64/kvm/hyp/nvhe/debug-sr.c static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr) · line 72
Quoted 10 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +9
-1-return host_data_test_flag (TRBE_ENABLED ); + *trblimitr_el1 =0 ; + +if (is_protected_kvm_enabled ()) { +if (!host_data_test_flag (HAS_TRBE )) +return ; + }else { +if (!host_data_test_flag (TRBE_ENABLED )) +return ; + }
Can we simplify this? e.g.,
+ bool needs_drain = is_protected_kvm_enabled() ?host_data_test_flag(HAS_TRBE) : host_data_test_flag(TRBE_ENABLED);
....
That said:
Cheers,
/fuad
Quoted 88 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +53
-5+ + *trblimitr_el1 =read_sysreg_s (SYS_TRBLIMITR_EL1 ); +if (*trblimitr_el1 &TRBLIMITR_EL1_E ) { +/* +* The host has enabled the Trace Buffer Unit so we have +* to beat the CPU with a stick until it stops accessing +* memory. +*/ + +/* First, ensure that our prior write to TRFCR has stuck. */ +isb (); + +/* Now synchronise with the trace and drain the buffer. */ +tsb_csync (); +dsb (nsh); + +/* +* With no more trace being generated, we can disable the +* Trace Buffer Unit. +*/ +write_sysreg_s (0 ,SYS_TRBLIMITR_EL1 ); +if (cpus_have_final_cap (ARM64_WORKAROUND_2064142 )) { +/* +* Some CPUs are so good, we have to drain 'em +* twice. +*/ +tsb_csync (); +dsb (nsh); + } + +/* +* Ensure that the Trace Buffer Unit is disabled before +* we start mucking with the stage-2 and trap +* configuration. +*/ +isb (); + } }static bool __trace_needs_switch (void )@@ -79,15 +123,26 @@ static void __trace_switch_to_guest(void)__trace_do_switch (host_data_ptr (host_debug_state.trfcr_el1), *host_data_ptr (trfcr_while_in_guest)); - -if (__trace_needs_drain ()) { -isb (); -tsb_csync (); - } +__trace_drain_and_disable (); }static void __trace_switch_to_host (void ) { +u64 trblimitr_el1 = *host_data_ptr (host_debug_state.trblimitr_el1); + +if (trblimitr_el1 &TRBLIMITR_EL1_E ) { +/* Re-enable the Trace Buffer Unit for the host. */ +write_sysreg_s (trblimitr_el1,SYS_TRBLIMITR_EL1 ); +isb (); +if (cpus_have_final_cap (ARM64_WORKAROUND_2038923 )) { +/* +* Make sure the unit is re-enabled before we +* poke TRFCR. +*/ +isb (); + } + } +__trace_do_switch (host_data_ptr (trfcr_while_in_guest), *host_data_ptr (host_debug_state.trfcr_el1)); }arch/arm64/kvm/hyp/nvhe/switch.c +1
-2@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE, SPE and TRBE. +* above disabling of BRBE and SPE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements. -- 2.53.0.473.g4a7958ca14-goog
Will Deacon
maintainerRe: [PATCH v2 1/3] KVM: arm64: Disable TRBE Trace Buffer Unit when running in guest context
Quoted 79 lines · Fuad Tabba
Quoted 65 lines · Will Deacon
The nVHE world-switch code relies on zeroing
TRFCR_EL1to disable trace generation in guest context when self-hosted TRBE is in use by the host.Per D3.2.1 ("Controls to prohibit trace at Exception levels"), clearing
TRFCR_EL1means that trace generation is prohibited at EL1 and EL0 but perR_YCHKJthe Trace Buffer Unit will still be enabled if TRBLIMITR_EL1.E is set.R_SJFRQgoes on to state that, when enabled, the Trace Buffer Unit can perform address translation for the "owning exception level" even when it is out of context.Consequently, we can end up in a state where TRBE performs speculative page-table walks for a host VA/IPA in guest/hypervisor context depending on the value of MDCR_EL2.E2TB, which changes over world-switch. The potential result appears to be a heady mixture of SErrors, data corruption and hardware lockups.
Extend the TRBE world-switch code to clear TRBLIMITR_EL1.E after draining the buffer, restoring the register on return to the host. This unfortunately means we need to tackle CPU errata #2064142 and #2038923 which add additional synchronisation requirements around manipulations of the limit register. Hopefully this doesn't need to be fast.
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes a1319260bf62 ("arm64: KVM: Enable access to TRBE support for host")Signed-off-by Will Deacon <[email protected]>--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 73 ++++++++++++++++++++++++++---- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 66 insertions(+), 10 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -770,6 +770,7 @@ struct kvm_host_data {u64 pmscr_el1;/* Self-hosted trace */ u64 trfcr_el1; +u64 trblimitr_el1;/* Values of trap registers for the host before guest entry. */ u64 mdcr_el2;u64 brbcr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +2
-3@@ -57,12 +57,56 @@ static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr)write_sysreg_el1 (new_trfcr,SYS_TRFCR ); } -static bool __trace_needs_drain (void ) +static void __trace_drain_and_disable (void ) { -if (is_protected_kvm_enabled () &&host_data_test_flag (HAS_TRBE )) -return read_sysreg_s (SYS_TRBLIMITR_EL1 ) &TRBLIMITR_EL1_E ; +u64 *trblimitr_el1 =host_data_ptr (host_debug_state.trblimitr_el1);arch/arm64/kvm/hyp/nvhe/debug-sr.c static void __trace_do_switch(u64 *saved_trfcr, u64 new_trfcr) · line 72
Quoted 10 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +9
-1-return host_data_test_flag (TRBE_ENABLED ); + *trblimitr_el1 =0 ; + +if (is_protected_kvm_enabled ()) { +if (!host_data_test_flag (HAS_TRBE )) +return ; + }else { +if (!host_data_test_flag (TRBE_ENABLED )) +return ; + }Can we simplify this? e.g.,
Quoted 3 lines
+ bool
needs_drain=is_protected_kvm_enabled()?host_data_test_flag(HAS_TRBE):host_data_test_flag(TRBE_ENABLED);
....
Good idea. I tend to avoid 'bool's as they often make the code less readable in my experience, but in this case it would be a lot better than the nested conditionals I have. I'll spin a v3!
Quoted 4 lines
That said:
Tested-by Fuad Tabba <[email protected]>Reviewed-by Fuad Tabba <[email protected]>
Cheers,
Will
Will Deacon
maintainerPATCH v2 2/3 KVM: arm64: Disable SPE Profiling Buffer when running in guest context
In reply to Will DeaconThe nVHE world-switch code relies on zeroing PMSCR_EL1 to disable profiling data generation in guest context when SPE is in use by the host.
Unfortunately, this may leave PMBLIMITR_EL1.E set and consequently we can end up running in guest/hypervisor context with the Profiling Buffer enabled. The current "known issues" document for Rev M.a of the Arm ARM states that this can lead to speculative, out-of-context translations:
| 2.18 D23136: | | When the Profiling Buffer is enabled, profiling is not stopped, and | Discard mode is not enabled, the Statistical Profiling Unit might | cause speculative translations for the owning translation regime, | including when the owning translation regime is out-of-context.
In a similar fashion to TRBE, ensure that the Profiling Buffer is disabled during the nVHE world switch before we start messing with the stage-2 MMU and trap configuration.
--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 33 ++++++++++++++++++++---------- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 24 insertions(+), 12 deletions(-)
arch/arm64/include/asm/kvm_host.h +1 -0
@@ -768,6 +768,7 @@ struct kvm_host_data {struct kvm_guest_debug_arch regs;/* Statistical profiling extension */ u64 pmscr_el1; +u64 pmblimitr_el1;/* Self-hosted trace */ u64 trfcr_el1;u64 trblimitr_el1;
arch/arm64/kvm/hyp/nvhe/debug-sr.c +22 -11
@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */
@@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void ) { -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* The host page table is installed, but not yet synchronised */ isb (); +/* Re-enable the profiling buffer. */ +write_sysreg_s (pmblimitr_el1,SYS_PMBLIMITR_EL1 ); +isb (); +/* Re-enable data generation */ -write_sysreg_el1 (pmscr_el1,SYS_PMSCR ); +write_sysreg_el1 (*host_data_ptr (host_debug_state.pmscr_el1),SYS_PMSCR ); }static void __trace_do_switch (u64 *saved_trfcr,u64 new_trfcr)
@@ -177,7 +188,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) {/* Disable and flush SPE data generation */ if (host_data_test_flag (HAS_SPE )) -__debug_save_spe (host_data_ptr (host_debug_state.pmscr_el1)); +__debug_save_spe ();/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE ))
@@ -195,7 +206,7 @@ void __debug_switch_to_guest(struct kvm_vcpu *vcpu)void __debug_restore_host_buffers_nvhe (struct kvm_vcpu *vcpu) {if (host_data_test_flag (HAS_SPE )) -__debug_restore_spe (*host_data_ptr (host_debug_state.pmscr_el1)); +__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE ))__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1));if (__trace_needs_switch ())
arch/arm64/kvm/hyp/nvhe/switch.c +1 -1
@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE and SPE. +* above disabling of BRBE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements.
Signature · 1 line
2.53.0.473.g4a7958ca14-goog
Suzuki K Poulose
reviewerRe: [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
Quoted 91 lines · Will Deacon
The nVHE world-switch code relies on zeroing
PMSCR_EL1to disable profiling data generation in guest context when SPE is in use by the host.Unfortunately, this may leave PMBLIMITR_EL1.E set and consequently we can end up running in guest/hypervisor context with the Profiling Buffer enabled. The current "known issues" document for Rev M.a of the Arm ARM states that this can lead to speculative, out-of-context translations:
| 2.18 D23136: | | When the Profiling Buffer is enabled, profiling is not stopped, and | Discard mode is not enabled, the Statistical Profiling Unit might | cause speculative translations for the owning translation regime, | including when the owning translation regime is out-of-context.In a similar fashion to TRBE, ensure that the Profiling Buffer is disabled during the nVHE world switch before we start messing with the stage-2 MMU and trap configuration.
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes f85279b4bd48 ("arm64: KVM: Save/restore the host SPE state when entering/leaving a VM")Signed-off-by Will Deacon <[email protected]>--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 33 ++++++++++++++++++++---------- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 24 insertions(+), 12 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -768,6 +768,7 @@ struct kvm_host_data {struct kvm_guest_debug_arch regs;/* Statistical profiling extension */ u64 pmscr_el1; +u64 pmblimitr_el1;/* Self-hosted trace */ u64 trfcr_el1;u64 trblimitr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +12
-7@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */ @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void )
arch/arm64/kvm/hyp/nvhe/debug-sr.c static void __debug_save_spe(u64 *pmscr_el1) · line 56
Quoted 10 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +3
-1{ -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* The host page table is installed, but not yet synchronised */ isb ();
minor nit: This seems buried deep down in a helper (with no context of what else could have happened since the host context has been restored) and for now it looks correct, but is prone to inadvertent changes
causing issues or making this obsolete. With the isb() following LIMITR, wouldn't that be sufficient ?
Otherwise, looks good to me
Suzuki
Quoted 41 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +7
-3+/* Re-enable the profiling buffer. */ +write_sysreg_s (pmblimitr_el1,SYS_PMBLIMITR_EL1 ); +isb (); +/* Re-enable data generation */ -write_sysreg_el1 (pmscr_el1,SYS_PMSCR ); +write_sysreg_el1 (*host_data_ptr (host_debug_state.pmscr_el1),SYS_PMSCR ); }static void __trace_do_switch (u64 *saved_trfcr,u64 new_trfcr)@@ -177,7 +188,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) {/* Disable and flush SPE data generation */ if (host_data_test_flag (HAS_SPE )) -__debug_save_spe (host_data_ptr (host_debug_state.pmscr_el1)); +__debug_save_spe ();/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE ))@@ -195,7 +206,7 @@ void __debug_switch_to_guest(struct kvm_vcpu *vcpu)void __debug_restore_host_buffers_nvhe (struct kvm_vcpu *vcpu) {if (host_data_test_flag (HAS_SPE )) -__debug_restore_spe (*host_data_ptr (host_debug_state.pmscr_el1)); +__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE ))__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1));if (__trace_needs_switch ())arch/arm64/kvm/hyp/nvhe/switch.c +1
-1@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE and SPE. +* above disabling of BRBE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements.
Will Deacon
maintainerRe: [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
Quoted 45 lines · Suzuki K Poulose
Quoted 44 lines · Will Deacon
arch/arm64/kvm/hyp/nvhe/debug-sr.c +15
-8@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */ @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void ) { -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;
Quoted 8 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c static void __debug_save_spe(u64 *pmscr_el1) · line 55
Quoted 2 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +0
-0/* The host page table is installed, but not yet synchronised */ isb ();minor nit: This seems buried deep down in a helper (with no context of what else could have happened since the host context has been restored) and for now it looks correct, but is prone to inadvertent changes causing issues or making this obsolete. With the
isb()following LIMITR, wouldn't that be sufficient ?
I'm just inherting this from the existing upstream code -- see the isb() in the existing implementation of __debug_restore_spe().
The isb() is needed to ensure that SPE can't start making out-of-context translation table walks (which can occur once PMBLIMITR_EL1.E is set) before the stage-2 MMU is restored back to the host configuration (e.g. by clearing HCR_EL2.VM for nVHE or by restoring VTCR and VTTBR for pKVM). We want to predicate it on SPE being enabled, otherwise it's unconditional overhead, so I don't think we can move it.
Will
Suzuki K Poulose
reviewerRe: [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
Quoted 55 lines · Will Deacon
Quoted 45 lines · Suzuki K Poulose
Quoted 44 lines · Will Deacon
arch/arm64/kvm/hyp/nvhe/debug-sr.c +15
-8@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */ @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void ) { -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;Quoted 8 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c static void __debug_save_spe(u64 *pmscr_el1) · line 55
Quoted 2 lines
arch/arm64/kvm/hyp/nvhe/debug-sr.c +0
-0/* The host page table is installed, but not yet synchronised */ isb ();minor nit: This seems buried deep down in a helper (with no context of what else could have happened since the host context has been restored) and for now it looks correct, but is prone to inadvertent changes causing issues or making this obsolete. With the
isb()following LIMITR, wouldn't that be sufficient ?
Quoted 2 lines
I'm just inherting this from the existing upstream code -- see the
isb()in the existing implementation of__debug_restore_spe().
Of course, it was. I should have added "not from your change".
Now we have:
__kvm_vcpu_run () {
..guest_exit..
//load_host_stage2() if required -> pkvm.
__sysreg_restore_state_nvhe() -> __sysreg_restore_el1_state () #- we restore "host MMU context" here
...__debug_restore_host_buffers_nvhe() -> __debug_restore_spe(); #issue isb here to sync the host context
}
and the isb() is placed in the spe restore code. All of this is correct and I do understand why it is there. My comment was, this is not easily relatable and prone to errors with inadvertent changes (e.g., moving the spe around etc). But I agree that we can avoid the unconditional overhead over the code readability.
Cheers
Suzuki
Quoted 9 lines
The
isb()is needed to ensure that SPE can't start making out-of-context translation table walks (which can occur once PMBLIMITR_EL1.E is set) before the stage-2 MMU is restored back to the host configuration (e.g. by clearing HCR_EL2.VM for nVHE or by restoring VTCR and VTTBR for pKVM). We want to predicate it on SPE being enabled, otherwise it's unconditional overhead, so I don't think we can move it.Will
Re: [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
In reply to Will DeaconHi Will,
The patch looks good to me:
Also tested the series for about 24h on an Orion O6 board with SPE enabled by profiling two host processes spread across all CPUs with SPE, and at the same time profiling a virtual machine with the VCPUs simiarly spread across the CPUs with SPE:
Thanks,
Alex
Quoted 145 lines · Will Deacon
The nVHE world-switch code relies on zeroing
PMSCR_EL1to disable profiling data generation in guest context when SPE is in use by the host.Unfortunately, this may leave PMBLIMITR_EL1.E set and consequently we can end up running in guest/hypervisor context with the Profiling Buffer enabled. The current "known issues" document for Rev M.a of the Arm ARM states that this can lead to speculative, out-of-context translations:
| 2.18 D23136: | | When the Profiling Buffer is enabled, profiling is not stopped, and | Discard mode is not enabled, the Statistical Profiling Unit might | cause speculative translations for the owning translation regime, | including when the owning translation regime is out-of-context.In a similar fashion to TRBE, ensure that the Profiling Buffer is disabled during the nVHE world switch before we start messing with the stage-2 MMU and trap configuration.
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes f85279b4bd48 ("arm64: KVM: Save/restore the host SPE state when entering/leaving a VM")Signed-off-by Will Deacon <[email protected]>--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 33 ++++++++++++++++++++---------- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 24 insertions(+), 12 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -768,6 +768,7 @@ struct kvm_host_data {struct kvm_guest_debug_arch regs;/* Statistical profiling extension */ u64 pmscr_el1; +u64 pmblimitr_el1;/* Self-hosted trace */ u64 trfcr_el1;u64 trblimitr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +22
-11@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */ @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void ) { -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* The host page table is installed, but not yet synchronised */ isb (); +/* Re-enable the profiling buffer. */ +write_sysreg_s (pmblimitr_el1,SYS_PMBLIMITR_EL1 ); +isb (); +/* Re-enable data generation */ -write_sysreg_el1 (pmscr_el1,SYS_PMSCR ); +write_sysreg_el1 (*host_data_ptr (host_debug_state.pmscr_el1),SYS_PMSCR ); }static void __trace_do_switch (u64 *saved_trfcr,u64 new_trfcr)@@ -177,7 +188,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) {/* Disable and flush SPE data generation */ if (host_data_test_flag (HAS_SPE )) -__debug_save_spe (host_data_ptr (host_debug_state.pmscr_el1)); +__debug_save_spe ();/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE ))@@ -195,7 +206,7 @@ void __debug_switch_to_guest(struct kvm_vcpu *vcpu)void __debug_restore_host_buffers_nvhe (struct kvm_vcpu *vcpu) {if (host_data_test_flag (HAS_SPE )) -__debug_restore_spe (*host_data_ptr (host_debug_state.pmscr_el1)); +__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE ))__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1));if (__trace_needs_switch ())arch/arm64/kvm/hyp/nvhe/switch.c +1
-1@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE and SPE. +* above disabling of BRBE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements. Signature · 1 line
2.53.0.473.g4a7958ca14-goog
Re: [PATCH v2 2/3] KVM: arm64: Disable SPE Profiling Buffer when running in guest context
In reply to Will DeaconQuoted 21 lines · Will Deacon
The nVHE world-switch code relies on zeroing
PMSCR_EL1to disable profiling data generation in guest context when SPE is in use by the host.Unfortunately, this may leave PMBLIMITR_EL1.E set and consequently we can end up running in guest/hypervisor context with the Profiling Buffer enabled. The current "known issues" document for Rev M.a of the Arm ARM states that this can lead to speculative, out-of-context translations:
| 2.18 D23136: | | When the Profiling Buffer is enabled, profiling is not stopped, and | Discard mode is not enabled, the Statistical Profiling Unit might | cause speculative translations for the owning translation regime, | including when the owning translation regime is out-of-context.In a similar fashion to TRBE, ensure that the Profiling Buffer is disabled during the nVHE world switch before we start messing with the stage-2 MMU and trap configuration.
Quoted 9 lines
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Fixes f85279b4bd48 ("arm64: KVM: Save/restore the host SPE state when entering/leaving a VM")Signed-off-by Will Deacon <[email protected]>
Cheers,
/fuad
Quoted 116 lines
--- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/nvhe/debug-sr.c | 33 ++++++++++++++++++++---------- arch/arm64/kvm/hyp/nvhe/switch.c | 2 +- 3 files changed, 24 insertions(+), 12 deletions(-)arch/arm64/include/asm/kvm_host.h +1
-0@@ -768,6 +768,7 @@ struct kvm_host_data {struct kvm_guest_debug_arch regs;/* Statistical profiling extension */ u64 pmscr_el1; +u64 pmblimitr_el1;/* Self-hosted trace */ u64 trfcr_el1;u64 trblimitr_el1;arch/arm64/kvm/hyp/nvhe/debug-sr.c +22
-11@@ -14,20 +14,20 @@#include <asm/kvm_hyp.h> #include <asm/kvm_mmu.h> -static void __debug_save_spe (u64 *pmscr_el1) +static void __debug_save_spe (void ) { -u64 reg; +u64 *pmscr_el1, *pmblimitr_el1; -/* Clear pmscr in case of early return */ - *pmscr_el1 =0 ; + pmscr_el1 =host_data_ptr (host_debug_state.pmscr_el1); + pmblimitr_el1 =host_data_ptr (host_debug_state.pmblimitr_el1);/* * At this point, we know that this CPU implements * SPE and is available to the host. * Check if the host is actually using it ? */ - reg =read_sysreg_s (SYS_PMBLIMITR_EL1 ); -if (!(reg &BIT (PMBLIMITR_EL1_E_SHIFT ))) + *pmblimitr_el1 =read_sysreg_s (SYS_PMBLIMITR_EL1 ); +if (!(*pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* Yes; save the control register and disable data generation */ @@ -37,18 +37,29 @@ static void __debug_save_spe(u64 *pmscr_el1)/* Now drain all buffered data to memory */ psb_csync (); +dsb (nsh); + +/* And disable the profiling buffer */ +write_sysreg_s (0 ,SYS_PMBLIMITR_EL1 ); +isb (); } -static void __debug_restore_spe (u64 pmscr_el1) +static void __debug_restore_spe (void ) { -if (!pmscr_el1) +u64 pmblimitr_el1 = *host_data_ptr (host_debug_state.pmblimitr_el1); + +if (!(pmblimitr_el1 &BIT (PMBLIMITR_EL1_E_SHIFT )))return ;/* The host page table is installed, but not yet synchronised */ isb (); +/* Re-enable the profiling buffer. */ +write_sysreg_s (pmblimitr_el1,SYS_PMBLIMITR_EL1 ); +isb (); +/* Re-enable data generation */ -write_sysreg_el1 (pmscr_el1,SYS_PMSCR ); +write_sysreg_el1 (*host_data_ptr (host_debug_state.pmscr_el1),SYS_PMSCR ); }static void __trace_do_switch (u64 *saved_trfcr,u64 new_trfcr)@@ -177,7 +188,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu) {/* Disable and flush SPE data generation */ if (host_data_test_flag (HAS_SPE )) -__debug_save_spe (host_data_ptr (host_debug_state.pmscr_el1)); +__debug_save_spe ();/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE ))@@ -195,7 +206,7 @@ void __debug_switch_to_guest(struct kvm_vcpu *vcpu)void __debug_restore_host_buffers_nvhe (struct kvm_vcpu *vcpu) {if (host_data_test_flag (HAS_SPE )) -__debug_restore_spe (*host_data_ptr (host_debug_state.pmscr_el1)); +__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE ))__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1));if (__trace_needs_switch ())arch/arm64/kvm/hyp/nvhe/switch.c +1
-2@@ -278,7 +278,7 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu)* We're about to restore some new MMU state. Make sure * ongoing page-table walks that have started before we * trapped to EL2 have completed. This also synchronises the -* above disabling of BRBE and SPE. +* above disabling of BRBE. * * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", * rule R_LFHQG and subsequent information statements. -- 2.53.0.473.g4a7958ca14-goog
Will Deacon
maintainerPATCH v2 3/3 KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines
In reply to Will DeaconNow that the SPE and BRBE nVHE world-switch routines operate on the host_debug_state directly, tweak the BRBE code to do the same for consistency.
This is purely cosmetic.
--- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)
arch/arm64/kvm/hyp/nvhe/debug-sr.c +7 -5
@@ -158,9 +158,9 @@ static void __trace_switch_to_host(void) *host_data_ptr(host_debug_state.trfcr_el1)); } -static void __debug_save_brbe (u64 *brbcr_el1) +static void __debug_save_brbe (void ) { - *brbcr_el1 =0 ; +u64 *brbcr_el1 =host_data_ptr (host_debug_state.brbcr_el1);/* Check if the BRBE is enabled */ if (!(read_sysreg_el1 (SYS_BRBCR ) & (BRBCR_ELx_E0BRE | BRBCR_ELx_ExBRE)))
@@ -175,8 +175,10 @@ static void __debug_save_brbe(u64 *brbcr_el1)write_sysreg_el1 (0 ,SYS_BRBCR ); } -static void __debug_restore_brbe (u64 brbcr_el1) +static void __debug_restore_brbe (void ) { +u64 brbcr_el1 = *host_data_ptr (host_debug_state.brbcr_el1); +if (!brbcr_el1)return ;
@@ -192,7 +194,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu)/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE )) -__debug_save_brbe (host_data_ptr (host_debug_state.brbcr_el1)); +__debug_save_brbe ();if (__trace_needs_switch ())__trace_switch_to_guest ();
@@ -208,7 +210,7 @@ void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)if (host_data_test_flag (HAS_SPE ))__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE )) -__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1)); +__debug_restore_brbe ();if (__trace_needs_switch ())__trace_switch_to_host (); }
Signature · 1 line
2.53.0.473.g4a7958ca14-goog
Re: [PATCH v2 3/3] KVM: arm64: Don't pass host_debug_state to BRBE world-switch routines
Quoted 7 lines · Will Deacon
Now that the SPE and BRBE nVHE world-switch routines operate on the
host_debug_statedirectly, tweak the BRBE code to do the same for consistency.This is purely cosmetic.
Quoted 8 lines
Cc Marc Zyngier <[email protected]>Cc Oliver Upton <[email protected]>Cc James Clark <[email protected]>Cc Leo Yan <[email protected]>Cc Suzuki K Poulose <[email protected]>Cc Fuad Tabba <[email protected]>Cc Alexandru Elisei <[email protected]>Signed-off-by Will Deacon <[email protected]>
Cheers,
/fuad
Quoted 53 lines
--- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)arch/arm64/kvm/hyp/nvhe/debug-sr.c +7
-6@@ -158,9 +158,9 @@ static void __trace_switch_to_host(void) *host_data_ptr(host_debug_state.trfcr_el1)); } -static void __debug_save_brbe (u64 *brbcr_el1) +static void __debug_save_brbe (void ) { - *brbcr_el1 =0 ; +u64 *brbcr_el1 =host_data_ptr (host_debug_state.brbcr_el1);/* Check if the BRBE is enabled */ if (!(read_sysreg_el1 (SYS_BRBCR ) & (BRBCR_ELx_E0BRE | BRBCR_ELx_ExBRE)))@@ -175,8 +175,10 @@ static void __debug_save_brbe(u64 *brbcr_el1)write_sysreg_el1 (0 ,SYS_BRBCR ); } -static void __debug_restore_brbe (u64 brbcr_el1) +static void __debug_restore_brbe (void ) { +u64 brbcr_el1 = *host_data_ptr (host_debug_state.brbcr_el1); +if (!brbcr_el1)return ;@@ -192,7 +194,7 @@ void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu)/* Disable BRBE branch records */ if (host_data_test_flag (HAS_BRBE )) -__debug_save_brbe (host_data_ptr (host_debug_state.brbcr_el1)); +__debug_save_brbe ();if (__trace_needs_switch ())__trace_switch_to_guest ();@@ -208,7 +210,7 @@ void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)if (host_data_test_flag (HAS_SPE ))__debug_restore_spe ();if (host_data_test_flag (HAS_BRBE )) -__debug_restore_brbe (*host_data_ptr (host_debug_state.brbcr_el1)); +__debug_restore_brbe ();if (__trace_needs_switch ())__trace_switch_to_host (); } --2.53.0.473.g4a7958ca14-goog