FAILED: Patch "drm/amdgpu: Use 5-level paging if gmc support 57-bit VA" failed to apply to 6.6-stable tree
Subsystems (3)
Sasha Levin
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
Thanks,
Sasha
------------------ original commit in Linus's tree ------------------
From 3b948dd0366a0b64c02e4ed1aefdf7825942e803 Mon Sep 17 00:00:00 2001
From: Philip Yang <[email protected]>
Date: Tue, 27 Jan 2026 13:52:33 -0500
Subject: [PATCH] drm/amdgpu: Use 5-level paging if gmc support 57-bit VA
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Regardless if CPU enable 5-level paging, GPU vm use 5-level paging if gmc init with 57-bit address space support, because
ARM64 4-level paging support 48-bit VA, x86 and GPU 4-level paging support 47-bit VA, require 5-level paging on GPU to support ARM64.
NPA address space 52-bit mapping on NPA GPU VM require 5-level paging.
Debugger trap get device snapshot expect LDS and Scratch base, limit above 57-bit, which is set only for 5-level paging.
--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ----------------- 1 file changed, 17 deletions(-)
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +0 -17
@@ -2360,26 +2360,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, unsigned max_bits) {unsigned int max_size =1 << (max_bits -30 ); -bool sys_5level_pgtable = false;unsigned int vm_size;uint64_t tmp; -#ifdef CONFIG_X86_64 -/* -* Refer to function configure_5level_paging() for details. -*/ - sys_5level_pgtable = (native_read_cr4 () &X86_CR4_LA57 ); -#endif - -/* -* If GPU supports 5-level page table, but system uses 4-level page table, -* then use 4-level page table on GPU -*/ -if (max_level ==4 && !sys_5level_pgtable) { - min_vm_size =256 *1024 ; - max_level =3 ; - } -/* adjust vm size first */ if (amdgpu_vm_size !=-1 ) { vm_size = amdgpu_vm_size;
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2.51.0