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spi: dt-bindings: mpfs-spi: permit resets

PATCH In review Conor Dooley 2 participants 3 messages Mar 3

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PATCH 1/2 spi: dt-bindings: mpfs-spi: permit resets

From: Conor Dooley <[email protected]>

CoreSPI, CoreQSPI and the hardened versions of them on mpfs and pic64gx have a reset pin. For the first two, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use.

---
CC: Conor Dooley <[email protected]>
CC: Daire McNamara <[email protected]>
CC: Mark Brown <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]

---
 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 3 +++
 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +3 -0
index 636338d24bdfb..b7d8acc924be4 100644
@@ -41,6 +41,9 @@ properties:
   clocks:
     maxItems: 1
 
+  resets:
+    maxItems: 1
+
   microchip,apb-datawidth:
     description: APB bus data width in bits.
     $ref: /schemas/types.yaml#/definitions/uint32
Signature · 1 line
2.51.0
#1 lore raw

PATCH 2/2 spi: dt-bindings: mpfs-spi: remove clock-names

From: Conor Dooley <[email protected]>

This binding documented clock-names, but never bothered to document what the name should be, rendering the property useless to software. It's not a required property, so it can just be removed without harming any software that conjured up it's own name for the clock, as they could not rely on it being there to begin with.

---
CC: Conor Dooley <[email protected]>
CC: Daire McNamara <[email protected]>
CC: Mark Brown <[email protected]>
CC: Rob Herring <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]
CC: [email protected]

---
 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml | 3 ---
 1 file changed, 3 deletions(-)
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml +0 -3
index b7d8acc924be4..8ff50dfcf5855 100644
@@ -35,9 +35,6 @@ properties:
   interrupts:
     maxItems: 1
 
-  clock-names:
-    maxItems: 1
-
   clocks:
     maxItems: 1
 
Signature · 1 line
2.51.0
maintainer
#2 lore raw
In reply to Conor Dooley
Quoted 9 lines · Conor Dooley

CoreSPI, CoreQSPI and the hardened versions of them on mpfs and pic64gx have a reset pin. For the first two, usually this is wired to a common fabric reset not managed by software and for the latter two the platform firmware takes them out of reset on first-party boards (or those using modified versions of the vendor firmware), but not all boards may take this approach. Permit providing a reset in devicetree for Linux, or other devicetree-consuming software, to use.

[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/2] spi: dt-bindings: mpfs-spi: permit resets

      commit: f5d09914d473059e4e851c6a3bfa9f0e848c63e4
[2/2] spi: dt-bindings: mpfs-spi: remove clock-names
      commit: 96f06d055ca03d1dfb5830fd07ff6eadbd66264c

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark