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PCI: Enable async probe by default

RFC In review Anand Moon 4 participants 23 messages Mar 4 – Mar 6

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Anand Moon

author
#0 lore raw

cover PCI: Enable async probe by default

Following recent asynchronous probing updates to the Rockchip PCIe controller, this change enables default async probe functionality for all DesignWare Core (DWC) based controllers to optimize boot times [0].

[0] https://lore.kernel.org/all/[email protected]/

This PROBE_PREFER_ASYNCHRONOUS flag help to parallelize device initialization.

Thanks
-Anand

Anand Moon (18):
PCI: al: Allow asynchronous probing for background link training
PCI: amd-mdb: Allow asynchronous probing for background link training
PCI: armada8x: Allow asynchronous probing for background link training
PCI: artpec6: Allow asynchronous probing for background link training
PCI: bt1: Allow asynchronous probing for background link training
PCI: dra7xx: Allow asynchronous probing for background link training
PCI: exynos: Allow asynchronous probing for background link training
PCI: fu740: Allow asynchronous probing for background link training
PCI: intel-gw: Allow asynchronous probing for background link training
PCI: keystone: Allow asynchronous probing for background link training
PCI: keembay: Allow asynchronous probing for background link training
PCI: kirin: Allow asynchronous probing for background link training
PCI: layerscape: Allow asynchronous probing for background link
training
PCI: meson: Allow asynchronous probing for background link training
PCI: sophgo: Allow asynchronous probing for background link training
PCI: tegra194: Allow asynchronous probing for background link training
PCI: uniphier: Allow asynchronous probing for background link training
PCI: visconti: Allow asynchronous probing for background link training

 drivers/pci/controller/dwc/pci-dra7xx.c     | 1 +
 drivers/pci/controller/dwc/pci-exynos.c     | 1 +
 drivers/pci/controller/dwc/pci-keystone.c   | 1 +
 drivers/pci/controller/dwc/pci-layerscape.c | 1 +
 drivers/pci/controller/dwc/pci-meson.c      | 1 +
 drivers/pci/controller/dwc/pcie-al.c        | 1 +
 drivers/pci/controller/dwc/pcie-amd-mdb.c   | 1 +
 drivers/pci/controller/dwc/pcie-armada8k.c  | 1 +
 drivers/pci/controller/dwc/pcie-artpec6.c   | 1 +
 drivers/pci/controller/dwc/pcie-bt1.c       | 1 +
 drivers/pci/controller/dwc/pcie-fu740.c     | 7 ++++---
 drivers/pci/controller/dwc/pcie-intel-gw.c  | 1 +
 drivers/pci/controller/dwc/pcie-keembay.c   | 1 +
 drivers/pci/controller/dwc/pcie-kirin.c     | 1 +
 drivers/pci/controller/dwc/pcie-sophgo.c    | 1 +
 drivers/pci/controller/dwc/pcie-tegra194.c  | 1 +
 drivers/pci/controller/dwc/pcie-uniphier.c  | 1 +
 drivers/pci/controller/dwc/pcie-visconti.c  | 1 +
 18 files changed, 21 insertions(+), 3 deletions(-)

base-commit: 0031c06807cfa8aa51a759ff8aa09e1aa48149af

Signature · 1 line
2.50.1
author
#1 lore raw

RFC 1/18 PCI: al: Allow asynchronous probing for background link training

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-al.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-al.c +1 -0
index 345c281c74fe..6e3f52ccc1fa 100644
@@ -383,6 +383,7 @@ static struct platform_driver al_pcie_driver = {
 		.name	= "al-pcie",
 		.of_match_table = al_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = al_pcie_probe,
 };
Signature · 1 line
2.50.1
author
#2 lore raw

RFC 2/18 PCI: amd-mdb: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-amd-mdb.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-amd-mdb.c +1 -0
index 3c6e837465bb..3da5ceac9b6a 100644
@@ -519,6 +519,7 @@ static struct platform_driver amd_mdb_pcie_driver = {
 		.name	= "amd-mdb-pcie",
 		.of_match_table = amd_mdb_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = amd_mdb_pcie_probe,
 };
Signature · 1 line
2.50.1
author
#3 lore raw

RFC 3/18 PCI: armada8x: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-armada8k.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-armada8k.c +1 -0
index c2650fd0d458..ffb5554a2a8d 100644
@@ -344,6 +344,7 @@ static struct platform_driver armada8k_pcie_driver = {
 		.name	= "armada8k-pcie",
 		.of_match_table = armada8k_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(armada8k_pcie_driver);
Signature · 1 line
2.50.1
author
#4 lore raw

RFC 4/18 PCI: artpec6: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-artpec6.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-artpec6.c +1 -0
index e994b75986c3..d8b827926b85 100644
@@ -520,6 +520,7 @@ static struct platform_driver artpec6_pcie_driver = {
 		.name	= "artpec6-pcie",
 		.of_match_table = artpec6_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(artpec6_pcie_driver);
Signature · 1 line
2.50.1
author
#5 lore raw

RFC 5/18 PCI: bt1: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-bt1.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-bt1.c +1 -0
index 1340edc18d12..ef6a3c7fa279 100644
@@ -636,6 +636,7 @@ static struct platform_driver bt1_pcie_driver = {
 	.driver = {
 		.name	= "bt1-pcie",
 		.of_match_table = bt1_pcie_of_match,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 module_platform_driver(bt1_pcie_driver);
Signature · 1 line
2.50.1
author
#6 lore raw

RFC 6/18 PCI: dra7xx: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pci-dra7xx.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pci-dra7xx.c +1 -0
index d5d26229063f..be470d54b2ee 100644
@@ -951,6 +951,7 @@ static struct platform_driver dra7xx_pcie_driver = {
 		.of_match_table = of_dra7xx_pcie_match,
 		.suppress_bind_attrs = true,
 		.pm	= &dra7xx_pcie_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.shutdown = dra7xx_pcie_shutdown,
 };
Signature · 1 line
2.50.1
author
#7 lore raw

RFC 7/18 PCI: exynos: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pci-exynos.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pci-exynos.c +1 -0
index 0bb7d4f5d784..ee2423e16b58 100644
@@ -388,6 +388,7 @@ static struct platform_driver exynos_pcie_driver = {
 		.name	= "exynos-pcie",
 		.of_match_table = exynos_pcie_of_match,
 		.pm		= &exynos_pcie_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 module_platform_driver(exynos_pcie_driver);
Signature · 1 line
2.50.1
author
#8 lore raw

RFC 8/18 PCI: fu740: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

Fix the identation of the callback functions.

---
 drivers/pci/controller/dwc/pcie-fu740.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
drivers/pci/controller/dwc/pcie-fu740.c +4 -3
index 66367252032b..aa6a15baf3fd 100644
@@ -346,9 +346,10 @@ static const struct of_device_id fu740_pcie_of_match[] = {
 
 static struct platform_driver fu740_pcie_driver = {
 	.driver = {
-		   .name = "fu740-pcie",
-		   .of_match_table = fu740_pcie_of_match,
-		   .suppress_bind_attrs = true,
+		.name = "fu740-pcie",
+		.of_match_table = fu740_pcie_of_match,
+		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = fu740_pcie_probe,
 	.shutdown = fu740_pcie_shutdown,
Signature · 1 line
2.50.1
maintainer
#9 lore raw

Re: [RFC v1 08/18] PCI: fu740: Allow asynchronous probing for background link training

From: Frank Li (AI-BOT) <[email protected]>

Commit message has a typo:

Quoted 1 line

Fix the identation of the callback functions.

Should be "indentation" (two 'n's).

The code changes look good otherwise. The indentation fix aligns with kernel style (8-char tabs), and adding PROBE_PREFER_ASYNCHRONOUS is a straightforward addition that matches the stated intent.

AI bot review and may be useless.

#10 lore raw

Re: [RFC v1 08/18] PCI: fu740: Allow asynchronous probing for background link training

Quoted 6 lines · Frank Li

From: Frank Li (AI-BOT) <[email protected]>

Commit message has a typo:

Quoted 1 line

Fix the identation of the callback functions.

Quoted 7 lines

Should be "indentation" (two 'n's).

The code changes look good otherwise. The indentation fix aligns with kernel style (8-char tabs), and adding PROBE_PREFER_ASYNCHRONOUS is a straightforward addition that matches the stated intent.

AI bot review and may be useless.

So don't send us useless reviews. Trim your reply list, so only you see them.

Best regards,
Krzysztof

author
#11 lore raw

RFC 9/18 PCI: intel-gw: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-intel-gw.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-intel-gw.c +1 -0
index c21906eced61..bc5d96dc12bf 100644
@@ -442,6 +442,7 @@ static struct platform_driver intel_pcie_driver = {
 		.name = "intel-gw-pcie",
 		.of_match_table = of_intel_pcie_match,
 		.pm = &intel_pcie_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(intel_pcie_driver);
Signature · 1 line
2.50.1
author
#12 lore raw

RFC 10/18 PCI: keystone: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pci-keystone.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pci-keystone.c +1 -0
index 20fa4dadb82a..b5c0c690593e 100644
@@ -1351,6 +1351,7 @@ static struct platform_driver ks_pcie_driver = {
 	.driver = {
 		.name	= "keystone-pcie",
 		.of_match_table = ks_pcie_of_match,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 
Signature · 1 line
2.50.1
author
#13 lore raw

RFC 11/18 PCI: keembay: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while; allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-keembay.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-keembay.c +1 -0
index 2666a9c3d67e..a82d69b37e4d 100644
@@ -478,6 +478,7 @@ static struct platform_driver keembay_pcie_driver = {
 		.name = "keembay-pcie",
 		.of_match_table = keembay_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe  = keembay_pcie_probe,
 };
Signature · 1 line
2.50.1
author
#14 lore raw

RFC 12/18 PCI: kirin: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while; allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-kirin.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-kirin.c +1 -0
index 91559c8b1866..bc905056a9d7 100644
@@ -757,6 +757,7 @@ static struct platform_driver kirin_pcie_driver = {
 		.name			= "kirin-pcie",
 		.of_match_table		= kirin_pcie_match,
 		.suppress_bind_attrs	= true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 module_platform_driver(kirin_pcie_driver);
Signature · 1 line
2.50.1
author
#15 lore raw

RFC 13/18 PCI: layerscape: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pci-layerscape.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pci-layerscape.c +1 -0
index a44b5c256d6e..43a28d9ea7b0 100644
@@ -410,6 +410,7 @@ static struct platform_driver ls_pcie_driver = {
 		.of_match_table = ls_pcie_of_match,
 		.suppress_bind_attrs = true,
 		.pm = &ls_pcie_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(ls_pcie_driver);
Signature · 1 line
2.50.1
author
#16 lore raw

RFC 14/18 PCI: meson: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pci-meson.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pci-meson.c +1 -0
index 0694084f612b..280146f7b783 100644
@@ -467,6 +467,7 @@ static struct platform_driver meson_pcie_driver = {
 	.driver = {
 		.name = "meson-pcie",
 		.of_match_table = meson_pcie_of_match,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 
Signature · 1 line
2.50.1
author
#17 lore raw

RFC 15/18 PCI: sophgo: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-sophgo.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-sophgo.c +1 -0
index 044088898819..0393f4b613de 100644
@@ -269,6 +269,7 @@ static struct platform_driver sophgo_pcie_driver = {
 		.name = "sophgo-pcie",
 		.of_match_table = sophgo_pcie_of_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = sophgo_pcie_probe,
 };
Signature · 1 line
2.50.1
author
#18 lore raw

RFC 16/18 PCI: tegra194: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-tegra194.c +1 -0
index 06571d806ab3..7381d0019d24 100644
@@ -2493,6 +2493,7 @@ static struct platform_driver tegra_pcie_dw_driver = {
 		.name	= "tegra194-pcie",
 		.pm = &tegra_pcie_dw_pm_ops,
 		.of_match_table = tegra_pcie_dw_of_match,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 module_platform_driver(tegra_pcie_dw_driver);
Signature · 1 line
2.50.1
author
#19 lore raw

RFC 17/18 PCI: uniphier: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-uniphier.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-uniphier.c +1 -0
index 297e7a3d9b36..53f3bc9f5ba7 100644
@@ -404,6 +404,7 @@ static struct platform_driver uniphier_pcie_driver = {
 	.driver = {
 		.name = "uniphier-pcie",
 		.of_match_table = uniphier_pcie_match,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(uniphier_pcie_driver);
Signature · 1 line
2.50.1
author
#20 lore raw

RFC 18/18 PCI: visconti: Allow asynchronous probing for background link training

In reply to Anand Moon

Establishing a PCIe link can take a while, allow asynchronous probing so that link establishment can happen in the background while other devices are being probed.

---
 drivers/pci/controller/dwc/pcie-visconti.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pci/controller/dwc/pcie-visconti.c +1 -0
index cdeac6177143..f21cc95fe89f 100644
@@ -324,6 +324,7 @@ static struct platform_driver visconti_pcie_driver = {
 		.name = "visconti-pcie",
 		.of_match_table = visconti_pcie_match,
 		.suppress_bind_attrs = true,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 };
 builtin_platform_driver(visconti_pcie_driver);
Signature · 1 line
2.50.1
#21 lore raw
In reply to Anand Moon

Hello Anand,

Quoted 53 lines · Anand Moon

Following recent asynchronous probing updates to the Rockchip PCIe controller, this change enables default async probe functionality for all DesignWare Core (DWC) based controllers to optimize boot times [0].

[0] https://lore.kernel.org/all/[email protected]/

This PROBE_PREFER_ASYNCHRONOUS flag help to parallelize device initialization.

Thanks
-Anand

Anand Moon (18):
PCI: al: Allow asynchronous probing for background link training
PCI: amd-mdb: Allow asynchronous probing for background link training
PCI: armada8x: Allow asynchronous probing for background link training
PCI: artpec6: Allow asynchronous probing for background link training
PCI: bt1: Allow asynchronous probing for background link training
PCI: dra7xx: Allow asynchronous probing for background link training
PCI: exynos: Allow asynchronous probing for background link training
PCI: fu740: Allow asynchronous probing for background link training
PCI: intel-gw: Allow asynchronous probing for background link training
PCI: keystone: Allow asynchronous probing for background link training
PCI: keembay: Allow asynchronous probing for background link training
PCI: kirin: Allow asynchronous probing for background link training
PCI: layerscape: Allow asynchronous probing for background link
training
PCI: meson: Allow asynchronous probing for background link training
PCI: sophgo: Allow asynchronous probing for background link training
PCI: tegra194: Allow asynchronous probing for background link training
PCI: uniphier: Allow asynchronous probing for background link training
PCI: visconti: Allow asynchronous probing for background link training

  drivers/pci/controller/dwc/pci-dra7xx.c     | 1 +
  drivers/pci/controller/dwc/pci-exynos.c     | 1 +
  drivers/pci/controller/dwc/pci-keystone.c   | 1 +
  drivers/pci/controller/dwc/pci-layerscape.c | 1 +
  drivers/pci/controller/dwc/pci-meson.c      | 1 +
  drivers/pci/controller/dwc/pcie-al.c        | 1 +
  drivers/pci/controller/dwc/pcie-amd-mdb.c   | 1 +
  drivers/pci/controller/dwc/pcie-armada8k.c  | 1 +
  drivers/pci/controller/dwc/pcie-artpec6.c   | 1 +
  drivers/pci/controller/dwc/pcie-bt1.c       | 1 +
  drivers/pci/controller/dwc/pcie-fu740.c     | 7 ++++---
  drivers/pci/controller/dwc/pcie-intel-gw.c  | 1 +
  drivers/pci/controller/dwc/pcie-keembay.c   | 1 +
  drivers/pci/controller/dwc/pcie-kirin.c     | 1 +
  drivers/pci/controller/dwc/pcie-sophgo.c    | 1 +
  drivers/pci/controller/dwc/pcie-tegra194.c  | 1 +
  drivers/pci/controller/dwc/pcie-uniphier.c  | 1 +
  drivers/pci/controller/dwc/pcie-visconti.c  | 1 +
  18 files changed, 21 insertions(+), 3 deletions(-)
Quoted 1 line

base-commit: 0031c06807cfa8aa51a759ff8aa09e1aa48149af

Suggest you indicate in the title of the cover letter for the next patch that this patchset is only related to dwc.

Thanks,

Chen

author
#22 lore raw

Hi Chen,

Quoted 57 lines · Chen Wang

Hello Anand,

Quoted 53 lines · Anand Moon

Following recent asynchronous probing updates to the Rockchip PCIe controller, this change enables default async probe functionality for all DesignWare Core (DWC) based controllers to optimize boot times [0].

[0] https://lore.kernel.org/all/[email protected]/

This PROBE_PREFER_ASYNCHRONOUS flag help to parallelize device initialization.

Thanks
-Anand

Anand Moon (18):
PCI: al: Allow asynchronous probing for background link training
PCI: amd-mdb: Allow asynchronous probing for background link training
PCI: armada8x: Allow asynchronous probing for background link training
PCI: artpec6: Allow asynchronous probing for background link training
PCI: bt1: Allow asynchronous probing for background link training
PCI: dra7xx: Allow asynchronous probing for background link training
PCI: exynos: Allow asynchronous probing for background link training
PCI: fu740: Allow asynchronous probing for background link training
PCI: intel-gw: Allow asynchronous probing for background link training
PCI: keystone: Allow asynchronous probing for background link training
PCI: keembay: Allow asynchronous probing for background link training
PCI: kirin: Allow asynchronous probing for background link training
PCI: layerscape: Allow asynchronous probing for background link
training
PCI: meson: Allow asynchronous probing for background link training
PCI: sophgo: Allow asynchronous probing for background link training
PCI: tegra194: Allow asynchronous probing for background link training
PCI: uniphier: Allow asynchronous probing for background link training
PCI: visconti: Allow asynchronous probing for background link training

  drivers/pci/controller/dwc/pci-dra7xx.c     | 1 +
  drivers/pci/controller/dwc/pci-exynos.c     | 1 +
  drivers/pci/controller/dwc/pci-keystone.c   | 1 +
  drivers/pci/controller/dwc/pci-layerscape.c | 1 +
  drivers/pci/controller/dwc/pci-meson.c      | 1 +
  drivers/pci/controller/dwc/pcie-al.c        | 1 +
  drivers/pci/controller/dwc/pcie-amd-mdb.c   | 1 +
  drivers/pci/controller/dwc/pcie-armada8k.c  | 1 +
  drivers/pci/controller/dwc/pcie-artpec6.c   | 1 +
  drivers/pci/controller/dwc/pcie-bt1.c       | 1 +
  drivers/pci/controller/dwc/pcie-fu740.c     | 7 ++++---
  drivers/pci/controller/dwc/pcie-intel-gw.c  | 1 +
  drivers/pci/controller/dwc/pcie-keembay.c   | 1 +
  drivers/pci/controller/dwc/pcie-kirin.c     | 1 +
  drivers/pci/controller/dwc/pcie-sophgo.c    | 1 +
  drivers/pci/controller/dwc/pcie-tegra194.c  | 1 +
  drivers/pci/controller/dwc/pcie-uniphier.c  | 1 +
  drivers/pci/controller/dwc/pcie-visconti.c  | 1 +
  18 files changed, 21 insertions(+), 3 deletions(-)
Quoted 5 lines
Quoted 1 line

base-commit: 0031c06807cfa8aa51a759ff8aa09e1aa48149af

Suggest you indicate in the title of the cover letter for the next patch that this patchset is only related to dwc.

Thanks, If I get positive feedback I will append dwc in the $subject.

Quoted 4 lines

Thanks,

Chen

Thanks
-Anand