arm64: dts: rockchip: Enable PCIe CLKREQ# for RK3588 on Rock 5b-5bp-5t series
Subsystems (2)
PATCH 1/1 arm64: dts: rockchip: Enable PCIe CLKREQ# for RK3588 on Rock 5b-5bp-5t series
Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency.
--- arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +6 -3
@@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay";
@@ -476,7 +477,8 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay";
@@ -488,7 +490,8 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay";
base-commit: b29fb8829bff243512bb8c8908fd39406f9fd4c3
Signature · 1 line
2.50.1
Quoted 10 lines · Anand Moon
Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency.Cc Shawn Lin <[email protected]>Signed-off-by Anand Moon <[email protected]>---
It would be better if you could put the link to the schematic here(under "---") for folks easy to review. I paste it here for reference：
https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf
Quoted 18 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +2
-1@@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay";
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie2x1l0 { · line 480
Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1@@ -476,7 +477,8 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;
Isn't it m1(PCIE20_1_2_CLKREQn_M1_L in the schematic)?
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie30phy { · line 493
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +2
-1+ supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay";@@ -488,7 +490,8 @@ &pcie30phy { &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>;
The pin is correct but I don't think it would support L1 substates because the refclk is out of control. For any refclk coming from external clock generator, clkreq# should connect to the enable pin of the clock generator.
Quoted 7 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay";base-commit:
b29fb8829bff243512bb8c8908fd39406f9fd4c3
Hi Shawn,
Thanks for your review comments.
Quoted 9 lines · Shawn Lin
Quoted 7 lines · Anand Moon
Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency.
Quoted 3 lines
Quoted 3 lines
Cc Shawn Lin <[email protected]>Signed-off-by Anand Moon <[email protected]>---
I verified the change by comparing the lspci -vvv output from before and after the modification.
Quoted 5 lines
It would be better if you could put the link to the schematic
here(under "---")for folks easy to review. I paste it here for reference：https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf
Ok, I will follow this advice next time,
Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +2
-1@@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay";@@ -476,7 +477,8 @@ &pcie2x1l0 {
Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie2x1l0 { · line 480
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;Isn't it
m1(PCIE20_1_2_CLKREQn_M1_L in the schematic)?
I just used the pinctrl label GPIO3_C7_u as a reference to select this one. see below.
The RK3588 Technical Reference Manual (TRM) Part 2 provides the following details regarding the clkreq# signal
pcie_clkreq_in/out_n M0 PCIE20X1_2_CLKREQN_M0 GPIO3_C7_u
pcie_clkreq_in/out_n M1 PCIE20X1_2_CLKREQN_M1 GPIO4_B7_u
Quoted 7 lines
Quoted 7 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay";@@ -488,7 +490,8 @@ &pcie30phy {
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie30phy { · line 493
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>;The pin is correct but I don't think it would support L1 substates because the refclk is out of control. For any refclk coming from external clock generator, clkreq# should connect to the enable pin of the clock generator.
I did not find the external clkreq# signal for this #clkreq signal in the schematics.
PCIE30X4_CLKREQn_M1_L (GPIO4_B4_u) .
Quoted 7 lines
Quoted 7 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay";base-commit:
b29fb8829bff243512bb8c8908fd39406f9fd4c3
Thanks
-Anand
Quoted 55 lines · Anand Moon
Hi Shawn,
Thanks for your review comments.
Quoted 9 lines · Shawn Lin
Quoted 7 lines · Anand Moon
Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency.Quoted 3 lines
Quoted 3 lines
Cc Shawn Lin <[email protected]>Signed-off-by Anand Moon <[email protected]>---
I verified the change by comparing the lspci -vvv output from before and after the modification.
Quoted 5 lines
It would be better if you could put the link to the schematic
here(under "---")for folks easy to review. I paste it here for reference：https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf
Ok, I will follow this advice next time,
Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +2
-1@@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay";@@ -476,7 +477,8 @@ &pcie2x1l0 {Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie2x1l0 { · line 480
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;Isn't it
m1(PCIE20_1_2_CLKREQn_M1_L in the schematic)?I just used the pinctrl label
GPIO3_C7_uas a reference to select this one. see below.
Quoted 6 lines
The RK3588 Technical Reference Manual (TRM) Part 2 provides the following details regarding the clkreq# signal
pcie_clkreq_in/out_n M0PCIE20X1_2_CLKREQN_M0GPIO3_C7_u
pcie_clkreq_in/out_n M1PCIE20X1_2_CLKREQN_M1GPIO4_B7_u
Okay, I checked it again, you are right. Apprently the schematic label is insane which marks it as PCIE20_1_2_CLKREQn_M1_L....
Quoted 18 lines
Quoted 8 lines
Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay";@@ -488,7 +490,8 @@ &pcie30phy {Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie30phy { · line 493
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>;The pin is correct but I don't think it would support L1 substates because the refclk is out of control. For any refclk coming from external clock generator, clkreq# should connect to the enable pin of the clock generator.
Quoted 4 lines
I did not find the external clkreq# signal for this #clkreq signal in the schematics.
PCIE30X4_CLKREQn_M1_L(GPIO4_B4_u) .
What I meant is PCIE30X4_CLKREQn_M1_L is connected between root port
and M.2 slot which is not the right hardware design to support L1 substates with PCIe3.0 PHY. We could do that for combophy as the refclk is auto controlled by controller when entering and exiting L1 substates.
But for PCIe3.0 PHY the refclk is always there coming fromAu5426_device, so the this port tries to enter L1 substates, no
component could turn off the refclk to meet the timing of entering L1
substate, except you connect clkreq# to the Au5426, because in that case
PHY could gate the incoming refclk via clkreq#, thanks to the natural
behaviour of how clkreq# is controlled.
To clarify, PCIE30X4_CLKREQn_M1_L is connected between the Root Port and the M.2 slot. This hardware configuration is not suitable for supporting L1 Substates with the PCIe 3.0 PHY. While this setup works for the Combo PHY—where the controller automatically manages the reference clock during L1 Substate entry and exit—it fails with the dedicated PCIe 3.0 PHY. In the latter case, the reference clock from the Au5426_device is always active. Consequently, when this port attempts to enter L1 Substates, no component can gate the reference clock to meet the required timing specifications.
The only way to satisfy the timing requirements is to connect CLKREQ# directly to the Au5426. This allows the PHY to gate the incoming reference clock via the CLKREQ# signal, leveraging its standard control behavior.
Otherwise you could only see it in L1 instead of L1 substates. By the way, how do you verfy it could enter L1 substate? Do you use debugfs like below ?
cat /sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status
Quoted 6 lines
Quoted 6 lines
Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay";
Quoted 6 lines
Quoted 2 lines
Quoted 2 lines
base-commit:
b29fb8829bff243512bb8c8908fd39406f9fd4c3Thanks
-Anand
_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
Hi Shawn,
Quoted 111 lines · Shawn Lin
Quoted 55 lines · Anand Moon
Hi Shawn,
Thanks for your review comments.
Quoted 9 lines · Shawn Lin
Quoted 7 lines · Anand Moon
Add supports-clkreq and the corresponding pinmux configurations for PCIe ASPM L1 substates on the Rock 5B, 5B+, and 5T.
The supports-clkreq flag informs the PCIe controller that the hardware routing for the CLKREQ# sideband signal is present. This enables support for PCIe ASPM (Active State Power Management) L1 substates, allowing for better power efficiency.Quoted 3 lines
Quoted 3 lines
Cc Shawn Lin <[email protected]>Signed-off-by Anand Moon <[email protected]>---
I verified the change by comparing the lspci -vvv output from before and after the modification.
Quoted 5 lines
It would be better if you could put the link to the schematic
here(under "---")for folks easy to review. I paste it here for reference：https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf
Ok, I will follow this advice next time,
Quoted 20 lines
Quoted 20 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +2
-1@@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay";@@ -476,7 +477,8 @@ &pcie2x1l0 {Quoted 6 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie2x1l0 { · line 480
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>;Isn't it
m1(PCIE20_1_2_CLKREQn_M1_L in the schematic)?I just used the pinctrl label
GPIO3_C7_uas a reference to select this one. see below.Quoted 6 lines
The RK3588 Technical Reference Manual (TRM) Part 2 provides the following details regarding the clkreq# signal
pcie_clkreq_in/out_n M0PCIE20X1_2_CLKREQN_M0GPIO3_C7_u
pcie_clkreq_in/out_n M1PCIE20X1_2_CLKREQN_M1GPIO4_B7_uOkay, I checked it again, you are right. Apprently the schematic label is insane which marks it as
PCIE20_1_2_CLKREQn_M1_L....Quoted 18 lines
Quoted 8 lines
Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-0+ supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay";@@ -488,7 +490,8 @@ &pcie30phy {Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi &pcie30phy { · line 493
Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +1
-1&pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_rst>; + pinctrl-0 = <&pcie3_rst>, <&pcie30x4m1_clkreqn>;The pin is correct but I don't think it would support L1 substates because the refclk is out of control. For any refclk coming from external clock generator, clkreq# should connect to the enable pin of the clock generator.
Quoted 4 lines
I did not find the external clkreq# signal for this #clkreq signal in the schematics.
PCIE30X4_CLKREQn_M1_L(GPIO4_B4_u) .What I meant is
PCIE30X4_CLKREQn_M1_Lis connected between root port and M.2 slot which is not the right hardware design to support L1 substates with PCIe3.0 PHY. We could do that for combophy as the refclk is auto controlled by controller when entering and exiting L1 substates. But for PCIe3.0 PHY the refclk is always there coming fromAu5426_device, so the this port tries to enter L1 substates, no component could turn off the refclk to meet the timing of entering L1 substate, except you connect clkreq# to the Au5426, because in that case PHY could gate the incoming refclk via clkreq#, thanks to the natural behaviour of how clkreq# is controlled.To clarify,
PCIE30X4_CLKREQn_M1_Lis connected between the Root Port and the M.2 slot. This hardware configuration is not suitable for supporting L1 Substates with the PCIe 3.0 PHY. While this setup works for the Combo PHY—where the controller automatically manages the reference clock during L1 Substate entry and exit—it fails with the dedicated PCIe 3.0 PHY. In the latter case, the reference clock from theAu5426_deviceis always active. Consequently, when this port attempts to enter L1 Substates, no component can gate the reference clock to meet the required timing specifications.
Quoted 5 lines
The only way to satisfy the timing requirements is to connect CLKREQ# directly to the Au5426. This allows the PHY to gate the incoming reference clock via the CLKREQ# signal, leveraging its standard control behavior.
Thanks for the info. I've decided to omit this setting.
Quoted 5 lines
Otherwise you could only see it in L1 instead of L1 substates. By the way, how do you verfy it could enter L1 substate? Do you use debugfs like below ?
cat/sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status
[root@rockpi-5b alarm]# cat /sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status L123_SEND_EIDLE (0x13)
[root@rockpi-5b alarm]# cat /sys/kernel/debug/dwc_pcie_a41000000.pcie/ltssm_status L0 (0x11)
[root@rockpi-5b alarm]# cat /sys/kernel/debug/dwc_pcie_a40800000.pcie/ltssm_status L1_IDLE (0x14)
I had just verified with lspci --vvv diff.
$ diff -Nru lspci.before lspci.after
--- lspci.before 2026-03-11 15:47:28.391050648 +0530
+++ lspci.after 2026-03-11 16:30:33.337808724 +0530
@@ -2,8 +2,8 @@
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
- Interrupt: pin A routed to IRQ 119
- IOMMU group: 10
+ Interrupt: pin A routed to IRQ 117
+ IOMMU group: 11
Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
I/O behind bridge: f000-0fff [disabled] [16-bit]
Memory behind bridge: f0200000-f02fffff [size=1M] [32-bit]
@@ -76,9 +76,11 @@
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [190 v1] L1 PM Substates
- L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2-
ASPM_L1.1- L1_PM_Substates-
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
- L1SubCtl2:
+ T_CommonMode=10us LTR1.2_Threshold=26016ns
+ L1SubCtl2: T_PwrOn=10us
Capabilities: [1d0 v1] Vendor Specific Information: ID=0002
Rev=4 Len=100 <?>
Capabilities: [2d0 v1] Vendor Specific Information: ID=0006
Rev=0 Len=018 <?>
Kernel driver in use: pcieport
@@ -89,8 +91,8 @@
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
- Interrupt: pin A routed to IRQ 118
- IOMMU group: 10
+ Interrupt: pin A routed to IRQ 116
+ IOMMU group: 11
Region 0: Memory at f0200000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0-,D1-,D2-,D3hot-,D3cold-)
@@ -156,7 +158,7 @@
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
- T_CommonMode=0us LTR1.2_Threshold=0ns
+ T_CommonMode=0us LTR1.2_Threshold=26016ns
L1SubCtl2: T_PwrOn=10us
Kernel driver in use: nvme
Kernel modules: nvme
@@ -238,9 +240,11 @@
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [180 v1] L1 PM Substates
- L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2-
ASPM_L1.1- L1_PM_Substates-
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
- L1SubCtl2:
+ T_CommonMode=30us LTR1.2_Threshold=54272ns
+ L1SubCtl2: T_PwrOn=18us
Capabilities: [190 v1] Vendor Specific Information: ID=0002
Rev=4 Len=100 <?>
Kernel driver in use: pcieport
Kernel modules: pci_endpoint_test
@@ -250,7 +254,7 @@
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
- Interrupt: pin A routed to IRQ 147
+ Interrupt: pin A routed to IRQ 150
IOMMU group: 9
Region 0: Memory at f2200000 (64-bit, non-prefetchable) [size=8K]
Capabilities: [c8] Power Management version 3
@@ -309,8 +313,8 @@
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=30us PortTPowerOnTime=18us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
- T_CommonMode=0us LTR1.2_Threshold=0ns
- L1SubCtl2: T_PwrOn=10us
+ T_CommonMode=0us LTR1.2_Threshold=54272ns
+ L1SubCtl2: T_PwrOn=18us
Kernel driver in use: iwlwifi
Kernel modules: iwlwifi@@ -318,10 +322,10 @@
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0
- Interrupt: pin A routed to IRQ 132
- IOMMU group: 11
+ Interrupt: pin A routed to IRQ 106
+ IOMMU group: 10
Bus: primary=40, secondary=41, subordinate=41, sec-latency=0- I/O behind bridge: 200000-200fff [size=4K] [16-bit]
+ I/O behind bridge: 100000-100fff [size=4K] [16-bit]
Memory behind bridge: f4200000-f42fffff [size=1M] [32-bit] Prefetchable memory behind bridge:
00000000fff00000-00000000000fffff [disabled] [64-bit]
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- <SERR- <PERR-
@@ -391,9 +395,11 @@
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: 0
Capabilities: [180 v1] L1 PM Substates
- L1SubCap: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2-
ASPM_L1.1- L1_PM_Substates-
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
- L1SubCtl2:
+ T_CommonMode=150us LTR1.2_Threshold=306176ns
+ L1SubCtl2: T_PwrOn=150us
Capabilities: [190 v1] Vendor Specific Information: ID=0002
Rev=4 Len=100 <?>
Kernel driver in use: pcieport
Kernel modules: pci_endpoint_test
@@ -403,9 +409,9 @@
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
- Interrupt: pin A routed to IRQ 129
- IOMMU group: 11
- Region 0: I/O ports at 200000 [size=256]
+ Interrupt: pin A routed to IRQ 105
+ IOMMU group: 10
+ Region 0: I/O ports at 100000 [size=256]
Region 2: Memory at f4200000 (64-bit, non-prefetchable) [size=64K]
Region 4: Memory at f4210000 (64-bit, non-prefetchable) [size=16K]
Capabilities: [40] Power Management version 3
@@ -482,8 +488,8 @@
L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+
ASPM_L1.1+ L1_PM_Substates+
PortCommonModeRestoreTime=150us PortTPowerOnTime=150us
L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-- T_CommonMode=0us LTR1.2_Threshold=0ns
- L1SubCtl2: T_PwrOn=10us
+ T_CommonMode=0us LTR1.2_Threshold=306176ns
+ L1SubCtl2: T_PwrOn=150us
Capabilities: [21c v1] Vendor Specific Information: ID=0002
Rev=4 Len=100 <?>
Kernel driver in use: r8169
Kernel modules: r8169
Thanks
-Anand