FAILED: patch "[PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET" failed to apply to 6.19-stable tree
[email protected]
maintainerThe patch below does not apply to the 6.19-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.19.y
git checkout FETCH_HEAD
git cherry-pick -x 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026031712-strep-autopilot-0999@gregkh' --subject-prefix 'PATCH 6.19.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <[email protected]>
Date: Wed, 4 Mar 2026 13:30:11 +0200
Subject: [PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET
mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
There are slice row per frame and pic height parameters in DSC that needs to be configured on every Selective Update in Early Transport mode. Use helper provided by DSC code to configure these on Selective Update when in Early Transport mode. Also fill crtc_state->psr2_su_area with full frame area on full frame update for DSC calculation.
v2: move psr2_su_area under skip_sel_fetch_set_loop label
Bspec: 68927, 71709
drivers/gpu/drm/i915/display/intel_psr.c +10 -0
@@ -2619,6 +2619,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,intel_de_write_dsb (display, dsb,PIPE_SRCSZ_ERLY_TPT (crtc->pipe), crtc_state->pipe_srcsz_early_tpt); + +if (!crtc_state->dsc.compression_enable) +return ; + +intel_dsc_su_et_parameters_configure (dsb, encoder, crtc_state, +drm_rect_height (&crtc_state->psr2_su_area)); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -3040,6 +3046,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, } skip_sel_fetch_set_loop: +if (full_update) +clip_area_update (&crtc_state->psr2_su_area, &crtc_state->pipe_src, + &crtc_state->pipe_src); +psr2_man_trk_ctl_calc (crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt =psr2_pipe_srcsz_early_tpt_calc (crtc_state, full_update);
Quoted 6 lines · On Tue, 2026-03-17 at 14:25 +0100, [email protected] wrote:
The patch below does not apply to the 6.19-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit
id to <[email protected]>.
You can solve this by first cherry-picking two dependencies:
c2c79c6d5b939ae8a42ddb884f576bddae685672 (drm/i915/dsc: Add Selective Update register definition)
bb5f1cd10101c2567bff4d0e760b74aee7c42f44 (drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters)
and only after that the fix itself:
5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 (drm/i915/psr: Write DSC parameters on Selective Update in ET mode)
BR,
Jouni Högander
Quoted 97 lines
To reproduce the conflict and resubmit, you may use the following commands:
git fetch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ lin
ux-6.19.y
git checkoutFETCH_HEAD
git cherry-pick -x5923a6e0459fdd3edac4ad5abccb24d777d8f1b6# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026031712-strep-autopilot-0999@gregkh' --subject-prefix 'PATCH 6.19.y' HEAD^..Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From
5923a6e0459fdd3edac4ad5abccb24d777d8f1b6Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <[email protected]>
Date: Wed, 4 Mar 2026 13:30:11 +0200
Subject: [PATCH] drm/i915/psr: Write DSC parameters on Selective Update in ET
mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bitThere are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fillcrtc_state->psr2_su_areawith full frame
area on full frame update for DSC calculation.v2: move
psr2_su_areaunderskip_sel_fetch_set_looplabelBspec: 68927, 71709
Fixes 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport aspossible")
Cc <[email protected]> # v6.9+Signed-off-by Jouni Högander <[email protected]>Reviewed-by Ankit Nautiyal <[email protected]>Link:
https://patch.msgid.link/[email protected](cherry picked from commit 3140af2fab505a4cd47d516284529bf1585628be)Signed-off-by Tvrtko Ursulin <[email protected]>drivers/gpu/drm/i915/display/intel_psr.c +0
-0@@ -2619,6 +2619,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc-Quoted 1 line
pipe),
crtc_state->pipe_srcsz_early_tpt);drivers/gpu/drm/i915/display/intel_psr.c +5
-0+ +if (!crtc_state->dsc.compression_enable) +return ; + + intel_dsc_su_et_parameters_configure(dsb, encoder,
crtc_state,drivers/gpu/drm/i915/display/intel_psr.c +1
-0+
drm_rect_height(&crtc_state->psr2_su_area));
}
static void psr2_man_trk_ctl_calc(structintel_crtc_state*crtc_state,drivers/gpu/drm/i915/display/intel_psr.c +0
-0@@ -3040,6 +3046,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, }
skip_sel_fetch_set_loop:drivers/gpu/drm/i915/display/intel_psr.c +2
-0+if (full_update) + clip_area_update(&crtc_state->psr2_su_area,
&crtc_state->pipe_src,drivers/gpu/drm/i915/display/intel_psr.c +2
-0+ &crtc_state->pipe_src); +
psr2_man_trk_ctl_calc(crtc_state, full_update);crtc_state->pipe_srcsz_early_tpt=psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
PATCH 1/3 drm/i915/dsc: Add Selective Update register definitions
In reply to [email protected]commit c2c79c6d5b939ae8a42ddb884f576bddae685672 upstream.
Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early Transport configuration.
Bspec: 71709
--- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/gpu/drm/i915/display/intel_vdsc_regs.h +12 -0
@@ -196,6 +196,18 @@#define DSC_PPS18_NSL_BPG_OFFSET (offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)#define DSC_PPS18_SL_OFFSET_ADJ (offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset) +#define _LNL_DSC0_SU_PARAMETER_SET_0_PA 0x78064 +#define _LNL_DSC1_SU_PARAMETER_SET_0_PA 0x78164 +#define _LNL_DSC0_SU_PARAMETER_SET_0_PB 0x78264 +#define _LNL_DSC1_SU_PARAMETER_SET_0_PB 0x78364 +#define LNL_DSC0_SU_PARAMETER_SET_0 (pipe) _MMIO_PIPE((pipe), _LNL_DSC0_SU_PARAMETER_SET_0_PA, _LNL_DSC0_SU_PARAMETER_SET_0_PB) +#define LNL_DSC1_SU_PARAMETER_SET_0 (pipe) _MMIO_PIPE((pipe), _LNL_DSC1_SU_PARAMETER_SET_0_PA, _LNL_DSC1_SU_PARAMETER_SET_0_PB) + +#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK REG_GENMASK(31, 20) +#define DSC_SUPS0_SU_SLICE_ROW_PER_FRAME (rows) REG_FIELD_PREP(DSC_SUPS0_SU_SLICE_ROW_PER_FRAME_MASK, (rows)) +#define DSC_SUPS0_SU_PIC_HEIGHT_MASK REG_GENMASK(15, 0) +#define DSC_SUPS0_SU_PIC_HEIGHT (h) REG_FIELD_PREP(DSC_SUPS0_SU_PIC_HEIGHT_MASK, (h)) +/* Icelake Rate Control Buffer Threshold Registers */ #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
Signature · 1 line
2.43.0
PATCH 2/3 drm/i915/dsc: Add helper for writing DSC Selective Update ET parameters
commit bb5f1cd10101c2567bff4d0e760b74aee7c42f44 upstream.
There are slice row per frame and pic height configuration in DSC Selective Update Parameter Set 1 register. Add helper for configuring these.
v2:
- Add WARN_ON_ONCE if vdsc instances per pipe > 2
- instead of checking vdsc instances per pipe being > 1 check == 2
Bspec: 71709
--- drivers/gpu/drm/i915/display/intel_vdsc.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 3 +++ 2 files changed, 26 insertions(+)
drivers/gpu/drm/i915/display/intel_vdsc.c +23 -0
@@ -767,6 +767,29 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder, sizeof(dp_dsc_pps_sdp)); } +void intel_dsc_su_et_parameters_configure (struct intel_dsb *dsb,struct intel_encoder *encoder, +const struct intel_crtc_state *crtc_state,int su_lines) +{ +struct intel_display *display =to_intel_display (crtc_state); +struct intel_crtc *crtc =to_intel_crtc (crtc_state->uapi.crtc); +const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; +enum pipe pipe = crtc->pipe; +int vdsc_instances_per_pipe =intel_dsc_get_vdsc_per_pipe (crtc_state); +int slice_row_per_frame = su_lines / vdsc_cfg->slice_height; +u32 val; + +drm_WARN_ON_ONCE (display->drm, su_lines % vdsc_cfg->slice_height); +drm_WARN_ON_ONCE (display->drm, vdsc_instances_per_pipe >2 ); + + val =DSC_SUPS0_SU_SLICE_ROW_PER_FRAME (slice_row_per_frame); + val |=DSC_SUPS0_SU_PIC_HEIGHT (su_lines); + +intel_de_write_dsb (display, dsb,LNL_DSC0_SU_PARAMETER_SET_0 (pipe), val); + +if (vdsc_instances_per_pipe ==2 ) +intel_de_write_dsb (display, dsb,LNL_DSC1_SU_PARAMETER_SET_0 (pipe), val); +} +static i915_reg_t dss_ctl1_reg (struct intel_crtc *crtc,enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ?
drivers/gpu/drm/i915/display/intel_vdsc.h +3 -0
@@ -13,6 +13,7 @@ struct drm_printer;enum transcoder ;struct intel_crtc ;struct intel_crtc_state ; +struct intel_dsb ;struct intel_encoder ;bool intel_dsc_source_support (const struct intel_crtc_state *crtc_state);
@@ -31,6 +32,8 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state);void intel_dsc_dp_pps_write (struct intel_encoder *encoder,const struct intel_crtc_state *crtc_state); +void intel_dsc_su_et_parameters_configure (struct intel_dsb *dsb,struct intel_encoder *encoder, +const struct intel_crtc_state *crtc_state,int su_lines);void intel_vdsc_state_dump (struct drm_printer *p,int indent,const struct intel_crtc_state *crtc_state);int intel_vdsc_min_cdclk (const struct intel_crtc_state *crtc_state);
Signature · 1 line
2.43.0
PATCH 3/3 drm/i915/psr: Write DSC parameters on Selective Update in ET mode
In reply to Jouni Högandercommit 5923a6e0459fdd3edac4ad5abccb24d777d8f1b6 upstream.
There are slice row per frame and pic height parameters in DSC that needs to be configured on every Selective Update in Early Transport mode. Use helper provided by DSC code to configure these on Selective Update when in Early Transport mode. Also fill crtc_state->psr2_su_area with full frame area on full frame update for DSC calculation.
v2: move psr2_su_area under skip_sel_fetch_set_loop label
Bspec: 68927, 71709
--- drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
drivers/gpu/drm/i915/display/intel_psr.c +10 -0
@@ -2597,6 +2597,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,intel_de_write_dsb (display, dsb,PIPE_SRCSZ_ERLY_TPT (crtc->pipe), crtc_state->pipe_srcsz_early_tpt); + +if (!crtc_state->dsc.compression_enable) +return ; + +intel_dsc_su_et_parameters_configure (dsb, encoder, crtc_state, +drm_rect_height (&crtc_state->psr2_su_area)); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -2991,6 +2997,10 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, } skip_sel_fetch_set_loop: +if (full_update) +clip_area_update (&crtc_state->psr2_su_area, &crtc_state->pipe_src, + &crtc_state->pipe_src); +psr2_man_trk_ctl_calc (crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt =psr2_pipe_srcsz_early_tpt_calc (crtc_state, full_update);
Signature · 1 line
2.43.0