dt-bindings: clock: fsl-sai: Document i.MX8M support
Subsystems (2)
PATCH v3 1/4 dt-bindings: clock: fsl-sai: Document i.MX8M support
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Document support for the i.MX8M variant of the IP with this register shift and additional clock. Update the description slightly.
---
Cc: Conor Dooley <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
V2: No change
V3: - Rebase on current next, update mail address
- Pick ancient AB from Conor, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/
- Invert the allOf conditional to match on VF610 and limit the clocks/clock-names there. MX8M can have one or two input clock, "bus" is mandatory and "mclk1" is optional. The "mclk1" are used by the driver in 4/4 .
--- .../bindings/clock/fsl,sai-clock.yaml | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml +35 -6
@@ -10,10 +10,10 @@ maintainers: - Michael Walle <[email protected]> description: | - It is possible to use the BCLK pin of a SAI module as a generic clock - output. Some SoC are very constrained in their pin multiplexer - configuration. Eg. pins can only be changed groups. For example, on the - LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, + It is possible to use the BCLK pin of a SAI module as a generic + clock output. Some SoC are very constrained in their pin multiplexer + configuration. E.g. pins can only be changed in groups. For example, on + the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI, the second pins are wasted. Using this binding it is possible to use the clock of the second SAI as a MCLK clock for an audio codec, for example.
@@ -21,17 +21,46 @@ description: | properties: compatible: - const: fsl,vf610-sai-clock + oneOf: + - items: + - enum: + - fsl,imx8mm-sai-clock + - fsl,imx8mn-sai-clock + - fsl,imx8mp-sai-clock + - const: fsl,imx8mq-sai-clock + - items: + - enum: + - fsl,imx8mq-sai-clock + - fsl,vf610-sai-clock reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: bus + - const: mclk1 '#clock-cells': const: 0 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,vf610-sai-clock + then: + properties: + clocks: + maxItems: 1 + clock-names: false + required: - compatible - reg
Signature · 1 line
2.53.0
PATCH v3 2/4 clk: fsl-sai: Add i.MX8M support with 8 byte register offset
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Add support for the i.MX8M variant of the IP with this register shift and additional clock.
---
Cc: Conor Dooley <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
V2: Update commit message, align it with the bindings one
V3: - Rebase on current next, update mail address
- Pick ancient RB from Peng, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/
- Optionally enable "bus" clock, which are needed on MX8M to operate register file
--- drivers/clk/Kconfig | 2 +- drivers/clk/clk-fsl-sai.c | 27 +++++++++++++++++++++++---- 2 files changed, 24 insertions(+), 5 deletions(-)
drivers/clk/Kconfig +1 -1
@@ -255,7 +255,7 @@ config COMMON_CLK_FSL_FLEXSPI config COMMON_CLK_FSL_SAI bool "Clock driver for BCLK of Freescale SAI cores" - depends on ARCH_LAYERSCAPE || COMPILE_TEST + depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST help This driver supports the Freescale SAI (Synchronous Audio Interface) to be used as a generic clock output. Some SoCs have restrictions
drivers/clk/clk-fsl-sai.c +23 -4
@@ -26,11 +26,17 @@ struct fsl_sai_clk {spinlock_t lock; }; +struct fsl_sai_data { +unsigned int offset;/* Register offset */ +}; +static int fsl_sai_clk_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev; +const struct fsl_sai_data *data =device_get_match_data (dev);struct fsl_sai_clk *sai_clk;struct clk_parent_data pdata = { .index =0 }; +struct clk *clk_bus;void __iomem *base;struct clk_hw *hw;
@@ -42,19 +48,23 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)if (IS_ERR (base))return PTR_ERR (base); + clk_bus =devm_clk_get_optional_enabled (dev,"bus" ); +if (IS_ERR (clk_bus)) +return PTR_ERR (clk_bus); +spin_lock_init (&sai_clk->lock); - sai_clk->gate.reg = base +I2S_CSR ; + sai_clk->gate.reg = base + data->offset +I2S_CSR ; sai_clk->gate.bit_idx =CSR_BCE_BIT ; sai_clk->gate.lock = &sai_clk->lock; - sai_clk->div.reg = base +I2S_CR2 ; + sai_clk->div.reg = base + data->offset +I2S_CR2 ; sai_clk->div.shift =CR2_DIV_SHIFT ; sai_clk->div.width =CR2_DIV_WIDTH ; sai_clk->div.lock = &sai_clk->lock;/* set clock direction, we are the BCLK master */ -writel (CR2_BCD , base +I2S_CR2 ); +writel (CR2_BCD , base + data->offset +I2S_CR2 ); hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name, &pdata, 1, NULL, NULL,
@@ -69,8 +79,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)return devm_of_clk_add_hw_provider (dev, of_clk_hw_simple_get, hw); } +static const struct fsl_sai_data fsl_sai_vf610_data = { + .offset =0 , +}; + +static const struct fsl_sai_data fsl_sai_imx8mq_data = { + .offset =8 , +}; +static const struct of_device_id of_fsl_sai_clk_ids[] = { - { .compatible ="fsl,vf610-sai-clock" }, + { .compatible ="fsl,vf610-sai-clock" , .data = &fsl_sai_vf610_data }, + { .compatible ="fsl,imx8mq-sai-clock" , .data = &fsl_sai_imx8mq_data }, { } };MODULE_DEVICE_TABLE (of, of_fsl_sai_clk_ids);
Signature · 1 line
2.53.0
Re: [PATCH v3 2/4] clk: fsl-sai: Add i.MX8M support with 8 byte register offset
Quoted 7 lines · Marek Vasut
The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers shifted by +8 bytes and requires additional bus clock. Add support for the i.MX8M variant of the IP with this register shift and additional clock.
Reviewed-by Peng Fan <[email protected]>Signed-off-by Marek Vasut <[email protected]>
PATCH v3 3/4 dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
In reply to Marek VasutThe driver now supports generation of both BCLK and MCLK, document support for #clock-cells = <0> for legacy case and #clock-cells = <1> for the new case which can differentiate between BCLK and MCLK.
---
Cc: Conor Dooley <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
V2: Update commit message, align it with the bindings one
V3: - Rebase on current next, update mail address
- Pick ancient AB from Conor, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/
--- Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml +2 -2
@@ -10,7 +10,7 @@ maintainers: - Michael Walle <[email protected]> description: | - It is possible to use the BCLK pin of a SAI module as a generic + It is possible to use the BCLK or MCLK pin of a SAI module as a generic clock output. Some SoC are very constrained in their pin multiplexer configuration. E.g. pins can only be changed in groups. For example, on the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
@@ -47,7 +47,7 @@ properties: - const: mclk1 '#clock-cells': - const: 0 + maximum: 1 allOf: - if:
Signature · 1 line
2.53.0
PATCH v3 4/4 clk: fsl-sai: Add MCLK generation support
In reply to Marek VasutThe driver currently supports generating BCLK. There are systems which require generation of MCLK instead. Register new MCLK clock and handle clock-cells = <1> to differentiate between BCLK and MCLK. In case of a legacy system with clock-cells = <0>, the driver behaves as before, i.e. always returns BCLK.
Note that it is not possible re-use the current SAI audio driver to generate MCLK and correctly enable and disable the MCLK.
If SAI (audio driver) is used to control the MCLK enablement, then MCLK clock is not always enabled, and it is not necessarily enabled when the codec may need the clock to be enabled. There is also no way for the codec node to specify phandle to clock provider in DT, because the SAI (audio driver) is not clock provider.
If SAI (clock driver) is used to control the MCLK enablement, then MCLK clock is enabled when the codec needs the clock enabled, because the codec is the clock consumer and the SAI (clock driver) is the clock provider, and the codec driver can request the clock to be enabled when needed. There is also the usual phandle to clock provider in DT, because the SAI (clock driver) is clock provider.
---
Cc: Conor Dooley <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
V2: No change
V3: - Rebase on current next, update mail address
- Update commit message according to clarify the difference between SAI audio and SAI clock driver
- Pick ancient AB from Michael, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/
--- drivers/clk/clk-fsl-sai.c | 74 ++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 13 deletions(-)
drivers/clk/clk-fsl-sai.c +61 -13
@@ -7,6 +7,7 @@#include <linux/module.h> #include <linux/platform_device.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/of.h>
@@ -15,21 +16,37 @@#define I2S_CSR 0x00#define I2S_CR2 0x08 +#define I2S_MCR 0x100#define CSR_BCE_BIT 28 +#define CSR_TE_BIT 31#define CR2_BCD BIT(24)#define CR2_DIV_SHIFT 0#define CR2_DIV_WIDTH 8 +#define MCR_MOE BIT(30)struct fsl_sai_clk { -struct clk_divider div; -struct clk_gate gate; +struct clk_divider bclk_div; +struct clk_divider mclk_div; +struct clk_gate bclk_gate; +struct clk_gate mclk_gate; +struct clk_hw *bclk_hw; +struct clk_hw *mclk_hw;spinlock_t lock; };struct fsl_sai_data {unsigned int offset;/* Register offset */ +bool have_mclk;/* Have MCLK control */ }; +static struct clk_hw * +fsl_sai_of_clk_get (struct of_phandle_args *clkspec,void *data) +{ +struct fsl_sai_clk *sai_clk = data; + +return clkspec->args[0 ] ? sai_clk->mclk_hw : sai_clk->bclk_hw; +} +static int fsl_sai_clk_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev;
@@ -54,37 +71,68 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)spin_lock_init (&sai_clk->lock); - sai_clk->gate.reg = base + data->offset +I2S_CSR ; - sai_clk->gate.bit_idx =CSR_BCE_BIT ; - sai_clk->gate.lock = &sai_clk->lock; + sai_clk->bclk_gate.reg = base + data->offset +I2S_CSR ; + sai_clk->bclk_gate.bit_idx =CSR_BCE_BIT ; + sai_clk->bclk_gate.lock = &sai_clk->lock; - sai_clk->div.reg = base + data->offset +I2S_CR2 ; - sai_clk->div.shift =CR2_DIV_SHIFT ; - sai_clk->div.width =CR2_DIV_WIDTH ; - sai_clk->div.lock = &sai_clk->lock; + sai_clk->bclk_div.reg = base + data->offset +I2S_CR2 ; + sai_clk->bclk_div.shift =CR2_DIV_SHIFT ; + sai_clk->bclk_div.width =CR2_DIV_WIDTH ; + sai_clk->bclk_div.lock = &sai_clk->lock;/* set clock direction, we are the BCLK master */ writel (CR2_BCD , base + data->offset +I2S_CR2 ); - hw =devm_clk_hw_register_composite_pdata (dev, dev->of_node->name, + hw =devm_clk_hw_register_composite_pdata (dev,"BCLK" , &pdata,1 ,NULL ,NULL , - &sai_clk->div.hw, + &sai_clk->bclk_div.hw, &clk_divider_ops, - &sai_clk->gate.hw, + &sai_clk->bclk_gate.hw, &clk_gate_ops,CLK_SET_RATE_GATE );if (IS_ERR (hw))return PTR_ERR (hw); -return devm_of_clk_add_hw_provider (dev, of_clk_hw_simple_get, hw); + sai_clk->bclk_hw = hw; + +if (data->have_mclk) { + sai_clk->mclk_gate.reg = base + data->offset +I2S_CSR ; + sai_clk->mclk_gate.bit_idx =CSR_TE_BIT ; + sai_clk->mclk_gate.lock = &sai_clk->lock; + + sai_clk->mclk_div.reg = base +I2S_MCR ; + sai_clk->mclk_div.shift =CR2_DIV_SHIFT ; + sai_clk->mclk_div.width =CR2_DIV_WIDTH ; + sai_clk->mclk_div.lock = &sai_clk->lock; + + pdata.index =1 ;/* MCLK1 */ + hw =devm_clk_hw_register_composite_pdata (dev,"MCLK" , + &pdata,1 ,NULL ,NULL , + &sai_clk->mclk_div.hw, + &clk_divider_ops, + &sai_clk->mclk_gate.hw, + &clk_gate_ops, +CLK_SET_RATE_GATE ); +if (IS_ERR (hw)) +return PTR_ERR (hw); + + sai_clk->mclk_hw = hw; + +/* set clock direction, we are the MCLK output */ +writel (MCR_MOE , base +I2S_MCR ); + } + +return devm_of_clk_add_hw_provider (dev, fsl_sai_of_clk_get, sai_clk); }static const struct fsl_sai_data fsl_sai_vf610_data = { .offset =0 , + .have_mclk = false, };static const struct fsl_sai_data fsl_sai_imx8mq_data = { .offset =8 , + .have_mclk = true, };static const struct of_device_id of_fsl_sai_clk_ids[] = {
Signature · 1 line
2.53.0
Re: [PATCH v3 4/4] clk: fsl-sai: Add MCLK generation support
Hi Marek,
Quoted 50 lines · Marek Vasut
The driver currently supports generating BCLK. There are systems which require generation of MCLK instead. Register new MCLK clock and handle clock-cells = <1> to differentiate between BCLK and MCLK. In case of a legacy system with clock-cells = <0>, the driver behaves as before, i.e. always returns BCLK.
Note that it is not possible re-use the current SAI audio driver to generate MCLK and correctly enable and disable the MCLK.
If SAI (audio driver) is used to control the MCLK enablement, then MCLK clock is not always enabled, and it is not necessarily enabled when the codec may need the clock to be enabled. There is also no way for the codec node to specify phandle to clock provider in DT, because the SAI (audio driver) is not clock provider.
If SAI (clock driver) is used to control the MCLK enablement, then MCLK clock is enabled when the codec needs the clock enabled, because the codec is the clock consumer and the SAI (clock driver) is the clock provider, and the codec driver can request the clock to be enabled when needed. There is also the usual phandle to clock provider in DT, because the SAI (clock driver) is clock provider.
Acked-by Michael Walle <[email protected]>Signed-off-by Marek Vasut <[email protected]>---
Cc: Conor Dooley <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Michael Walle <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
V2: No change
V3: - Rebase on current next, update mail address
- Update commit message according to clarify the difference between SAI audio and SAI clock driver
- Pick ancient AB from Michael, although this may be outdated
https://patchwork.kernel.org/project/alsa-devel/patch/[email protected]/--- drivers/clk/clk-fsl-sai.c | 74 ++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 13 deletions(-)drivers/clk/clk-fsl-sai.c +0
-0
drivers/clk/clk-fsl-sai.c line 13
Quoted 7 lines
drivers/clk/clk-fsl-sai.c +1
-0@@ -7,6 +7,7 @@#include <linux/module.h> #include <linux/platform_device.h> +#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/of.h>
Since changes are being made here, could the includes be sorted in a separate patch?
Quoted 55 lines
drivers/clk/clk-fsl-sai.c +21
-9@@ -15,21 +16,37 @@#define I2S_CSR 0x00#define I2S_CR2 0x08 +#define I2S_MCR 0x100#define CSR_BCE_BIT 28 +#define CSR_TE_BIT 31#define CR2_BCD BIT(24)#define CR2_DIV_SHIFT 0#define CR2_DIV_WIDTH 8 +#define MCR_MOE BIT(30)struct fsl_sai_clk { -struct clk_divider div; -struct clk_gate gate; +struct clk_divider bclk_div; +struct clk_divider mclk_div; +struct clk_gate bclk_gate; +struct clk_gate mclk_gate; +struct clk_hw *bclk_hw; +struct clk_hw *mclk_hw;spinlock_t lock; };struct fsl_sai_data {unsigned int offset;/* Register offset */ +bool have_mclk;/* Have MCLK control */ }; +static struct clk_hw * +fsl_sai_of_clk_get (struct of_phandle_args *clkspec,void *data) +{ +struct fsl_sai_clk *sai_clk = data; + +return clkspec->args[0 ] ? sai_clk->mclk_hw : sai_clk->bclk_hw; +} +static int fsl_sai_clk_probe (struct platform_device *pdev) {struct device *dev = &pdev->dev;@@ -54,37 +71,68 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)spin_lock_init (&sai_clk->lock); - sai_clk->gate.reg = base + data->offset +I2S_CSR ; - sai_clk->gate.bit_idx =CSR_BCE_BIT ; - sai_clk->gate.lock = &sai_clk->lock; + sai_clk->bclk_gate.reg = base + data->offset +I2S_CSR ; + sai_clk->bclk_gate.bit_idx =CSR_BCE_BIT ; + sai_clk->bclk_gate.lock = &sai_clk->lock; - sai_clk->div.reg = base + data->offset +I2S_CR2 ; - sai_clk->div.shift =CR2_DIV_SHIFT ; - sai_clk->div.width =CR2_DIV_WIDTH ; - sai_clk->div.lock = &sai_clk->lock;
drivers/clk/clk-fsl-sai.c static int fsl_sai_clk_probe(struct platform_device *pdev) · line 86
Quoted 10 lines
drivers/clk/clk-fsl-sai.c +5
-1+ sai_clk->bclk_div.reg = base + data->offset +I2S_CR2 ; + sai_clk->bclk_div.shift =CR2_DIV_SHIFT ; + sai_clk->bclk_div.width =CR2_DIV_WIDTH ; + sai_clk->bclk_div.lock = &sai_clk->lock;/* set clock direction, we are the BCLK master */ writel (CR2_BCD , base + data->offset +I2S_CR2 ); - hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name, + hw = devm_clk_hw_register_composite_pdata(dev, "BCLK",
Will there ever be multiple instances of this IP block on a system? If so, the hardcoded BCLK and MCLK clk names will collide.
Quoted 26 lines
drivers/clk/clk-fsl-sai.c +16
-3&pdata,1 ,NULL ,NULL , - &sai_clk->div.hw, + &sai_clk->bclk_div.hw, &clk_divider_ops, - &sai_clk->gate.hw, + &sai_clk->bclk_gate.hw, &clk_gate_ops, CLK_SET_RATE_GATE);if (IS_ERR (hw))return PTR_ERR (hw); -return devm_of_clk_add_hw_provider (dev, of_clk_hw_simple_get, hw); + sai_clk->bclk_hw = hw; + +if (data->have_mclk) { + sai_clk->mclk_gate.reg = base + data->offset +I2S_CSR ; + sai_clk->mclk_gate.bit_idx =CSR_TE_BIT ; + sai_clk->mclk_gate.lock = &sai_clk->lock; + + sai_clk->mclk_div.reg = base +I2S_MCR ; + sai_clk->mclk_div.shift =CR2_DIV_SHIFT ; + sai_clk->mclk_div.width =CR2_DIV_WIDTH ; + sai_clk->mclk_div.lock = &sai_clk->lock; + + pdata.index =1 ;/* MCLK1 */ + hw = devm_clk_hw_register_composite_pdata(dev, "MCLK",
drivers/clk/clk-fsl-sai.c static int fsl_sai_clk_probe(struct platform_device *pdev) · line 119
Quoted 10 lines
drivers/clk/clk-fsl-sai.c +10
-0+ &pdata,1 ,NULL ,NULL , + &sai_clk->mclk_div.hw, + &clk_divider_ops, + &sai_clk->mclk_gate.hw, + &clk_gate_ops, + CLK_SET_RATE_GATE); +if (IS_ERR (hw)) +return PTR_ERR (hw); + + sai_clk->mclk_hw = hw;
This section is basically a copy/paste of the bclk from above, with a few minor changes (bclk renamed to mclk, different gate and div regs, and a different base offset). What do you think about mostly keeping struct fsl_sai_clk with the same names, and add a new helper to do the registrations?
Brian
Quoted 22 lines
drivers/clk/clk-fsl-sai.c +8
-0+ +/* set clock direction, we are the MCLK output */ +writel (MCR_MOE , base +I2S_MCR ); + } + +return devm_of_clk_add_hw_provider (dev, fsl_sai_of_clk_get, sai_clk); }static const struct fsl_sai_data fsl_sai_vf610_data = { .offset =0 , + .have_mclk = false, };static const struct fsl_sai_data fsl_sai_imx8mq_data = { .offset =8 , + .have_mclk = true, };static const struct of_device_id of_fsl_sai_clk_ids[] = {Signature · 1 line
2.53.0